[qemu.git] / hw / milkymist-minimac.c

/*
 *  QEMU model of the Milkymist minimac block.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://www.milkymist.org/socdoc/minimac.pdf
 *
 */

#include "hw.h"
#include "sysbus.h"
#include "trace.h"
#include "net.h"
#include "qemu-error.h"

#include <zlib.h>

enum {
    R_SETUP = 0,
    R_MDIO,
    R_STATE0,
    R_ADDR0,
    R_COUNT0,
    R_STATE1,
    R_ADDR1,
    R_COUNT1,
    R_STATE2,
    R_ADDR2,
    R_COUNT2,
    R_STATE3,
    R_ADDR3,
    R_COUNT3,
    R_TXADDR,
    R_TXCOUNT,
    R_MAX
};

enum {
    SETUP_RX_RST = (1<<0),
    SETUP_TX_RST = (1<<2),
};

enum {
    MDIO_DO  = (1<<0),
    MDIO_DI  = (1<<1),
    MDIO_OE  = (1<<2),
    MDIO_CLK = (1<<3),
};

enum {
    STATE_EMPTY   = 0,
    STATE_LOADED  = 1,
    STATE_PENDING = 2,
};

enum {
    MDIO_OP_WRITE = 1,
    MDIO_OP_READ  = 2,
};

enum mdio_state {
    MDIO_STATE_IDLE,
    MDIO_STATE_READING,
    MDIO_STATE_WRITING,
};

enum {
    R_PHY_ID1  = 2,
    R_PHY_ID2  = 3,
    R_PHY_MAX  = 32
};

#define MINIMAC_MTU 1530

struct MilkymistMinimacMdioState {
    int last_clk;
    int count;
    uint32_t data;
    uint16_t data_out;
    int state;

    uint8_t phy_addr;
    uint8_t reg_addr;
};
typedef struct MilkymistMinimacMdioState MilkymistMinimacMdioState;

struct MilkymistMinimacState {
    SysBusDevice busdev;
    NICState *nic;
    NICConf conf;
    char *phy_model;

    qemu_irq rx_irq;
    qemu_irq tx_irq;

    uint32_t regs[R_MAX];

    MilkymistMinimacMdioState mdio;

    uint16_t phy_regs[R_PHY_MAX];
};
typedef struct MilkymistMinimacState MilkymistMinimacState;

static const uint8_t preamble_sfd[] = {
        0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
};

static void minimac_mdio_write_reg(MilkymistMinimacState *s,
        uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
{
    trace_milkymist_minimac_mdio_write(phy_addr, reg_addr, value);

    /* nop */
}

static uint16_t minimac_mdio_read_reg(MilkymistMinimacState *s,
        uint8_t phy_addr, uint8_t reg_addr)
{
    uint16_t r = s->phy_regs[reg_addr];

    trace_milkymist_minimac_mdio_read(phy_addr, reg_addr, r);

    return r;
}

static void minimac_update_mdio(MilkymistMinimacState *s)
{
    MilkymistMinimacMdioState *m = &s->mdio;

    /* detect rising clk edge */
    if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
        /* shift data in */
        int bit = ((s->regs[R_MDIO] & MDIO_DO)
                   && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
        m->data = (m->data << 1) | bit;

        /* check for sync */
        if (m->data == 0xffffffff) {
            m->count = 32;
        }

        if (m->count == 16) {
            uint8_t start = (m->data >> 14) & 0x3;
            uint8_t op = (m->data >> 12) & 0x3;
            uint8_t ta = (m->data) & 0x3;

            if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
                m->state = MDIO_STATE_WRITING;
            } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
                m->state = MDIO_STATE_READING;
            } else {
                m->state = MDIO_STATE_IDLE;
            }

            if (m->state != MDIO_STATE_IDLE) {
                m->phy_addr = (m->data >> 7) & 0x1f;
                m->reg_addr = (m->data >> 2) & 0x1f;
            }

            if (m->state == MDIO_STATE_READING) {
                m->data_out = minimac_mdio_read_reg(s, m->phy_addr,
                        m->reg_addr);
            }
        }

        if (m->count < 16 && m->state == MDIO_STATE_READING) {
            int bit = (m->data_out & 0x8000) ? 1 : 0;
            m->data_out <<= 1;

            if (bit) {
                s->regs[R_MDIO] |= MDIO_DI;
            } else {
                s->regs[R_MDIO] &= ~MDIO_DI;
            }
        }

        if (m->count == 0 && m->state) {
            if (m->state == MDIO_STATE_WRITING) {
                uint16_t data = m->data & 0xffff;
                minimac_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
            }
            m->state = MDIO_STATE_IDLE;
        }
        m->count--;
    }

    m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
}

static size_t assemble_frame(uint8_t *buf, size_t size,
        const uint8_t *payload, size_t payload_size)
{
    uint32_t crc;

    if (size < payload_size + 12) {
        error_report("milkymist_minimac: received too big ethernet frame");
        return 0;
    }

    /* prepend preamble and sfd */
    memcpy(buf, preamble_sfd, 8);

    /* now copy the payload */
    memcpy(buf + 8, payload, payload_size);

    /* pad frame if needed */
    if (payload_size < 60) {
        memset(buf + payload_size + 8, 0, 60 - payload_size);
        payload_size = 60;
    }

    /* append fcs */
    crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
    memcpy(buf + payload_size + 8, &crc, 4);

    return payload_size + 12;
}

static void minimac_tx(MilkymistMinimacState *s)
{
    uint8_t buf[MINIMAC_MTU];
    uint32_t txcount = s->regs[R_TXCOUNT];

    /* do nothing if transmission logic is in reset */
    if (s->regs[R_SETUP] & SETUP_TX_RST) {
        return;
    }

    if (txcount < 64) {
        error_report("milkymist_minimac: ethernet frame too small (%u < %u)\n",
                txcount, 64);
        return;
    }

    if (txcount > MINIMAC_MTU) {
        error_report("milkymist_minimac: MTU exceeded (%u > %u)\n",
                txcount, MINIMAC_MTU);
        return;
    }

    /* dma */
    cpu_physical_memory_read(s->regs[R_TXADDR], buf, txcount);

    if (memcmp(buf, preamble_sfd, 8) != 0) {
        error_report("milkymist_minimac: frame doesn't contain the preamble "
                "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)\n",
                buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
        return;
    }

    trace_milkymist_minimac_tx_frame(txcount - 12);

    /* send packet, skipping preamble and sfd */
    qemu_send_packet_raw(&s->nic->nc, buf + 8, txcount - 12);

    s->regs[R_TXCOUNT] = 0;

    trace_milkymist_minimac_pulse_irq_tx();
    qemu_irq_pulse(s->tx_irq);
}

static ssize_t minimac_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
{
    MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;

    uint32_t r_addr;
    uint32_t r_count;
    uint32_t r_state;

    uint8_t frame_buf[MINIMAC_MTU];
    size_t frame_size;

    trace_milkymist_minimac_rx_frame(buf, size);

    /* discard frames if nic is in reset */
    if (s->regs[R_SETUP] & SETUP_RX_RST) {
        return size;
    }

    /* choose appropriate slot */
    if (s->regs[R_STATE0] == STATE_LOADED) {
        r_addr = R_ADDR0;
        r_count = R_COUNT0;
        r_state = R_STATE0;
    } else if (s->regs[R_STATE1] == STATE_LOADED) {
        r_addr = R_ADDR1;
        r_count = R_COUNT1;
        r_state = R_STATE1;
    } else if (s->regs[R_STATE2] == STATE_LOADED) {
        r_addr = R_ADDR2;
        r_count = R_COUNT2;
        r_state = R_STATE2;
    } else if (s->regs[R_STATE3] == STATE_LOADED) {
        r_addr = R_ADDR3;
        r_count = R_COUNT3;
        r_state = R_STATE3;
    } else {
        trace_milkymist_minimac_drop_rx_frame(buf);
        return size;
    }

    /* assemble frame */
    frame_size = assemble_frame(frame_buf, sizeof(frame_buf), buf, size);

    if (frame_size == 0) {
        return size;
    }

    trace_milkymist_minimac_rx_transfer(buf, frame_size);

    /* do dma */
    cpu_physical_memory_write(s->regs[r_addr], frame_buf, frame_size);

    /* update slot */
    s->regs[r_count] = frame_size;
    s->regs[r_state] = STATE_PENDING;

    trace_milkymist_minimac_pulse_irq_rx();
    qemu_irq_pulse(s->rx_irq);

    return size;
}

static uint32_t
minimac_read(void *opaque, target_phys_addr_t addr)
{
    MilkymistMinimacState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_SETUP:
    case R_MDIO:
    case R_STATE0:
    case R_ADDR0:
    case R_COUNT0:
    case R_STATE1:
    case R_ADDR1:
    case R_COUNT1:
    case R_STATE2:
    case R_ADDR2:
    case R_COUNT2:
    case R_STATE3:
    case R_ADDR3:
    case R_COUNT3:
    case R_TXADDR:
    case R_TXCOUNT:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_minimac: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_minimac_memory_read(addr << 2, r);

    return r;
}

static void
minimac_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
    MilkymistMinimacState *s = opaque;

    trace_milkymist_minimac_memory_read(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_MDIO:
    {
        /* MDIO_DI is read only */
        int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
        s->regs[R_MDIO] = value;
        if (mdio_di) {
            s->regs[R_MDIO] |= mdio_di;
        } else {
            s->regs[R_MDIO] &= ~mdio_di;
        }

        minimac_update_mdio(s);
    } break;
    case R_TXCOUNT:
        s->regs[addr] = value;
        if (value > 0) {
            minimac_tx(s);
        }
        break;
    case R_SETUP:
    case R_STATE0:
    case R_ADDR0:
    case R_COUNT0:
    case R_STATE1:
    case R_ADDR1:
    case R_COUNT1:
    case R_STATE2:
    case R_ADDR2:
    case R_COUNT2:
    case R_STATE3:
    case R_ADDR3:
    case R_COUNT3:
    case R_TXADDR:
        s->regs[addr] = value;
        break;

    default:
        error_report("milkymist_minimac: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static CPUReadMemoryFunc * const minimac_read_fn[] = {
    NULL,
    NULL,
    &minimac_read,
};

static CPUWriteMemoryFunc * const minimac_write_fn[] = {
    NULL,
    NULL,
    &minimac_write,
};

static int minimac_can_rx(VLANClientState *nc)
{
    MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;

    /* discard frames if nic is in reset */
    if (s->regs[R_SETUP] & SETUP_RX_RST) {
        return 1;
    }

    if (s->regs[R_STATE0] == STATE_LOADED) {
        return 1;
    }
    if (s->regs[R_STATE1] == STATE_LOADED) {
        return 1;
    }
    if (s->regs[R_STATE2] == STATE_LOADED) {
        return 1;
    }
    if (s->regs[R_STATE3] == STATE_LOADED) {
        return 1;
    }

    return 0;
}

static void minimac_cleanup(VLANClientState *nc)
{
    MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;

    s->nic = NULL;
}

static void milkymist_minimac_reset(DeviceState *d)
{
    MilkymistMinimacState *s =
            container_of(d, MilkymistMinimacState, busdev.qdev);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }
    for (i = 0; i < R_PHY_MAX; i++) {
        s->phy_regs[i] = 0;
    }

    /* defaults */
    s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
    s->phy_regs[R_PHY_ID2] = 0x161a;
}

static NetClientInfo net_milkymist_minimac_info = {
    .type = NET_CLIENT_TYPE_NIC,
    .size = sizeof(NICState),
    .can_receive = minimac_can_rx,
    .receive = minimac_rx,
    .cleanup = minimac_cleanup,
};

static int milkymist_minimac_init(SysBusDevice *dev)
{
    MilkymistMinimacState *s = FROM_SYSBUS(typeof(*s), dev);
    int regs;

    sysbus_init_irq(dev, &s->rx_irq);
    sysbus_init_irq(dev, &s->tx_irq);

    regs = cpu_register_io_memory(minimac_read_fn, minimac_write_fn, s,
            DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, regs);

    qemu_macaddr_default_if_unset(&s->conf.macaddr);
    s->nic = qemu_new_nic(&net_milkymist_minimac_info, &s->conf,
                          dev->qdev.info->name, dev->qdev.id, s);
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);

    return 0;
}

static const VMStateDescription vmstate_milkymist_minimac_mdio = {
    .name = "milkymist_minimac_mdio",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_INT32(last_clk, MilkymistMinimacMdioState),
        VMSTATE_INT32(count, MilkymistMinimacMdioState),
        VMSTATE_UINT32(data, MilkymistMinimacMdioState),
        VMSTATE_UINT16(data_out, MilkymistMinimacMdioState),
        VMSTATE_INT32(state, MilkymistMinimacMdioState),
        VMSTATE_UINT8(phy_addr, MilkymistMinimacMdioState),
        VMSTATE_UINT8(reg_addr, MilkymistMinimacMdioState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_milkymist_minimac = {
    .name = "milkymist-minimac",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistMinimacState, R_MAX),
        VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimacState, R_PHY_MAX),
        VMSTATE_STRUCT(mdio, MilkymistMinimacState, 0,
                vmstate_milkymist_minimac_mdio, MilkymistMinimacMdioState),
        VMSTATE_END_OF_LIST()
    }
};

static SysBusDeviceInfo milkymist_minimac_info = {
    .init = milkymist_minimac_init,
    .qdev.name  = "milkymist-minimac",
    .qdev.size  = sizeof(MilkymistMinimacState),
    .qdev.vmsd  = &vmstate_milkymist_minimac,
    .qdev.reset = milkymist_minimac_reset,
    .qdev.props = (Property[]) {
        DEFINE_NIC_PROPERTIES(MilkymistMinimacState, conf),
        DEFINE_PROP_STRING("phy_model", MilkymistMinimacState, phy_model),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void milkymist_minimac_register(void)
{
    sysbus_register_withprop(&milkymist_minimac_info);
}

device_init(milkymist_minimac_register)
Commit	Line	Data
07424544 MW	1	/*
	2	* QEMU model of the Milkymist minimac block.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
	21	* http://www.milkymist.org/socdoc/minimac.pdf
	22	*
	23	*/
	24
	25	#include "hw.h"
	26	#include "sysbus.h"
	27	#include "trace.h"
	28	#include "net.h"
	29	#include "qemu-error.h"
	30
	31	#include <zlib.h>
	32
	33	enum {
	34	R_SETUP = 0,
	35	R_MDIO,
	36	R_STATE0,
	37	R_ADDR0,
	38	R_COUNT0,
	39	R_STATE1,
	40	R_ADDR1,
	41	R_COUNT1,
	42	R_STATE2,
	43	R_ADDR2,
	44	R_COUNT2,
	45	R_STATE3,
	46	R_ADDR3,
	47	R_COUNT3,
	48	R_TXADDR,
	49	R_TXCOUNT,
	50	R_MAX
	51	};
	52
	53	enum {
	54	SETUP_RX_RST = (1<<0),
	55	SETUP_TX_RST = (1<<2),
	56	};
	57
	58	enum {
	59	MDIO_DO = (1<<0),
	60	MDIO_DI = (1<<1),
	61	MDIO_OE = (1<<2),
	62	MDIO_CLK = (1<<3),
	63	};
	64
65	enum {
66	STATE_EMPTY = 0,
67	STATE_LOADED = 1,
68	STATE_PENDING = 2,
69	};
70
71	enum {
72	MDIO_OP_WRITE = 1,
73	MDIO_OP_READ = 2,
74	};
75
76	enum mdio_state {
77	MDIO_STATE_IDLE,
78	MDIO_STATE_READING,
79	MDIO_STATE_WRITING,
80	};
81
82	enum {
83	R_PHY_ID1 = 2,
84	R_PHY_ID2 = 3,
85	R_PHY_MAX = 32
86	};
87
88	#define MINIMAC_MTU 1530
89
90	struct MilkymistMinimacMdioState {
91	int last_clk;
92	int count;
93	uint32_t data;
94	uint16_t data_out;
95	int state;
96
97	uint8_t phy_addr;
98	uint8_t reg_addr;
99	};
100	typedef struct MilkymistMinimacMdioState MilkymistMinimacMdioState;
101
102	struct MilkymistMinimacState {
103	SysBusDevice busdev;
104	NICState *nic;
105	NICConf conf;
106	char *phy_model;
107
108	qemu_irq rx_irq;
109	qemu_irq tx_irq;
110
111	uint32_t regs[R_MAX];
112
113	MilkymistMinimacMdioState mdio;
114
115	uint16_t phy_regs[R_PHY_MAX];
116	};
117	typedef struct MilkymistMinimacState MilkymistMinimacState;
118
119	static const uint8_t preamble_sfd[] = {
120	0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
121	};
122
123	static void minimac_mdio_write_reg(MilkymistMinimacState *s,
124	uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
125	{
126	trace_milkymist_minimac_mdio_write(phy_addr, reg_addr, value);
127
128	/* nop */
129	}
130
131	static uint16_t minimac_mdio_read_reg(MilkymistMinimacState *s,
132	uint8_t phy_addr, uint8_t reg_addr)
133	{
134	uint16_t r = s->phy_regs[reg_addr];
135
136	trace_milkymist_minimac_mdio_read(phy_addr, reg_addr, r);
137
138	return r;
139	}
140
141	static void minimac_update_mdio(MilkymistMinimacState *s)
142	{
143	MilkymistMinimacMdioState *m = &s->mdio;
144
145	/* detect rising clk edge */
146	if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
147	/* shift data in */
148	int bit = ((s->regs[R_MDIO] & MDIO_DO)
149	&& (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
150	m->data = (m->data << 1) \| bit;
151
152	/* check for sync */
153	if (m->data == 0xffffffff) {
154	m->count = 32;
155	}
156
157	if (m->count == 16) {
158	uint8_t start = (m->data >> 14) & 0x3;
159	uint8_t op = (m->data >> 12) & 0x3;
160	uint8_t ta = (m->data) & 0x3;
161
162	if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
163	m->state = MDIO_STATE_WRITING;
164	} else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
165	m->state = MDIO_STATE_READING;
166	} else {
167	m->state = MDIO_STATE_IDLE;
168	}
169
170	if (m->state != MDIO_STATE_IDLE) {
171	m->phy_addr = (m->data >> 7) & 0x1f;
172	m->reg_addr = (m->data >> 2) & 0x1f;
173	}
174
175	if (m->state == MDIO_STATE_READING) {
176	m->data_out = minimac_mdio_read_reg(s, m->phy_addr,
177	m->reg_addr);
178	}
179	}
180
181	if (m->count < 16 && m->state == MDIO_STATE_READING) {
182	int bit = (m->data_out & 0x8000) ? 1 : 0;
183	m->data_out <<= 1;
184
185	if (bit) {
186	s->regs[R_MDIO] \|= MDIO_DI;
187	} else {
188	s->regs[R_MDIO] &= ~MDIO_DI;
189	}
190	}
191
192	if (m->count == 0 && m->state) {
193	if (m->state == MDIO_STATE_WRITING) {
194	uint16_t data = m->data & 0xffff;
195	minimac_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
196	}
197	m->state = MDIO_STATE_IDLE;
198	}
199	m->count--;
200	}
201
202	m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
203	}
204
205	static size_t assemble_frame(uint8_t *buf, size_t size,
206	const uint8_t *payload, size_t payload_size)
207	{
208	uint32_t crc;
209
210	if (size < payload_size + 12) {
211	error_report("milkymist_minimac: received too big ethernet frame");
212	return 0;
213	}
214
215	/* prepend preamble and sfd */
216	memcpy(buf, preamble_sfd, 8);
217
218	/* now copy the payload */
219	memcpy(buf + 8, payload, payload_size);
220
221	/* pad frame if needed */
222	if (payload_size < 60) {
223	memset(buf + payload_size + 8, 0, 60 - payload_size);
224	payload_size = 60;
225	}
226
227	/* append fcs */
228	crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
229	memcpy(buf + payload_size + 8, &crc, 4);
230
231	return payload_size + 12;
232	}
233
234	static void minimac_tx(MilkymistMinimacState *s)
235	{
236	uint8_t buf[MINIMAC_MTU];
237	uint32_t txcount = s->regs[R_TXCOUNT];
238
239	/* do nothing if transmission logic is in reset */
240	if (s->regs[R_SETUP] & SETUP_TX_RST) {
241	return;
242	}
243
244	if (txcount < 64) {
245	error_report("milkymist_minimac: ethernet frame too small (%u < %u)\n",
246	txcount, 64);
247	return;
248	}
249
250	if (txcount > MINIMAC_MTU) {
251	error_report("milkymist_minimac: MTU exceeded (%u > %u)\n",
252	txcount, MINIMAC_MTU);
253	return;
254	}
255
256	/* dma */
257	cpu_physical_memory_read(s->regs[R_TXADDR], buf, txcount);
258
259	if (memcmp(buf, preamble_sfd, 8) != 0) {
260	error_report("milkymist_minimac: frame doesn't contain the preamble "
261	"and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)\n",
262	buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
263	return;
264	}
265
266	trace_milkymist_minimac_tx_frame(txcount - 12);
267
268	/* send packet, skipping preamble and sfd */
269	qemu_send_packet_raw(&s->nic->nc, buf + 8, txcount - 12);
270
271	s->regs[R_TXCOUNT] = 0;
272
273	trace_milkymist_minimac_pulse_irq_tx();
274	qemu_irq_pulse(s->tx_irq);
275	}
276
277	static ssize_t minimac_rx(VLANClientState nc, const uint8_t buf, size_t size)
278	{
279	MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
280
281	uint32_t r_addr;
282	uint32_t r_count;
283	uint32_t r_state;
284
285	uint8_t frame_buf[MINIMAC_MTU];
286	size_t frame_size;
287
288	trace_milkymist_minimac_rx_frame(buf, size);
289
290	/* discard frames if nic is in reset */
291	if (s->regs[R_SETUP] & SETUP_RX_RST) {
292	return size;
293	}
294
295	/* choose appropriate slot */
296	if (s->regs[R_STATE0] == STATE_LOADED) {
297	r_addr = R_ADDR0;
298	r_count = R_COUNT0;
299	r_state = R_STATE0;
300	} else if (s->regs[R_STATE1] == STATE_LOADED) {
301	r_addr = R_ADDR1;
302	r_count = R_COUNT1;
303	r_state = R_STATE1;
304	} else if (s->regs[R_STATE2] == STATE_LOADED) {
305	r_addr = R_ADDR2;
306	r_count = R_COUNT2;
307	r_state = R_STATE2;
308	} else if (s->regs[R_STATE3] == STATE_LOADED) {
309	r_addr = R_ADDR3;
310	r_count = R_COUNT3;
311	r_state = R_STATE3;
312	} else {
313	trace_milkymist_minimac_drop_rx_frame(buf);
314	return size;
315	}
316
317	/* assemble frame */
318	frame_size = assemble_frame(frame_buf, sizeof(frame_buf), buf, size);
319
320	if (frame_size == 0) {
321	return size;
322	}
323
324	trace_milkymist_minimac_rx_transfer(buf, frame_size);
325
326	/* do dma */
327	cpu_physical_memory_write(s->regs[r_addr], frame_buf, frame_size);
328
329	/* update slot */
330	s->regs[r_count] = frame_size;
331	s->regs[r_state] = STATE_PENDING;
332
333	trace_milkymist_minimac_pulse_irq_rx();
334	qemu_irq_pulse(s->rx_irq);
335
336	return size;
337	}
338
339	static uint32_t
340	minimac_read(void *opaque, target_phys_addr_t addr)
341	{
342	MilkymistMinimacState *s = opaque;
343	uint32_t r = 0;
344
345	addr >>= 2;
346	switch (addr) {
347	case R_SETUP:
348	case R_MDIO:
349	case R_STATE0:
350	case R_ADDR0:
351	case R_COUNT0:
352	case R_STATE1:
353	case R_ADDR1:
354	case R_COUNT1:
355	case R_STATE2:
356	case R_ADDR2:
357	case R_COUNT2:
358	case R_STATE3:
359	case R_ADDR3:
360	case R_COUNT3:
361	case R_TXADDR:
362	case R_TXCOUNT:
363	r = s->regs[addr];
364	break;
365
366	default:
367	error_report("milkymist_minimac: read access to unknown register 0x"
368	TARGET_FMT_plx, addr << 2);
369	break;
370	}
371
372	trace_milkymist_minimac_memory_read(addr << 2, r);
373
374	return r;
375	}
376
377	static void
378	minimac_write(void *opaque, target_phys_addr_t addr, uint32_t value)
379	{
380	MilkymistMinimacState *s = opaque;
381
382	trace_milkymist_minimac_memory_read(addr, value);
383
384	addr >>= 2;
385	switch (addr) {
386	case R_MDIO:
387	{
388	/* MDIO_DI is read only */
389	int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
390	s->regs[R_MDIO] = value;
391	if (mdio_di) {
392	s->regs[R_MDIO] \|= mdio_di;
393	} else {
394	s->regs[R_MDIO] &= ~mdio_di;
395	}
396
397	minimac_update_mdio(s);
398	} break;
399	case R_TXCOUNT:
400	s->regs[addr] = value;
401	if (value > 0) {
402	minimac_tx(s);
403	}
404	break;
405	case R_SETUP:
406	case R_STATE0:
407	case R_ADDR0:
408	case R_COUNT0:
409	case R_STATE1:
410	case R_ADDR1:
411	case R_COUNT1:
412	case R_STATE2:
413	case R_ADDR2:
414	case R_COUNT2:
415	case R_STATE3:
416	case R_ADDR3:
417	case R_COUNT3:
418	case R_TXADDR:
419	s->regs[addr] = value;
420	break;
421
422	default:
423	error_report("milkymist_minimac: write access to unknown register 0x"
424	TARGET_FMT_plx, addr << 2);
425	break;
426	}
427	}
428
429	static CPUReadMemoryFunc * const minimac_read_fn[] = {
430	NULL,
431	NULL,
432	&minimac_read,
433	};
434
435	static CPUWriteMemoryFunc * const minimac_write_fn[] = {
436	NULL,
437	NULL,
438	&minimac_write,
439	};
440
441	static int minimac_can_rx(VLANClientState *nc)
442	{
443	MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
444
445	/* discard frames if nic is in reset */
446	if (s->regs[R_SETUP] & SETUP_RX_RST) {
447	return 1;
448	}
449
450	if (s->regs[R_STATE0] == STATE_LOADED) {
451	return 1;
452	}
453	if (s->regs[R_STATE1] == STATE_LOADED) {
454	return 1;
455	}
456	if (s->regs[R_STATE2] == STATE_LOADED) {
457	return 1;
458	}
459	if (s->regs[R_STATE3] == STATE_LOADED) {
460	return 1;
461	}
462
463	return 0;
464	}
465
466	static void minimac_cleanup(VLANClientState *nc)
467	{
468	MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
469
470	s->nic = NULL;
471	}
472
473	static void milkymist_minimac_reset(DeviceState *d)
474	{
475	MilkymistMinimacState *s =
476	container_of(d, MilkymistMinimacState, busdev.qdev);
477	int i;
478
479	for (i = 0; i < R_MAX; i++) {
480	s->regs[i] = 0;
481	}
482	for (i = 0; i < R_PHY_MAX; i++) {
483	s->phy_regs[i] = 0;
484	}
485
486	/* defaults */
487	s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
488	s->phy_regs[R_PHY_ID2] = 0x161a;
489	}
490
491	static NetClientInfo net_milkymist_minimac_info = {
492	.type = NET_CLIENT_TYPE_NIC,
493	.size = sizeof(NICState),
494	.can_receive = minimac_can_rx,
495	.receive = minimac_rx,
496	.cleanup = minimac_cleanup,
497	};
498
499	static int milkymist_minimac_init(SysBusDevice *dev)
500	{
501	MilkymistMinimacState s = FROM_SYSBUS(typeof(s), dev);
502	int regs;
503
504	sysbus_init_irq(dev, &s->rx_irq);
505	sysbus_init_irq(dev, &s->tx_irq);
506
507	regs = cpu_register_io_memory(minimac_read_fn, minimac_write_fn, s,
508	DEVICE_NATIVE_ENDIAN);
509	sysbus_init_mmio(dev, R_MAX * 4, regs);
510
511	qemu_macaddr_default_if_unset(&s->conf.macaddr);
512	s->nic = qemu_new_nic(&net_milkymist_minimac_info, &s->conf,
513	dev->qdev.info->name, dev->qdev.id, s);
514	qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
515
516	return 0;
517	}
518
519	static const VMStateDescription vmstate_milkymist_minimac_mdio = {
520	.name = "milkymist_minimac_mdio",
521	.version_id = 1,
522	.minimum_version_id = 1,
523	.minimum_version_id_old = 1,
524	.fields = (VMStateField[]) {
525	VMSTATE_INT32(last_clk, MilkymistMinimacMdioState),
526	VMSTATE_INT32(count, MilkymistMinimacMdioState),
527	VMSTATE_UINT32(data, MilkymistMinimacMdioState),
528	VMSTATE_UINT16(data_out, MilkymistMinimacMdioState),
529	VMSTATE_INT32(state, MilkymistMinimacMdioState),
530	VMSTATE_UINT8(phy_addr, MilkymistMinimacMdioState),
531	VMSTATE_UINT8(reg_addr, MilkymistMinimacMdioState),
532	VMSTATE_END_OF_LIST()
533	}
534	};
535
536	static const VMStateDescription vmstate_milkymist_minimac = {
537	.name = "milkymist-minimac",
538	.version_id = 1,
539	.minimum_version_id = 1,
540	.minimum_version_id_old = 1,
541	.fields = (VMStateField[]) {
542	VMSTATE_UINT32_ARRAY(regs, MilkymistMinimacState, R_MAX),
543	VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimacState, R_PHY_MAX),
544	VMSTATE_STRUCT(mdio, MilkymistMinimacState, 0,
545	vmstate_milkymist_minimac_mdio, MilkymistMinimacMdioState),
546	VMSTATE_END_OF_LIST()
547	}
548	};
549
550	static SysBusDeviceInfo milkymist_minimac_info = {
551	.init = milkymist_minimac_init,
552	.qdev.name = "milkymist-minimac",
553	.qdev.size = sizeof(MilkymistMinimacState),
554	.qdev.vmsd = &vmstate_milkymist_minimac,
555	.qdev.reset = milkymist_minimac_reset,
556	.qdev.props = (Property[]) {
557	DEFINE_NIC_PROPERTIES(MilkymistMinimacState, conf),
558	DEFINE_PROP_STRING("phy_model", MilkymistMinimacState, phy_model),
559	DEFINE_PROP_END_OF_LIST(),
560	}
561	};
562
563	static void milkymist_minimac_register(void)
564	{
565	sysbus_register_withprop(&milkymist_minimac_info);
566	}
567
568	device_init(milkymist_minimac_register)