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b00052e4 AZ |
1 | /* |
2 | * PXA270-based Clamshell PDA platforms. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <[email protected]> | |
6 | * | |
7 | * This code is licensed under the GNU GPL v2. | |
8 | */ | |
9 | ||
87ecb68b PB |
10 | #include "hw.h" |
11 | #include "pxa.h" | |
12 | #include "arm-misc.h" | |
13 | #include "sysemu.h" | |
14 | #include "pcmcia.h" | |
15 | #include "i2c.h" | |
a984a69e | 16 | #include "ssi.h" |
87ecb68b PB |
17 | #include "flash.h" |
18 | #include "qemu-timer.h" | |
19 | #include "devices.h" | |
e33d8cdb | 20 | #include "sharpsl.h" |
87ecb68b PB |
21 | #include "console.h" |
22 | #include "block.h" | |
23 | #include "audio/audio.h" | |
24 | #include "boards.h" | |
2446333c | 25 | #include "blockdev.h" |
b00052e4 | 26 | |
b00052e4 AZ |
27 | #undef REG_FMT |
28 | #define REG_FMT "0x%02lx" | |
29 | ||
30 | /* Spitz Flash */ | |
31 | #define FLASH_BASE 0x0c000000 | |
32 | #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ | |
33 | #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ | |
34 | #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ | |
35 | #define FLASH_ECCCNTR 0x0c /* ECC byte counter */ | |
36 | #define FLASH_ECCCLRR 0x10 /* Clear ECC */ | |
37 | #define FLASH_FLASHIO 0x14 /* Flash I/O */ | |
38 | #define FLASH_FLASHCTL 0x18 /* Flash Control */ | |
39 | ||
40 | #define FLASHCTL_CE0 (1 << 0) | |
41 | #define FLASHCTL_CLE (1 << 1) | |
42 | #define FLASHCTL_ALE (1 << 2) | |
43 | #define FLASHCTL_WP (1 << 3) | |
44 | #define FLASHCTL_CE1 (1 << 4) | |
45 | #define FLASHCTL_RYBY (1 << 5) | |
46 | #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) | |
47 | ||
bc24a225 PB |
48 | typedef struct { |
49 | NANDFlashState *nand; | |
b00052e4 | 50 | uint8_t ctl; |
bc24a225 PB |
51 | ECCState ecc; |
52 | } SLNANDState; | |
b00052e4 | 53 | |
c227f099 | 54 | static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
b00052e4 | 55 | { |
bc24a225 | 56 | SLNANDState *s = (SLNANDState *) opaque; |
b00052e4 | 57 | int ryby; |
b00052e4 AZ |
58 | |
59 | switch (addr) { | |
60 | #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) | |
61 | case FLASH_ECCLPLB: | |
62 | return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | | |
63 | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); | |
64 | ||
65 | #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) | |
66 | case FLASH_ECCLPUB: | |
67 | return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | | |
68 | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); | |
69 | ||
70 | case FLASH_ECCCP: | |
71 | return s->ecc.cp; | |
72 | ||
73 | case FLASH_ECCCNTR: | |
74 | return s->ecc.count & 0xff; | |
75 | ||
76 | case FLASH_FLASHCTL: | |
77 | nand_getpins(s->nand, &ryby); | |
78 | if (ryby) | |
79 | return s->ctl | FLASHCTL_RYBY; | |
80 | else | |
81 | return s->ctl; | |
82 | ||
83 | case FLASH_FLASHIO: | |
84 | return ecc_digest(&s->ecc, nand_getio(s->nand)); | |
85 | ||
86 | default: | |
a8b7063b | 87 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
b00052e4 AZ |
88 | } |
89 | return 0; | |
90 | } | |
91 | ||
c227f099 | 92 | static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) |
a5236105 | 93 | { |
bc24a225 | 94 | SLNANDState *s = (SLNANDState *) opaque; |
a5236105 AZ |
95 | |
96 | if (addr == FLASH_FLASHIO) | |
97 | return ecc_digest(&s->ecc, nand_getio(s->nand)) | | |
98 | (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16); | |
99 | ||
100 | return sl_readb(opaque, addr); | |
101 | } | |
102 | ||
c227f099 | 103 | static void sl_writeb(void *opaque, target_phys_addr_t addr, |
b00052e4 AZ |
104 | uint32_t value) |
105 | { | |
bc24a225 | 106 | SLNANDState *s = (SLNANDState *) opaque; |
b00052e4 AZ |
107 | |
108 | switch (addr) { | |
109 | case FLASH_ECCCLRR: | |
110 | /* Value is ignored. */ | |
111 | ecc_reset(&s->ecc); | |
112 | break; | |
113 | ||
114 | case FLASH_FLASHCTL: | |
115 | s->ctl = value & 0xff & ~FLASHCTL_RYBY; | |
116 | nand_setpins(s->nand, | |
117 | s->ctl & FLASHCTL_CLE, | |
118 | s->ctl & FLASHCTL_ALE, | |
119 | s->ctl & FLASHCTL_NCE, | |
120 | s->ctl & FLASHCTL_WP, | |
121 | 0); | |
122 | break; | |
123 | ||
124 | case FLASH_FLASHIO: | |
125 | nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff)); | |
126 | break; | |
127 | ||
128 | default: | |
a8b7063b | 129 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
b00052e4 AZ |
130 | } |
131 | } | |
132 | ||
aa941b94 AZ |
133 | static void sl_save(QEMUFile *f, void *opaque) |
134 | { | |
bc24a225 | 135 | SLNANDState *s = (SLNANDState *) opaque; |
aa941b94 AZ |
136 | |
137 | qemu_put_8s(f, &s->ctl); | |
138 | ecc_put(f, &s->ecc); | |
139 | } | |
140 | ||
141 | static int sl_load(QEMUFile *f, void *opaque, int version_id) | |
142 | { | |
bc24a225 | 143 | SLNANDState *s = (SLNANDState *) opaque; |
aa941b94 AZ |
144 | |
145 | qemu_get_8s(f, &s->ctl); | |
146 | ecc_get(f, &s->ecc); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
b00052e4 AZ |
151 | enum { |
152 | FLASH_128M, | |
153 | FLASH_1024M, | |
154 | }; | |
155 | ||
bc24a225 | 156 | static void sl_flash_register(PXA2xxState *cpu, int size) |
b00052e4 AZ |
157 | { |
158 | int iomemtype; | |
bc24a225 | 159 | SLNANDState *s; |
d60efc6b | 160 | CPUReadMemoryFunc * const sl_readfn[] = { |
b00052e4 AZ |
161 | sl_readb, |
162 | sl_readb, | |
a5236105 | 163 | sl_readl, |
b00052e4 | 164 | }; |
d60efc6b | 165 | CPUWriteMemoryFunc * const sl_writefn[] = { |
b00052e4 AZ |
166 | sl_writeb, |
167 | sl_writeb, | |
168 | sl_writeb, | |
169 | }; | |
170 | ||
bc24a225 | 171 | s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState)); |
b00052e4 AZ |
172 | s->ctl = 0; |
173 | if (size == FLASH_128M) | |
174 | s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73); | |
175 | else if (size == FLASH_1024M) | |
176 | s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1); | |
177 | ||
1eed09cb | 178 | iomemtype = cpu_register_io_memory(sl_readfn, |
2507c12a | 179 | sl_writefn, s, DEVICE_NATIVE_ENDIAN); |
8da3ff18 | 180 | cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype); |
aa941b94 | 181 | |
0be71e32 | 182 | register_savevm(NULL, "sl_flash", 0, 0, sl_save, sl_load, s); |
b00052e4 AZ |
183 | } |
184 | ||
185 | /* Spitz Keyboard */ | |
186 | ||
187 | #define SPITZ_KEY_STROBE_NUM 11 | |
188 | #define SPITZ_KEY_SENSE_NUM 7 | |
189 | ||
190 | static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { | |
191 | 12, 17, 91, 34, 36, 38, 39 | |
192 | }; | |
193 | ||
194 | static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { | |
195 | 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 | |
196 | }; | |
197 | ||
198 | /* Eighth additional row maps the special keys */ | |
199 | static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { | |
200 | { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, | |
201 | { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, | |
202 | { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, | |
203 | { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, | |
204 | { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, | |
2b76bdc9 AZ |
205 | { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 }, |
206 | { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, | |
b00052e4 AZ |
207 | { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
208 | }; | |
209 | ||
210 | #define SPITZ_GPIO_AK_INT 13 /* Remote control */ | |
211 | #define SPITZ_GPIO_SYNC 16 /* Sync button */ | |
212 | #define SPITZ_GPIO_ON_KEY 95 /* Power button */ | |
213 | #define SPITZ_GPIO_SWA 97 /* Lid */ | |
214 | #define SPITZ_GPIO_SWB 96 /* Tablet mode */ | |
215 | ||
216 | /* The special buttons are mapped to unused keys */ | |
217 | static const int spitz_gpiomap[5] = { | |
218 | SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, | |
219 | SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, | |
220 | }; | |
221 | static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; | |
222 | ||
bc24a225 | 223 | typedef struct { |
38641a52 AZ |
224 | qemu_irq sense[SPITZ_KEY_SENSE_NUM]; |
225 | qemu_irq *strobe; | |
226 | qemu_irq gpiomap[5]; | |
b00052e4 AZ |
227 | int keymap[0x80]; |
228 | uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; | |
229 | uint16_t strobe_state; | |
230 | uint16_t sense_state; | |
231 | ||
232 | uint16_t pre_map[0x100]; | |
233 | uint16_t modifiers; | |
234 | uint16_t imodifiers; | |
235 | uint8_t fifo[16]; | |
236 | int fifopos, fifolen; | |
237 | QEMUTimer *kbdtimer; | |
bc24a225 | 238 | } SpitzKeyboardState; |
b00052e4 | 239 | |
bc24a225 | 240 | static void spitz_keyboard_sense_update(SpitzKeyboardState *s) |
b00052e4 AZ |
241 | { |
242 | int i; | |
243 | uint16_t strobe, sense = 0; | |
244 | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { | |
245 | strobe = s->keyrow[i] & s->strobe_state; | |
246 | if (strobe) { | |
247 | sense |= 1 << i; | |
248 | if (!(s->sense_state & (1 << i))) | |
38641a52 | 249 | qemu_irq_raise(s->sense[i]); |
b00052e4 | 250 | } else if (s->sense_state & (1 << i)) |
38641a52 | 251 | qemu_irq_lower(s->sense[i]); |
b00052e4 AZ |
252 | } |
253 | ||
254 | s->sense_state = sense; | |
255 | } | |
256 | ||
38641a52 | 257 | static void spitz_keyboard_strobe(void *opaque, int line, int level) |
b00052e4 | 258 | { |
bc24a225 | 259 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
38641a52 AZ |
260 | |
261 | if (level) | |
262 | s->strobe_state |= 1 << line; | |
263 | else | |
264 | s->strobe_state &= ~(1 << line); | |
265 | spitz_keyboard_sense_update(s); | |
b00052e4 AZ |
266 | } |
267 | ||
bc24a225 | 268 | static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) |
b00052e4 AZ |
269 | { |
270 | int spitz_keycode = s->keymap[keycode & 0x7f]; | |
271 | if (spitz_keycode == -1) | |
272 | return; | |
273 | ||
274 | /* Handle the additional keys */ | |
275 | if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { | |
38641a52 | 276 | qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^ |
b00052e4 AZ |
277 | spitz_gpio_invert[spitz_keycode & 0xf]); |
278 | return; | |
279 | } | |
280 | ||
281 | if (keycode & 0x80) | |
282 | s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); | |
283 | else | |
284 | s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); | |
285 | ||
286 | spitz_keyboard_sense_update(s); | |
287 | } | |
288 | ||
289 | #define SHIFT (1 << 7) | |
290 | #define CTRL (1 << 8) | |
291 | #define FN (1 << 9) | |
292 | ||
293 | #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c | |
294 | ||
bc24a225 | 295 | static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode) |
b00052e4 AZ |
296 | { |
297 | uint16_t code; | |
298 | int mapcode; | |
299 | switch (keycode) { | |
300 | case 0x2a: /* Left Shift */ | |
301 | s->modifiers |= 1; | |
302 | break; | |
303 | case 0xaa: | |
304 | s->modifiers &= ~1; | |
305 | break; | |
306 | case 0x36: /* Right Shift */ | |
307 | s->modifiers |= 2; | |
308 | break; | |
309 | case 0xb6: | |
310 | s->modifiers &= ~2; | |
311 | break; | |
312 | case 0x1d: /* Control */ | |
313 | s->modifiers |= 4; | |
314 | break; | |
315 | case 0x9d: | |
316 | s->modifiers &= ~4; | |
317 | break; | |
318 | case 0x38: /* Alt */ | |
319 | s->modifiers |= 8; | |
320 | break; | |
321 | case 0xb8: | |
322 | s->modifiers &= ~8; | |
323 | break; | |
324 | } | |
325 | ||
326 | code = s->pre_map[mapcode = ((s->modifiers & 3) ? | |
327 | (keycode | SHIFT) : | |
328 | (keycode & ~SHIFT))]; | |
329 | ||
330 | if (code != mapcode) { | |
331 | #if 0 | |
332 | if ((code & SHIFT) && !(s->modifiers & 1)) | |
333 | QUEUE_KEY(0x2a | (keycode & 0x80)); | |
334 | if ((code & CTRL ) && !(s->modifiers & 4)) | |
335 | QUEUE_KEY(0x1d | (keycode & 0x80)); | |
336 | if ((code & FN ) && !(s->modifiers & 8)) | |
337 | QUEUE_KEY(0x38 | (keycode & 0x80)); | |
338 | if ((code & FN ) && (s->modifiers & 1)) | |
339 | QUEUE_KEY(0x2a | (~keycode & 0x80)); | |
340 | if ((code & FN ) && (s->modifiers & 2)) | |
341 | QUEUE_KEY(0x36 | (~keycode & 0x80)); | |
342 | #else | |
343 | if (keycode & 0x80) { | |
344 | if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) | |
345 | QUEUE_KEY(0x2a | 0x80); | |
346 | if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) | |
347 | QUEUE_KEY(0x1d | 0x80); | |
348 | if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) | |
349 | QUEUE_KEY(0x38 | 0x80); | |
350 | if ((s->imodifiers & 0x10) && (s->modifiers & 1)) | |
351 | QUEUE_KEY(0x2a); | |
352 | if ((s->imodifiers & 0x20) && (s->modifiers & 2)) | |
353 | QUEUE_KEY(0x36); | |
354 | s->imodifiers = 0; | |
355 | } else { | |
356 | if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { | |
357 | QUEUE_KEY(0x2a); | |
358 | s->imodifiers |= 1; | |
359 | } | |
360 | if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { | |
361 | QUEUE_KEY(0x1d); | |
362 | s->imodifiers |= 4; | |
363 | } | |
364 | if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { | |
365 | QUEUE_KEY(0x38); | |
366 | s->imodifiers |= 8; | |
367 | } | |
368 | if ((code & FN ) && (s->modifiers & 1) && | |
369 | !(s->imodifiers & 0x10)) { | |
370 | QUEUE_KEY(0x2a | 0x80); | |
371 | s->imodifiers |= 0x10; | |
372 | } | |
373 | if ((code & FN ) && (s->modifiers & 2) && | |
374 | !(s->imodifiers & 0x20)) { | |
375 | QUEUE_KEY(0x36 | 0x80); | |
376 | s->imodifiers |= 0x20; | |
377 | } | |
378 | } | |
379 | #endif | |
380 | } | |
381 | ||
382 | QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); | |
383 | } | |
384 | ||
385 | static void spitz_keyboard_tick(void *opaque) | |
386 | { | |
bc24a225 | 387 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
b00052e4 AZ |
388 | |
389 | if (s->fifolen) { | |
390 | spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); | |
391 | s->fifolen --; | |
392 | if (s->fifopos >= 16) | |
393 | s->fifopos = 0; | |
394 | } | |
395 | ||
6ee093c9 JQ |
396 | qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + |
397 | get_ticks_per_sec() / 32); | |
b00052e4 AZ |
398 | } |
399 | ||
bc24a225 | 400 | static void spitz_keyboard_pre_map(SpitzKeyboardState *s) |
b00052e4 AZ |
401 | { |
402 | int i; | |
403 | for (i = 0; i < 0x100; i ++) | |
404 | s->pre_map[i] = i; | |
405 | s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ | |
406 | s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ | |
407 | s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ | |
408 | s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ | |
409 | s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ | |
410 | s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ | |
411 | s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ | |
412 | s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ | |
413 | s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ | |
414 | s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ | |
415 | s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ | |
416 | s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ | |
417 | s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ | |
418 | s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ | |
419 | s->pre_map[0x0d ] = 0x12 | FN; /* equal */ | |
420 | s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ | |
421 | s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ | |
422 | s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ | |
2b76bdc9 AZ |
423 | s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */ |
424 | s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */ | |
b00052e4 AZ |
425 | s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
426 | s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ | |
427 | s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ | |
428 | s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ | |
429 | s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ | |
430 | s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ | |
2b76bdc9 | 431 | s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */ |
b00052e4 | 432 | s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
2b76bdc9 | 433 | s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */ |
b00052e4 AZ |
434 | s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
435 | s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ | |
436 | s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ | |
437 | ||
438 | s->modifiers = 0; | |
439 | s->imodifiers = 0; | |
440 | s->fifopos = 0; | |
441 | s->fifolen = 0; | |
442 | s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); | |
443 | spitz_keyboard_tick(s); | |
444 | } | |
445 | ||
446 | #undef SHIFT | |
447 | #undef CTRL | |
448 | #undef FN | |
449 | ||
aa941b94 AZ |
450 | static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
451 | { | |
bc24a225 | 452 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
aa941b94 AZ |
453 | int i; |
454 | ||
455 | qemu_put_be16s(f, &s->sense_state); | |
456 | qemu_put_be16s(f, &s->strobe_state); | |
457 | for (i = 0; i < 5; i ++) | |
458 | qemu_put_byte(f, spitz_gpio_invert[i]); | |
459 | } | |
460 | ||
461 | static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) | |
462 | { | |
bc24a225 | 463 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
aa941b94 AZ |
464 | int i; |
465 | ||
466 | qemu_get_be16s(f, &s->sense_state); | |
467 | qemu_get_be16s(f, &s->strobe_state); | |
468 | for (i = 0; i < 5; i ++) | |
469 | spitz_gpio_invert[i] = qemu_get_byte(f); | |
470 | ||
471 | /* Release all pressed keys */ | |
472 | memset(s->keyrow, 0, sizeof(s->keyrow)); | |
473 | spitz_keyboard_sense_update(s); | |
474 | s->modifiers = 0; | |
475 | s->imodifiers = 0; | |
476 | s->fifopos = 0; | |
477 | s->fifolen = 0; | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
bc24a225 | 482 | static void spitz_keyboard_register(PXA2xxState *cpu) |
b00052e4 AZ |
483 | { |
484 | int i, j; | |
bc24a225 | 485 | SpitzKeyboardState *s; |
b00052e4 | 486 | |
bc24a225 PB |
487 | s = (SpitzKeyboardState *) |
488 | qemu_mallocz(sizeof(SpitzKeyboardState)); | |
489 | memset(s, 0, sizeof(SpitzKeyboardState)); | |
b00052e4 AZ |
490 | |
491 | for (i = 0; i < 0x80; i ++) | |
492 | s->keymap[i] = -1; | |
493 | for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) | |
494 | for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) | |
495 | if (spitz_keymap[i][j] != -1) | |
496 | s->keymap[spitz_keymap[i][j]] = (i << 4) | j; | |
497 | ||
38641a52 AZ |
498 | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) |
499 | s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]]; | |
500 | ||
501 | for (i = 0; i < 5; i ++) | |
502 | s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]]; | |
503 | ||
504 | s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s, | |
505 | SPITZ_KEY_STROBE_NUM); | |
b00052e4 | 506 | for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
38641a52 | 507 | pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]); |
b00052e4 AZ |
508 | |
509 | spitz_keyboard_pre_map(s); | |
510 | qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); | |
aa941b94 | 511 | |
0be71e32 | 512 | register_savevm(NULL, "spitz_keyboard", 0, 0, |
aa941b94 | 513 | spitz_keyboard_save, spitz_keyboard_load, s); |
b00052e4 AZ |
514 | } |
515 | ||
b00052e4 AZ |
516 | /* LCD backlight controller */ |
517 | ||
518 | #define LCDTG_RESCTL 0x00 | |
519 | #define LCDTG_PHACTRL 0x01 | |
520 | #define LCDTG_DUTYCTRL 0x02 | |
521 | #define LCDTG_POWERREG0 0x03 | |
522 | #define LCDTG_POWERREG1 0x04 | |
523 | #define LCDTG_GPOR3 0x05 | |
524 | #define LCDTG_PICTRL 0x06 | |
525 | #define LCDTG_POLCTRL 0x07 | |
526 | ||
a984a69e PB |
527 | typedef struct { |
528 | SSISlave ssidev; | |
529 | int bl_intensity; | |
530 | int bl_power; | |
531 | } SpitzLCDTG; | |
b00052e4 | 532 | |
a984a69e | 533 | static void spitz_bl_update(SpitzLCDTG *s) |
b00052e4 | 534 | { |
a984a69e PB |
535 | if (s->bl_power && s->bl_intensity) |
536 | zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity); | |
b00052e4 | 537 | else |
89cdb6af | 538 | zaurus_printf("LCD Backlight now off\n"); |
b00052e4 AZ |
539 | } |
540 | ||
a984a69e PB |
541 | /* FIXME: Implement GPIO properly and remove this hack. */ |
542 | static SpitzLCDTG *spitz_lcdtg; | |
543 | ||
38641a52 | 544 | static inline void spitz_bl_bit5(void *opaque, int line, int level) |
b00052e4 | 545 | { |
a984a69e PB |
546 | SpitzLCDTG *s = spitz_lcdtg; |
547 | int prev = s->bl_intensity; | |
b00052e4 AZ |
548 | |
549 | if (level) | |
a984a69e | 550 | s->bl_intensity &= ~0x20; |
b00052e4 | 551 | else |
a984a69e | 552 | s->bl_intensity |= 0x20; |
b00052e4 | 553 | |
a984a69e PB |
554 | if (s->bl_power && prev != s->bl_intensity) |
555 | spitz_bl_update(s); | |
b00052e4 AZ |
556 | } |
557 | ||
38641a52 | 558 | static inline void spitz_bl_power(void *opaque, int line, int level) |
b00052e4 | 559 | { |
a984a69e PB |
560 | SpitzLCDTG *s = spitz_lcdtg; |
561 | s->bl_power = !!level; | |
562 | spitz_bl_update(s); | |
b00052e4 AZ |
563 | } |
564 | ||
a984a69e | 565 | static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) |
b00052e4 | 566 | { |
a984a69e PB |
567 | SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); |
568 | int addr; | |
569 | addr = value >> 5; | |
570 | value &= 0x1f; | |
b00052e4 AZ |
571 | |
572 | switch (addr) { | |
573 | case LCDTG_RESCTL: | |
574 | if (value) | |
89cdb6af | 575 | zaurus_printf("LCD in QVGA mode\n"); |
b00052e4 | 576 | else |
89cdb6af | 577 | zaurus_printf("LCD in VGA mode\n"); |
b00052e4 AZ |
578 | break; |
579 | ||
580 | case LCDTG_DUTYCTRL: | |
a984a69e PB |
581 | s->bl_intensity &= ~0x1f; |
582 | s->bl_intensity |= value; | |
583 | if (s->bl_power) | |
584 | spitz_bl_update(s); | |
b00052e4 AZ |
585 | break; |
586 | ||
587 | case LCDTG_POWERREG0: | |
588 | /* Set common voltage to M62332FP */ | |
589 | break; | |
590 | } | |
a984a69e PB |
591 | return 0; |
592 | } | |
593 | ||
594 | static void spitz_lcdtg_save(QEMUFile *f, void *opaque) | |
595 | { | |
596 | SpitzLCDTG *s = (SpitzLCDTG *)opaque; | |
597 | qemu_put_be32(f, s->bl_intensity); | |
598 | qemu_put_be32(f, s->bl_power); | |
599 | } | |
600 | ||
601 | static int spitz_lcdtg_load(QEMUFile *f, void *opaque, int version_id) | |
602 | { | |
603 | SpitzLCDTG *s = (SpitzLCDTG *)opaque; | |
604 | s->bl_intensity = qemu_get_be32(f); | |
605 | s->bl_power = qemu_get_be32(f); | |
606 | return 0; | |
607 | } | |
608 | ||
81a322d4 | 609 | static int spitz_lcdtg_init(SSISlave *dev) |
a984a69e PB |
610 | { |
611 | SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); | |
612 | ||
613 | spitz_lcdtg = s; | |
614 | s->bl_power = 0; | |
615 | s->bl_intensity = 0x20; | |
616 | ||
0be71e32 | 617 | register_savevm(&dev->qdev, "spitz-lcdtg", -1, 1, |
a984a69e | 618 | spitz_lcdtg_save, spitz_lcdtg_load, s); |
81a322d4 | 619 | return 0; |
b00052e4 AZ |
620 | } |
621 | ||
622 | /* SSP devices */ | |
623 | ||
624 | #define CORGI_SSP_PORT 2 | |
625 | ||
626 | #define SPITZ_GPIO_LCDCON_CS 53 | |
627 | #define SPITZ_GPIO_ADS7846_CS 14 | |
628 | #define SPITZ_GPIO_MAX1111_CS 20 | |
629 | #define SPITZ_GPIO_TP_INT 11 | |
630 | ||
a984a69e | 631 | static DeviceState *max1111; |
b00052e4 AZ |
632 | |
633 | /* "Demux" the signal based on current chipselect */ | |
a984a69e PB |
634 | typedef struct { |
635 | SSISlave ssidev; | |
636 | SSIBus *bus[3]; | |
637 | int enable[3]; | |
638 | } CorgiSSPState; | |
b00052e4 | 639 | |
a984a69e | 640 | static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value) |
b00052e4 | 641 | { |
a984a69e PB |
642 | CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); |
643 | int i; | |
644 | ||
645 | for (i = 0; i < 3; i++) { | |
646 | if (s->enable[i]) { | |
647 | return ssi_transfer(s->bus[i], value); | |
648 | } | |
649 | } | |
650 | return 0; | |
b00052e4 AZ |
651 | } |
652 | ||
38641a52 | 653 | static void corgi_ssp_gpio_cs(void *opaque, int line, int level) |
b00052e4 | 654 | { |
a984a69e PB |
655 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
656 | assert(line >= 0 && line < 3); | |
657 | s->enable[line] = !level; | |
b00052e4 AZ |
658 | } |
659 | ||
660 | #define MAX1111_BATT_VOLT 1 | |
661 | #define MAX1111_BATT_TEMP 2 | |
662 | #define MAX1111_ACIN_VOLT 3 | |
663 | ||
664 | #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ | |
665 | #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ | |
666 | #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ | |
667 | ||
38641a52 | 668 | static void spitz_adc_temp_on(void *opaque, int line, int level) |
b00052e4 AZ |
669 | { |
670 | if (!max1111) | |
671 | return; | |
672 | ||
673 | if (level) | |
674 | max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); | |
675 | else | |
676 | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | |
677 | } | |
678 | ||
aa941b94 AZ |
679 | static void spitz_ssp_save(QEMUFile *f, void *opaque) |
680 | { | |
a984a69e PB |
681 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
682 | int i; | |
683 | ||
684 | for (i = 0; i < 3; i++) { | |
685 | qemu_put_be32(f, s->enable[i]); | |
686 | } | |
aa941b94 AZ |
687 | } |
688 | ||
689 | static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) | |
690 | { | |
a984a69e PB |
691 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
692 | int i; | |
aa941b94 | 693 | |
a984a69e PB |
694 | if (version_id != 1) { |
695 | return -EINVAL; | |
696 | } | |
697 | for (i = 0; i < 3; i++) { | |
698 | s->enable[i] = qemu_get_be32(f); | |
699 | } | |
aa941b94 AZ |
700 | return 0; |
701 | } | |
702 | ||
81a322d4 | 703 | static int corgi_ssp_init(SSISlave *dev) |
a984a69e PB |
704 | { |
705 | CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); | |
706 | ||
707 | qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3); | |
02e2da45 PB |
708 | s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0"); |
709 | s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1"); | |
710 | s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2"); | |
a984a69e | 711 | |
0be71e32 AW |
712 | register_savevm(&dev->qdev, "spitz_ssp", -1, 1, |
713 | spitz_ssp_save, spitz_ssp_load, s); | |
81a322d4 | 714 | return 0; |
a984a69e PB |
715 | } |
716 | ||
bc24a225 | 717 | static void spitz_ssp_attach(PXA2xxState *cpu) |
b00052e4 | 718 | { |
a984a69e PB |
719 | DeviceState *mux; |
720 | DeviceState *dev; | |
721 | void *bus; | |
722 | ||
723 | mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); | |
38641a52 | 724 | |
a984a69e | 725 | bus = qdev_get_child_bus(mux, "ssi0"); |
22ed1d34 | 726 | ssi_create_slave(bus, "spitz-lcdtg"); |
b00052e4 | 727 | |
a984a69e PB |
728 | bus = qdev_get_child_bus(mux, "ssi1"); |
729 | dev = ssi_create_slave(bus, "ads7846"); | |
730 | qdev_connect_gpio_out(dev, 0, | |
731 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]); | |
b00052e4 | 732 | |
a984a69e PB |
733 | bus = qdev_get_child_bus(mux, "ssi2"); |
734 | max1111 = ssi_create_slave(bus, "max1111"); | |
b00052e4 AZ |
735 | max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
736 | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | |
737 | max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); | |
738 | ||
a984a69e PB |
739 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, |
740 | qdev_get_gpio_in(mux, 0)); | |
741 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, | |
742 | qdev_get_gpio_in(mux, 1)); | |
743 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, | |
744 | qdev_get_gpio_in(mux, 2)); | |
b00052e4 AZ |
745 | } |
746 | ||
747 | /* CF Microdrive */ | |
748 | ||
bc24a225 | 749 | static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) |
b00052e4 | 750 | { |
bc24a225 | 751 | PCMCIACardState *md; |
e4bcb14c | 752 | BlockDriverState *bs; |
751c6a17 | 753 | DriveInfo *dinfo; |
b00052e4 | 754 | |
751c6a17 GH |
755 | dinfo = drive_get(IF_IDE, 0, 0); |
756 | if (!dinfo) | |
e4bcb14c | 757 | return; |
751c6a17 | 758 | bs = dinfo->bdrv; |
e4bcb14c | 759 | if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) { |
f455e98c | 760 | md = dscm1xxxx_init(dinfo); |
15b18ec2 | 761 | pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md); |
b00052e4 AZ |
762 | } |
763 | } | |
764 | ||
adb86c37 AZ |
765 | /* Wm8750 and Max7310 on I2C */ |
766 | ||
767 | #define AKITA_MAX_ADDR 0x18 | |
611d7189 AZ |
768 | #define SPITZ_WM_ADDRL 0x1b |
769 | #define SPITZ_WM_ADDRH 0x1a | |
adb86c37 AZ |
770 | |
771 | #define SPITZ_GPIO_WM 5 | |
772 | ||
38641a52 | 773 | static void spitz_wm8750_addr(void *opaque, int line, int level) |
adb86c37 AZ |
774 | { |
775 | i2c_slave *wm = (i2c_slave *) opaque; | |
776 | if (level) | |
777 | i2c_set_slave_address(wm, SPITZ_WM_ADDRH); | |
778 | else | |
779 | i2c_set_slave_address(wm, SPITZ_WM_ADDRL); | |
780 | } | |
adb86c37 | 781 | |
bc24a225 | 782 | static void spitz_i2c_setup(PXA2xxState *cpu) |
adb86c37 AZ |
783 | { |
784 | /* Attach the CPU on one end of our I2C bus. */ | |
785 | i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]); | |
786 | ||
cdbe40ca | 787 | DeviceState *wm; |
adb86c37 | 788 | |
adb86c37 | 789 | /* Attach a WM8750 to the bus */ |
cdbe40ca | 790 | wm = i2c_create_slave(bus, "wm8750", 0); |
adb86c37 | 791 | |
38641a52 AZ |
792 | spitz_wm8750_addr(wm, 0, 0); |
793 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM, | |
794 | qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]); | |
adb86c37 AZ |
795 | /* .. and to the sound interface. */ |
796 | cpu->i2s->opaque = wm; | |
797 | cpu->i2s->codec_out = wm8750_dac_dat; | |
798 | cpu->i2s->codec_in = wm8750_adc_dat; | |
799 | wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); | |
adb86c37 AZ |
800 | } |
801 | ||
bc24a225 | 802 | static void spitz_akita_i2c_setup(PXA2xxState *cpu) |
adb86c37 AZ |
803 | { |
804 | /* Attach a Max7310 to Akita I2C bus. */ | |
6c0bd6bd PB |
805 | i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310", |
806 | AKITA_MAX_ADDR); | |
adb86c37 AZ |
807 | } |
808 | ||
b00052e4 AZ |
809 | /* Other peripherals */ |
810 | ||
38641a52 | 811 | static void spitz_out_switch(void *opaque, int line, int level) |
b00052e4 | 812 | { |
38641a52 AZ |
813 | switch (line) { |
814 | case 0: | |
89cdb6af | 815 | zaurus_printf("Charging %s.\n", level ? "off" : "on"); |
38641a52 AZ |
816 | break; |
817 | case 1: | |
89cdb6af | 818 | zaurus_printf("Discharging %s.\n", level ? "on" : "off"); |
38641a52 AZ |
819 | break; |
820 | case 2: | |
89cdb6af | 821 | zaurus_printf("Green LED %s.\n", level ? "on" : "off"); |
38641a52 AZ |
822 | break; |
823 | case 3: | |
89cdb6af | 824 | zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); |
38641a52 AZ |
825 | break; |
826 | case 4: | |
827 | spitz_bl_bit5(opaque, line, level); | |
828 | break; | |
829 | case 5: | |
830 | spitz_bl_power(opaque, line, level); | |
831 | break; | |
832 | case 6: | |
833 | spitz_adc_temp_on(opaque, line, level); | |
834 | break; | |
835 | } | |
b00052e4 AZ |
836 | } |
837 | ||
838 | #define SPITZ_SCP_LED_GREEN 1 | |
839 | #define SPITZ_SCP_JK_B 2 | |
840 | #define SPITZ_SCP_CHRG_ON 3 | |
841 | #define SPITZ_SCP_MUTE_L 4 | |
842 | #define SPITZ_SCP_MUTE_R 5 | |
843 | #define SPITZ_SCP_CF_POWER 6 | |
844 | #define SPITZ_SCP_LED_ORANGE 7 | |
845 | #define SPITZ_SCP_JK_A 8 | |
846 | #define SPITZ_SCP_ADC_TEMP_ON 9 | |
847 | #define SPITZ_SCP2_IR_ON 1 | |
848 | #define SPITZ_SCP2_AKIN_PULLUP 2 | |
849 | #define SPITZ_SCP2_BACKLIGHT_CONT 7 | |
850 | #define SPITZ_SCP2_BACKLIGHT_ON 8 | |
851 | #define SPITZ_SCP2_MIC_BIAS 9 | |
852 | ||
bc24a225 PB |
853 | static void spitz_scoop_gpio_setup(PXA2xxState *cpu, |
854 | ScoopInfo *scp0, ScoopInfo *scp1) | |
b00052e4 | 855 | { |
38641a52 AZ |
856 | qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); |
857 | ||
e33d8cdb AZ |
858 | scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); |
859 | scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]); | |
860 | scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); | |
861 | scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); | |
b00052e4 | 862 | |
e33d8cdb AZ |
863 | if (scp1) { |
864 | scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); | |
865 | scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); | |
b00052e4 AZ |
866 | } |
867 | ||
e33d8cdb | 868 | scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); |
b00052e4 AZ |
869 | } |
870 | ||
871 | #define SPITZ_GPIO_HSYNC 22 | |
872 | #define SPITZ_GPIO_SD_DETECT 9 | |
873 | #define SPITZ_GPIO_SD_WP 81 | |
874 | #define SPITZ_GPIO_ON_RESET 89 | |
875 | #define SPITZ_GPIO_BAT_COVER 90 | |
876 | #define SPITZ_GPIO_CF1_IRQ 105 | |
877 | #define SPITZ_GPIO_CF1_CD 94 | |
878 | #define SPITZ_GPIO_CF2_IRQ 106 | |
879 | #define SPITZ_GPIO_CF2_CD 93 | |
880 | ||
38641a52 | 881 | static int spitz_hsync; |
b00052e4 | 882 | |
38641a52 | 883 | static void spitz_lcd_hsync_handler(void *opaque, int line, int level) |
b00052e4 | 884 | { |
bc24a225 | 885 | PXA2xxState *cpu = (PXA2xxState *) opaque; |
38641a52 | 886 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync); |
b00052e4 AZ |
887 | spitz_hsync ^= 1; |
888 | } | |
889 | ||
bc24a225 | 890 | static void spitz_gpio_setup(PXA2xxState *cpu, int slots) |
b00052e4 | 891 | { |
38641a52 | 892 | qemu_irq lcd_hsync; |
b00052e4 AZ |
893 | /* |
894 | * Bad hack: We toggle the LCD hsync GPIO on every GPIO status | |
895 | * read to satisfy broken guests that poll-wait for hsync. | |
896 | * Simulating a real hsync event would be less practical and | |
897 | * wouldn't guarantee that a guest ever exits the loop. | |
898 | */ | |
899 | spitz_hsync = 0; | |
38641a52 AZ |
900 | lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0]; |
901 | pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync); | |
902 | pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync); | |
b00052e4 AZ |
903 | |
904 | /* MMC/SD host */ | |
02ce600c AZ |
905 | pxa2xx_mmci_handlers(cpu->mmc, |
906 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP], | |
907 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]); | |
b00052e4 AZ |
908 | |
909 | /* Battery lock always closed */ | |
38641a52 | 910 | qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]); |
b00052e4 AZ |
911 | |
912 | /* Handle reset */ | |
38641a52 | 913 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset); |
b00052e4 AZ |
914 | |
915 | /* PCMCIA signals: card's IRQ and Card-Detect */ | |
b00052e4 | 916 | if (slots >= 1) |
38641a52 AZ |
917 | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], |
918 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ], | |
919 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]); | |
b00052e4 | 920 | if (slots >= 2) |
38641a52 AZ |
921 | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], |
922 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ], | |
923 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]); | |
b00052e4 AZ |
924 | |
925 | /* Initialise the screen rotation related signals */ | |
926 | spitz_gpio_invert[3] = 0; /* Always open */ | |
927 | if (graphic_rotate) { /* Tablet mode */ | |
928 | spitz_gpio_invert[4] = 0; | |
929 | } else { /* Portrait mode */ | |
930 | spitz_gpio_invert[4] = 1; | |
931 | } | |
38641a52 AZ |
932 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA], |
933 | spitz_gpio_invert[3]); | |
934 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB], | |
935 | spitz_gpio_invert[4]); | |
b00052e4 AZ |
936 | } |
937 | ||
b00052e4 AZ |
938 | /* Board init. */ |
939 | enum spitz_model_e { spitz, akita, borzoi, terrier }; | |
940 | ||
7fb4fdcf AZ |
941 | #define SPITZ_RAM 0x04000000 |
942 | #define SPITZ_ROM 0x00800000 | |
943 | ||
f93eb9ff AZ |
944 | static struct arm_boot_info spitz_binfo = { |
945 | .loader_start = PXA2XX_SDRAM_BASE, | |
946 | .ram_size = 0x04000000, | |
947 | }; | |
948 | ||
c227f099 | 949 | static void spitz_common_init(ram_addr_t ram_size, |
3023f332 | 950 | const char *kernel_filename, |
b00052e4 | 951 | const char *kernel_cmdline, const char *initrd_filename, |
4207117c | 952 | const char *cpu_model, enum spitz_model_e model, int arm_id) |
b00052e4 | 953 | { |
bc24a225 PB |
954 | PXA2xxState *cpu; |
955 | ScoopInfo *scp0, *scp1 = NULL; | |
b00052e4 | 956 | |
4207117c AZ |
957 | if (!cpu_model) |
958 | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; | |
b00052e4 | 959 | |
d95b2f8d | 960 | /* Setup CPU & memory */ |
3023f332 | 961 | cpu = pxa270_init(spitz_binfo.ram_size, cpu_model); |
b00052e4 AZ |
962 | |
963 | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); | |
964 | ||
7fb4fdcf | 965 | cpu_register_physical_memory(0, SPITZ_ROM, |
1724f049 | 966 | qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM); |
b00052e4 AZ |
967 | |
968 | /* Setup peripherals */ | |
969 | spitz_keyboard_register(cpu); | |
970 | ||
971 | spitz_ssp_attach(cpu); | |
972 | ||
e33d8cdb AZ |
973 | scp0 = scoop_init(cpu, 0, 0x10800000); |
974 | if (model != akita) { | |
975 | scp1 = scoop_init(cpu, 1, 0x08800040); | |
976 | } | |
b00052e4 | 977 | |
e33d8cdb | 978 | spitz_scoop_gpio_setup(cpu, scp0, scp1); |
b00052e4 AZ |
979 | |
980 | spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); | |
981 | ||
adb86c37 AZ |
982 | spitz_i2c_setup(cpu); |
983 | ||
984 | if (model == akita) | |
985 | spitz_akita_i2c_setup(cpu); | |
986 | ||
b00052e4 | 987 | if (model == terrier) |
bf5ee248 | 988 | /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */ |
15b18ec2 | 989 | spitz_microdrive_attach(cpu, 1); |
b00052e4 | 990 | else if (model != akita) |
15b18ec2 AZ |
991 | /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ |
992 | spitz_microdrive_attach(cpu, 0); | |
b00052e4 | 993 | |
f93eb9ff AZ |
994 | spitz_binfo.kernel_filename = kernel_filename; |
995 | spitz_binfo.kernel_cmdline = kernel_cmdline; | |
996 | spitz_binfo.initrd_filename = initrd_filename; | |
997 | spitz_binfo.board_id = arm_id; | |
998 | arm_load_kernel(cpu->env, &spitz_binfo); | |
f78630ab | 999 | sl_bootparam_write(SL_PXA_PARAM_BASE); |
b00052e4 AZ |
1000 | } |
1001 | ||
c227f099 | 1002 | static void spitz_init(ram_addr_t ram_size, |
3023f332 | 1003 | const char *boot_device, |
b00052e4 AZ |
1004 | const char *kernel_filename, const char *kernel_cmdline, |
1005 | const char *initrd_filename, const char *cpu_model) | |
1006 | { | |
fbe1b595 | 1007 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1008 | kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9); |
b00052e4 AZ |
1009 | } |
1010 | ||
c227f099 | 1011 | static void borzoi_init(ram_addr_t ram_size, |
3023f332 | 1012 | const char *boot_device, |
b00052e4 AZ |
1013 | const char *kernel_filename, const char *kernel_cmdline, |
1014 | const char *initrd_filename, const char *cpu_model) | |
1015 | { | |
fbe1b595 | 1016 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1017 | kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f); |
b00052e4 AZ |
1018 | } |
1019 | ||
c227f099 | 1020 | static void akita_init(ram_addr_t ram_size, |
3023f332 | 1021 | const char *boot_device, |
b00052e4 AZ |
1022 | const char *kernel_filename, const char *kernel_cmdline, |
1023 | const char *initrd_filename, const char *cpu_model) | |
1024 | { | |
fbe1b595 | 1025 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1026 | kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8); |
b00052e4 AZ |
1027 | } |
1028 | ||
c227f099 | 1029 | static void terrier_init(ram_addr_t ram_size, |
3023f332 | 1030 | const char *boot_device, |
b00052e4 AZ |
1031 | const char *kernel_filename, const char *kernel_cmdline, |
1032 | const char *initrd_filename, const char *cpu_model) | |
1033 | { | |
fbe1b595 | 1034 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1035 | kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f); |
b00052e4 AZ |
1036 | } |
1037 | ||
11be4b3e | 1038 | static QEMUMachine akitapda_machine = { |
4b32e168 AL |
1039 | .name = "akita", |
1040 | .desc = "Akita PDA (PXA270)", | |
1041 | .init = akita_init, | |
b00052e4 AZ |
1042 | }; |
1043 | ||
f80f9ec9 | 1044 | static QEMUMachine spitzpda_machine = { |
4b32e168 AL |
1045 | .name = "spitz", |
1046 | .desc = "Spitz PDA (PXA270)", | |
1047 | .init = spitz_init, | |
b00052e4 AZ |
1048 | }; |
1049 | ||
f80f9ec9 | 1050 | static QEMUMachine borzoipda_machine = { |
4b32e168 AL |
1051 | .name = "borzoi", |
1052 | .desc = "Borzoi PDA (PXA270)", | |
1053 | .init = borzoi_init, | |
b00052e4 AZ |
1054 | }; |
1055 | ||
f80f9ec9 | 1056 | static QEMUMachine terrierpda_machine = { |
4b32e168 AL |
1057 | .name = "terrier", |
1058 | .desc = "Terrier PDA (PXA270)", | |
1059 | .init = terrier_init, | |
b00052e4 | 1060 | }; |
a984a69e | 1061 | |
f80f9ec9 AL |
1062 | static void spitz_machine_init(void) |
1063 | { | |
1064 | qemu_register_machine(&akitapda_machine); | |
1065 | qemu_register_machine(&spitzpda_machine); | |
1066 | qemu_register_machine(&borzoipda_machine); | |
1067 | qemu_register_machine(&terrierpda_machine); | |
1068 | } | |
1069 | ||
1070 | machine_init(spitz_machine_init); | |
1071 | ||
a984a69e | 1072 | static SSISlaveInfo corgi_ssp_info = { |
074f2fff GH |
1073 | .qdev.name = "corgi-ssp", |
1074 | .qdev.size = sizeof(CorgiSSPState), | |
a984a69e PB |
1075 | .init = corgi_ssp_init, |
1076 | .transfer = corgi_ssp_transfer | |
1077 | }; | |
1078 | ||
1079 | static SSISlaveInfo spitz_lcdtg_info = { | |
074f2fff GH |
1080 | .qdev.name = "spitz-lcdtg", |
1081 | .qdev.size = sizeof(SpitzLCDTG), | |
a984a69e PB |
1082 | .init = spitz_lcdtg_init, |
1083 | .transfer = spitz_lcdtg_transfer | |
1084 | }; | |
1085 | ||
1086 | static void spitz_register_devices(void) | |
1087 | { | |
074f2fff GH |
1088 | ssi_register_slave(&corgi_ssp_info); |
1089 | ssi_register_slave(&spitz_lcdtg_info); | |
a984a69e PB |
1090 | } |
1091 | ||
1092 | device_init(spitz_register_devices) |