[qemu.git] / hw / misc / imx31_ccm.c

/*
 * IMX31 Clock Control Module
 *
 * Copyright (C) 2012 NICTA
 * Updated by Jean-Christophe Dubois <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * To get the timer frequencies right, we need to emulate at least part of
 * the i.MX31 CCM.
 */

#include "hw/misc/imx31_ccm.h"

#define CKIH_FREQ 26000000 /* 26MHz crystal input */

#ifndef DEBUG_IMX31_CCM
#define DEBUG_IMX31_CCM 0
#endif

#define DPRINTF(fmt, args...) \
    do { \
        if (DEBUG_IMX31_CCM) { \
            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
                                             __func__, ##args); \
        } \
    } while (0)

static char const *imx31_ccm_reg_name(uint32_t reg)
{
    static char unknown[20];

    switch (reg) {
    case IMX31_CCM_CCMR_REG:
        return "CCMR";
    case IMX31_CCM_PDR0_REG:
        return "PDR0";
    case IMX31_CCM_PDR1_REG:
        return "PDR1";
    case IMX31_CCM_RCSR_REG:
        return "RCSR";
    case IMX31_CCM_MPCTL_REG:
        return "MPCTL";
    case IMX31_CCM_UPCTL_REG:
        return "UPCTL";
    case IMX31_CCM_SPCTL_REG:
        return "SPCTL";
    case IMX31_CCM_COSR_REG:
        return "COSR";
    case IMX31_CCM_CGR0_REG:
        return "CGR0";
    case IMX31_CCM_CGR1_REG:
        return "CGR1";
    case IMX31_CCM_CGR2_REG:
        return "CGR2";
    case IMX31_CCM_WIMR_REG:
        return "WIMR";
    case IMX31_CCM_LDC_REG:
        return "LDC";
    case IMX31_CCM_DCVR0_REG:
        return "DCVR0";
    case IMX31_CCM_DCVR1_REG:
        return "DCVR1";
    case IMX31_CCM_DCVR2_REG:
        return "DCVR2";
    case IMX31_CCM_DCVR3_REG:
        return "DCVR3";
    case IMX31_CCM_LTR0_REG:
        return "LTR0";
    case IMX31_CCM_LTR1_REG:
        return "LTR1";
    case IMX31_CCM_LTR2_REG:
        return "LTR2";
    case IMX31_CCM_LTR3_REG:
        return "LTR3";
    case IMX31_CCM_LTBR0_REG:
        return "LTBR0";
    case IMX31_CCM_LTBR1_REG:
        return "LTBR1";
    case IMX31_CCM_PMCR0_REG:
        return "PMCR0";
    case IMX31_CCM_PMCR1_REG:
        return "PMCR1";
    case IMX31_CCM_PDR2_REG:
        return "PDR2";
    default:
        sprintf(unknown, "[%d ?]", reg);
        return unknown;
    }
}

static const VMStateDescription vmstate_imx31_ccm = {
    .name = TYPE_IMX31_CCM,
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
        VMSTATE_END_OF_LIST()
    },
};

static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
{
    uint32_t freq = 0;
    IMX31CCMState *s = IMX31_CCM(dev);

    if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
        if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
            freq = CKIL_FREQ;
            if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
                freq *= 1024;
            }
        } 
    } else {
        freq = CKIH_FREQ;
    }

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
                            imx31_ccm_get_pll_ref_clk(dev));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
        !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
        freq = imx31_ccm_get_pll_ref_clk(dev);
    } else {
        freq = imx31_ccm_get_mpll_clk(dev);
    }

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_mcu_main_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MCU));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_mcu_main_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], HSP));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_mcu_main_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
{
    uint32_t freq;
    IMX31CCMState *s = IMX31_CCM(dev);

    freq = imx31_ccm_get_hclk_clk(dev)
           / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));

    DPRINTF("freq = %d\n", freq);

    return freq;
}

static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
{
    uint32_t freq = 0;

    switch (clock) {
    case NOCLK:
        break;
    case CLK_MCU:
        freq = imx31_ccm_get_mcu_clk(dev);
        break;
    case CLK_HSP:
        freq = imx31_ccm_get_hsp_clk(dev);
        break;
    case CLK_IPG:
        freq = imx31_ccm_get_ipg_clk(dev);
        break;
    case CLK_32k:
        freq = CKIL_FREQ;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
                      TYPE_IMX31_CCM, __func__, clock);
        break;
    }

    DPRINTF("Clock = %d) = %d\n", clock, freq);

    return freq;
}

static void imx31_ccm_reset(DeviceState *dev)
{
    IMX31CCMState *s = IMX31_CCM(dev);

    DPRINTF("()\n");

    memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);

    s->reg[IMX31_CCM_CCMR_REG]   = 0x074b0b7d;
    s->reg[IMX31_CCM_PDR0_REG]   = 0xff870b48;
    s->reg[IMX31_CCM_PDR1_REG]   = 0x49fcfe7f;
    s->reg[IMX31_CCM_RCSR_REG]   = 0x007f0000;
    s->reg[IMX31_CCM_MPCTL_REG]  = 0x04001800;
    s->reg[IMX31_CCM_UPCTL_REG]  = 0x04051c03;
    s->reg[IMX31_CCM_SPCTL_REG]  = 0x04043001;
    s->reg[IMX31_CCM_COSR_REG]   = 0x00000280;
    s->reg[IMX31_CCM_CGR0_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_CGR1_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_CGR2_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_WIMR_REG]   = 0xffffffff;
    s->reg[IMX31_CCM_LTR1_REG]   = 0x00004040;
    s->reg[IMX31_CCM_PMCR0_REG]  = 0x80209828;
    s->reg[IMX31_CCM_PMCR1_REG]  = 0x00aa0000;
    s->reg[IMX31_CCM_PDR2_REG]   = 0x00000285;
}

static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
{
    uint32_t value = 0;
    IMX31CCMState *s = (IMX31CCMState *)opaque;

    if ((offset >> 2) < IMX31_CCM_MAX_REG) {
        value = s->reg[offset >> 2];
    } else {
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
    }

    DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
            value);

    return (uint64_t)value;
}

static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
                            unsigned size)
{
    IMX31CCMState *s = (IMX31CCMState *)opaque;

    DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
            (uint32_t)value);

    switch (offset >> 2) {
    case IMX31_CCM_CCMR_REG:
        s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
        break;
    case IMX31_CCM_PDR0_REG:
        s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
        break;
    case IMX31_CCM_PDR1_REG:
        s->reg[IMX31_CCM_PDR1_REG] = value;
        break;
    case IMX31_CCM_MPCTL_REG:
        s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
        break;
    case IMX31_CCM_SPCTL_REG:
        s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
        break;
    case IMX31_CCM_CGR0_REG:
        s->reg[IMX31_CCM_CGR0_REG] = value;
        break;
    case IMX31_CCM_CGR1_REG:
        s->reg[IMX31_CCM_CGR1_REG] = value;
        break;
    case IMX31_CCM_CGR2_REG:
        s->reg[IMX31_CCM_CGR2_REG] = value;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
        break;
    }
}

static const struct MemoryRegionOps imx31_ccm_ops = {
    .read = imx31_ccm_read,
    .write = imx31_ccm_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        /*
         * Our device would not work correctly if the guest was doing
         * unaligned access. This might not be a limitation on the real
         * device but in practice there is no reason for a guest to access
         * this device unaligned.
         */
        .min_access_size = 4,
        .max_access_size = 4,
        .unaligned = false,
    },

};

static void imx31_ccm_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    SysBusDevice *sd = SYS_BUS_DEVICE(obj);
    IMX31CCMState *s = IMX31_CCM(obj);

    memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
                          TYPE_IMX31_CCM, 0x1000);
    sysbus_init_mmio(sd, &s->iomem);
}

static void imx31_ccm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc  = DEVICE_CLASS(klass);
    IMXCCMClass *ccm = IMX_CCM_CLASS(klass);

    dc->reset = imx31_ccm_reset;
    dc->vmsd  = &vmstate_imx31_ccm;
    dc->desc  = "i.MX31 Clock Control Module";

    ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
}

static const TypeInfo imx31_ccm_info = {
    .name          = TYPE_IMX31_CCM,
    .parent        = TYPE_IMX_CCM,
    .instance_size = sizeof(IMX31CCMState),
    .instance_init = imx31_ccm_init,
    .class_init    = imx31_ccm_class_init,
};

static void imx31_ccm_register_types(void)
{
    type_register_static(&imx31_ccm_info);
}

type_init(imx31_ccm_register_types)
Commit	Line	Data
cb54d868 JCD	1	/*
	2	* IMX31 Clock Control Module
	3	*
	4	* Copyright (C) 2012 NICTA
	5	* Updated by Jean-Christophe Dubois <[email protected]>
	6	*
	7	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	8	* See the COPYING file in the top-level directory.
	9	*
	10	* To get the timer frequencies right, we need to emulate at least part of
	11	* the i.MX31 CCM.
	12	*/
	13
	14	#include "hw/misc/imx31_ccm.h"
	15
	16	#define CKIH_FREQ 26000000 /* 26MHz crystal input */
	17
	18	#ifndef DEBUG_IMX31_CCM
	19	#define DEBUG_IMX31_CCM 0
	20	#endif
	21
	22	#define DPRINTF(fmt, args...) \
	23	do { \
	24	if (DEBUG_IMX31_CCM) { \
	25	fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
	26	__func__, ##args); \
	27	} \
	28	} while (0)
	29
	30	static char const *imx31_ccm_reg_name(uint32_t reg)
	31	{
fea01f96 JCD	32	static char unknown[20];
fea01f96 JCD	33
cb54d868	34	switch (reg) {
fea01f96	35	case IMX31_CCM_CCMR_REG:
cb54d868	36	return "CCMR";
fea01f96	37	case IMX31_CCM_PDR0_REG:
cb54d868	38	return "PDR0";
fea01f96	39	case IMX31_CCM_PDR1_REG:
cb54d868	40	return "PDR1";
fea01f96	41	case IMX31_CCM_RCSR_REG:
cb54d868	42	return "RCSR";
fea01f96	43	case IMX31_CCM_MPCTL_REG:
cb54d868	44	return "MPCTL";
fea01f96	45	case IMX31_CCM_UPCTL_REG:
cb54d868	46	return "UPCTL";
fea01f96	47	case IMX31_CCM_SPCTL_REG:
cb54d868	48	return "SPCTL";
fea01f96	49	case IMX31_CCM_COSR_REG:
cb54d868	50	return "COSR";
fea01f96	51	case IMX31_CCM_CGR0_REG:
cb54d868	52	return "CGR0";
fea01f96	53	case IMX31_CCM_CGR1_REG:
cb54d868	54	return "CGR1";
fea01f96	55	case IMX31_CCM_CGR2_REG:
cb54d868	56	return "CGR2";
fea01f96	57	case IMX31_CCM_WIMR_REG:
cb54d868	58	return "WIMR";
fea01f96	59	case IMX31_CCM_LDC_REG:
cb54d868	60	return "LDC";
fea01f96	61	case IMX31_CCM_DCVR0_REG:
cb54d868	62	return "DCVR0";
fea01f96	63	case IMX31_CCM_DCVR1_REG:
cb54d868	64	return "DCVR1";
fea01f96	65	case IMX31_CCM_DCVR2_REG:
cb54d868	66	return "DCVR2";
fea01f96	67	case IMX31_CCM_DCVR3_REG:
cb54d868	68	return "DCVR3";
fea01f96	69	case IMX31_CCM_LTR0_REG:
cb54d868	70	return "LTR0";
fea01f96	71	case IMX31_CCM_LTR1_REG:
cb54d868	72	return "LTR1";
fea01f96	73	case IMX31_CCM_LTR2_REG:
cb54d868	74	return "LTR2";
fea01f96	75	case IMX31_CCM_LTR3_REG:
cb54d868	76	return "LTR3";
fea01f96	77	case IMX31_CCM_LTBR0_REG:
cb54d868	78	return "LTBR0";
fea01f96	79	case IMX31_CCM_LTBR1_REG:
cb54d868	80	return "LTBR1";
fea01f96	81	case IMX31_CCM_PMCR0_REG:
cb54d868	82	return "PMCR0";
fea01f96	83	case IMX31_CCM_PMCR1_REG:
cb54d868	84	return "PMCR1";
fea01f96	85	case IMX31_CCM_PDR2_REG:
cb54d868 JCD	86	return "PDR2";
cb54d868 JCD	87	default:
fea01f96 JCD	88	sprintf(unknown, "[%d ?]", reg);
fea01f96 JCD	89	return unknown;
cb54d868 JCD	90	}
	91	}
	92
	93	static const VMStateDescription vmstate_imx31_ccm = {
	94	.name = TYPE_IMX31_CCM,
fea01f96 JCD	95	.version_id = 2,
fea01f96 JCD	96	.minimum_version_id = 2,
cb54d868	97	.fields = (VMStateField[]) {
fea01f96	98	VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
cb54d868 JCD	99	VMSTATE_END_OF_LIST()
	100	},
	101	};
	102
	103	static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
	104	{
	105	uint32_t freq = 0;
	106	IMX31CCMState *s = IMX31_CCM(dev);
	107
fea01f96 JCD	108	if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
fea01f96 JCD	109	if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
cb54d868	110	freq = CKIL_FREQ;
fea01f96	111	if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
cb54d868 JCD	112	freq *= 1024;
	113	}
	114	}
	115	} else {
	116	freq = CKIH_FREQ;
	117	}
	118
	119	DPRINTF("freq = %d\n", freq);
	120
	121	return freq;
	122	}
	123
	124	static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
	125	{
	126	uint32_t freq;
	127	IMX31CCMState *s = IMX31_CCM(dev);
	128
fea01f96 JCD	129	freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
fea01f96 JCD	130	imx31_ccm_get_pll_ref_clk(dev));
cb54d868 JCD	131
	132	DPRINTF("freq = %d\n", freq);
	133
	134	return freq;
	135	}
	136
	137	static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
	138	{
	139	uint32_t freq;
	140	IMX31CCMState *s = IMX31_CCM(dev);
	141
fea01f96 JCD	142	if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) \|\|
fea01f96 JCD	143	!(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
cb54d868 JCD	144	freq = imx31_ccm_get_pll_ref_clk(dev);
	145	} else {
	146	freq = imx31_ccm_get_mpll_clk(dev);
	147	}
	148
	149	DPRINTF("freq = %d\n", freq);
	150
	151	return freq;
	152	}
	153
	154	static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev)
	155	{
	156	uint32_t freq;
	157	IMX31CCMState *s = IMX31_CCM(dev);
	158
fea01f96 JCD	159	freq = imx31_ccm_get_mcu_main_clk(dev)
fea01f96 JCD	160	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MCU));
cb54d868 JCD	161
	162	DPRINTF("freq = %d\n", freq);
	163
	164	return freq;
	165	}
	166
	167	static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev)
	168	{
	169	uint32_t freq;
	170	IMX31CCMState *s = IMX31_CCM(dev);
	171
fea01f96 JCD	172	freq = imx31_ccm_get_mcu_main_clk(dev)
fea01f96 JCD	173	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], HSP));
cb54d868 JCD	174
	175	DPRINTF("freq = %d\n", freq);
	176
	177	return freq;
	178	}
	179
	180	static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
	181	{
	182	uint32_t freq;
	183	IMX31CCMState *s = IMX31_CCM(dev);
	184
fea01f96 JCD	185	freq = imx31_ccm_get_mcu_main_clk(dev)
fea01f96 JCD	186	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
cb54d868 JCD	187
	188	DPRINTF("freq = %d\n", freq);
	189
	190	return freq;
	191	}
	192
	193	static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
	194	{
	195	uint32_t freq;
	196	IMX31CCMState *s = IMX31_CCM(dev);
	197
fea01f96 JCD	198	freq = imx31_ccm_get_hclk_clk(dev)
fea01f96 JCD	199	/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
cb54d868 JCD	200
	201	DPRINTF("freq = %d\n", freq);
	202
	203	return freq;
	204	}
	205
	206	static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
	207	{
	208	uint32_t freq = 0;
	209
	210	switch (clock) {
	211	case NOCLK:
	212	break;
	213	case CLK_MCU:
	214	freq = imx31_ccm_get_mcu_clk(dev);
	215	break;
	216	case CLK_HSP:
	217	freq = imx31_ccm_get_hsp_clk(dev);
	218	break;
	219	case CLK_IPG:
	220	freq = imx31_ccm_get_ipg_clk(dev);
	221	break;
	222	case CLK_32k:
	223	freq = CKIL_FREQ;
	224	break;
	225	default:
	226	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
	227	TYPE_IMX31_CCM, __func__, clock);
	228	break;
	229	}
	230
	231	DPRINTF("Clock = %d) = %d\n", clock, freq);
	232
	233	return freq;
	234	}
	235
	236	static void imx31_ccm_reset(DeviceState *dev)
	237	{
	238	IMX31CCMState *s = IMX31_CCM(dev);
	239
	240	DPRINTF("()\n");
	241
fea01f96 JCD	242	memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
	243
	244	s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
	245	s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
	246	s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
	247	s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
	248	s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
	249	s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
	250	s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
	251	s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
	252	s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
	253	s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
	254	s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
	255	s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
	256	s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
	257	s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
	258	s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
	259	s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
cb54d868 JCD	260	}
	261
	262	static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
	263	{
3a87d009	264	uint32_t value = 0;
cb54d868 JCD	265	IMX31CCMState s = (IMX31CCMState )opaque;
cb54d868 JCD	266
fea01f96 JCD	267	if ((offset >> 2) < IMX31_CCM_MAX_REG) {
	268	value = s->reg[offset >> 2];
	269	} else {
cb54d868 JCD	270	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
cb54d868 JCD	271	HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
cb54d868 JCD	272	}
	273
	274	DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
	275	value);
	276
	277	return (uint64_t)value;
	278	}
	279
	280	static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
	281	unsigned size)
	282	{
	283	IMX31CCMState s = (IMX31CCMState )opaque;
	284
	285	DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
	286	(uint32_t)value);
	287
	288	switch (offset >> 2) {
fea01f96 JCD	289	case IMX31_CCM_CCMR_REG:
fea01f96 JCD	290	s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF \| (value & 0x3b6fdfff);
cb54d868	291	break;
fea01f96 JCD	292	case IMX31_CCM_PDR0_REG:
fea01f96 JCD	293	s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
cb54d868	294	break;
fea01f96 JCD	295	case IMX31_CCM_PDR1_REG:
fea01f96 JCD	296	s->reg[IMX31_CCM_PDR1_REG] = value;
cb54d868	297	break;
fea01f96 JCD	298	case IMX31_CCM_MPCTL_REG:
fea01f96 JCD	299	s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
cb54d868	300	break;
fea01f96 JCD	301	case IMX31_CCM_SPCTL_REG:
fea01f96 JCD	302	s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
cb54d868	303	break;
fea01f96 JCD	304	case IMX31_CCM_CGR0_REG:
fea01f96 JCD	305	s->reg[IMX31_CCM_CGR0_REG] = value;
cb54d868	306	break;
fea01f96 JCD	307	case IMX31_CCM_CGR1_REG:
fea01f96 JCD	308	s->reg[IMX31_CCM_CGR1_REG] = value;
cb54d868	309	break;
fea01f96 JCD	310	case IMX31_CCM_CGR2_REG:
fea01f96 JCD	311	s->reg[IMX31_CCM_CGR2_REG] = value;
cb54d868 JCD	312	break;
	313	default:
	314	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
	315	HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
	316	break;
	317	}
	318	}
	319
	320	static const struct MemoryRegionOps imx31_ccm_ops = {
	321	.read = imx31_ccm_read,
	322	.write = imx31_ccm_write,
	323	.endianness = DEVICE_NATIVE_ENDIAN,
	324	.valid = {
	325	/*
	326	* Our device would not work correctly if the guest was doing
	327	* unaligned access. This might not be a limitation on the real
	328	* device but in practice there is no reason for a guest to access
	329	* this device unaligned.
	330	*/
	331	.min_access_size = 4,
	332	.max_access_size = 4,
	333	.unaligned = false,
	334	},
	335
	336	};
	337
	338	static void imx31_ccm_init(Object *obj)
	339	{
	340	DeviceState *dev = DEVICE(obj);
	341	SysBusDevice *sd = SYS_BUS_DEVICE(obj);
	342	IMX31CCMState *s = IMX31_CCM(obj);
	343
	344	memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
	345	TYPE_IMX31_CCM, 0x1000);
	346	sysbus_init_mmio(sd, &s->iomem);
	347	}
	348
	349	static void imx31_ccm_class_init(ObjectClass klass, void data)
	350	{
	351	DeviceClass *dc = DEVICE_CLASS(klass);
	352	IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
	353
	354	dc->reset = imx31_ccm_reset;
	355	dc->vmsd = &vmstate_imx31_ccm;
	356	dc->desc = "i.MX31 Clock Control Module";
	357
	358	ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
	359	}
	360
	361	static const TypeInfo imx31_ccm_info = {
	362	.name = TYPE_IMX31_CCM,
	363	.parent = TYPE_IMX_CCM,
	364	.instance_size = sizeof(IMX31CCMState),
	365	.instance_init = imx31_ccm_init,
	366	.class_init = imx31_ccm_class_init,
	367	};
	368
	369	static void imx31_ccm_register_types(void)
	370	{
	371	type_register_static(&imx31_ccm_info);
	372	}
	373
	374	type_init(imx31_ccm_register_types)