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target-tilegx: Handle basic load and store instructions
[qemu.git] / target-tilegx / translate.c
CommitLineData
8fd29dd7
RH		 1/*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21#include "cpu.h"
22#include "qemu/log.h"
23#include "disas/disas.h"
24#include "tcg-op.h"
25#include "exec/cpu_ldst.h"
26#include "opcode_tilegx.h"
27
28#define FMT64X "%016" PRIx64
29
30static TCGv_ptr cpu_env;
31static TCGv cpu_pc;
32static TCGv cpu_regs[TILEGX_R_COUNT];
33
34static const char * const reg_names[64] = {
35 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
36 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
37 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
38 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
39 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
40 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
41 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
42 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
43};
44
45/* Modified registers are cached in temporaries until the end of the bundle. */
46typedef struct {
47 unsigned reg;
48 TCGv val;
49} DisasContextTemp;
50
51#define MAX_WRITEBACK 4
52
53/* This is the state at translation time. */
54typedef struct {
55 uint64_t pc; /* Current pc */
56
57 TCGv zero; /* For zero register */
58
59 DisasContextTemp wb[MAX_WRITEBACK];
60 int num_wb;
61 int mmuidx;
62 bool exit_tb;
63
64 struct {
65 TCGCond cond; /* branch condition */
66 TCGv dest; /* branch destination */
67 TCGv val1; /* value to be compared against zero, for cond */
68 } jmp; /* Jump object, only once in each TB block */
69} DisasContext;
70
71#include "exec/gen-icount.h"
72
73/* Differentiate the various pipe encodings. */
74#define TY_X0 0
75#define TY_X1 1
76#define TY_Y0 2
77#define TY_Y1 3
78
79/* Remerge the base opcode and extension fields for switching.
80 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
81 Y2 opcode field is 2 bits. */
82#define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
83
84/* Similar, but for Y2 only. */
85#define OEY2(OP, MODE) (OP + MODE * 4)
86
87/* Similar, but make sure opcode names match up. */
88#define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
89#define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
90#define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
91#define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
92#define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
93#define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
94#define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
95
96
97static void gen_exception(DisasContext *dc, TileExcp num)
98{
99 TCGv_i32 tmp;
100
101 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
102
103 tmp = tcg_const_i32(num);
104 gen_helper_exception(cpu_env, tmp);
105 tcg_temp_free_i32(tmp);
106 dc->exit_tb = true;
107}
108
a9fdfc7e
RH		 109static bool check_gr(DisasContext *dc, uint8_t reg)
110{
111 if (likely(reg < TILEGX_R_COUNT)) {
112 return true;
113 }
114
115 switch (reg) {
116 case TILEGX_R_SN:
117 case TILEGX_R_ZERO:
118 break;
119 case TILEGX_R_IDN0:
120 case TILEGX_R_IDN1:
121 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
122 break;
123 case TILEGX_R_UDN0:
124 case TILEGX_R_UDN1:
125 case TILEGX_R_UDN2:
126 case TILEGX_R_UDN3:
127 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
128 break;
129 default:
130 g_assert_not_reached();
131 }
132 return false;
133}
134
135static TCGv load_zero(DisasContext *dc)
136{
137 if (TCGV_IS_UNUSED_I64(dc->zero)) {
138 dc->zero = tcg_const_i64(0);
139 }
140 return dc->zero;
141}
142
143static TCGv load_gr(DisasContext *dc, unsigned reg)
144{
145 if (check_gr(dc, reg)) {
146 return cpu_regs[reg];
147 }
148 return load_zero(dc);
149}
150
151static TCGv dest_gr(DisasContext *dc, unsigned reg)
152{
153 int n;
154
155 /* Skip the result, mark the exception if necessary, and continue */
156 check_gr(dc, reg);
157
158 n = dc->num_wb++;
159 dc->wb[n].reg = reg;
160 return dc->wb[n].val = tcg_temp_new_i64();
161}
162
89b8c750
RH		 163static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
164 void (*operate)(TCGv, TCGv, TCGv))
165{
166 TCGv t0 = tcg_temp_new();
167
168 tcg_gen_ext32s_tl(tdest, tsrca);
169 tcg_gen_ext32s_tl(t0, tsrcb);
170 operate(tdest, tdest, t0);
171
172 tcg_gen_movi_tl(t0, 0x7fffffff);
173 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
174 tcg_gen_movi_tl(t0, -0x80000000LL);
175 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
176
177 tcg_temp_free(t0);
178}
179
7f41a8d6
RH		 180/* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
181 specified by the bottom 3 bits of TSRCB, and set TDEST to the
182 low 64 bits of the resulting value. */
183static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
184{
185 TCGv t0 = tcg_temp_new();
186
187 tcg_gen_andi_tl(t0, tsrcb, 7);
188 tcg_gen_shli_tl(t0, t0, 3);
189 tcg_gen_shr_tl(tdest, tsrcd, t0);
190
191 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
192 arithmetic on a 6-bit field tells us that 64 - t0 is equal
193 to (t0 ^ 63) + 1. So we can do the shift in two parts,
194 neither of which will be an invalid shift by 64. */
195 tcg_gen_xori_tl(t0, t0, 63);
196 tcg_gen_shl_tl(t0, tsrca, t0);
197 tcg_gen_shli_tl(t0, t0, 1);
198 tcg_gen_or_tl(tdest, tdest, t0);
199
200 tcg_temp_free(t0);
201}
202
203/* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
204 right shift is an immediate. */
205static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
206{
207 TCGv t0 = tcg_temp_new();
208
209 tcg_gen_shri_tl(t0, tsrcb, shr);
210 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
211 tcg_gen_or_tl(tdest, tdest, t0);
212
213 tcg_temp_free(t0);
214}
215
0426335d
RH		 216static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
217 unsigned srcb, TCGMemOp memop, const char *name)
218{
219 if (dest) {
220 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
221 }
222
223 tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
224 dc->mmuidx, memop);
225
226 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
227 reg_names[srca], reg_names[srcb]);
228 return TILEGX_EXCP_NONE;
229}
7f41a8d6 230
8fd29dd7
RH		 231static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
232 unsigned dest, unsigned srca)
233{
a9fdfc7e 234 TCGv tdest, tsrca;
8fd29dd7 235 const char *mnemonic;
0426335d 236 TCGMemOp memop;
8fd29dd7
RH		 237
238 /* Eliminate nops before doing anything else. */
239 switch (opext) {
240 case OE_RR_Y0(NOP):
241 case OE_RR_Y1(NOP):
242 case OE_RR_X0(NOP):
243 case OE_RR_X1(NOP):
244 mnemonic = "nop";
245 goto do_nop;
246 case OE_RR_Y0(FNOP):
247 case OE_RR_Y1(FNOP):
248 case OE_RR_X0(FNOP):
249 case OE_RR_X1(FNOP):
250 mnemonic = "fnop";
251 do_nop:
252 if (srca || dest) {
253 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
254 }
255 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
256 return TILEGX_EXCP_NONE;
257 }
258
a9fdfc7e
RH		 259 tdest = dest_gr(dc, dest);
260 tsrca = load_gr(dc, srca);
261
8fd29dd7
RH		 262 switch (opext) {
263 case OE_RR_X0(CNTLZ):
264 case OE_RR_Y0(CNTLZ):
7f41a8d6
RH		 265 gen_helper_cntlz(tdest, tsrca);
266 mnemonic = "cntlz";
267 break;
8fd29dd7
RH		 268 case OE_RR_X0(CNTTZ):
269 case OE_RR_Y0(CNTTZ):
7f41a8d6
RH		 270 gen_helper_cnttz(tdest, tsrca);
271 mnemonic = "cnttz";
272 break;
8fd29dd7
RH		 273 case OE_RR_X1(DRAIN):
274 case OE_RR_X1(DTLBPR):
275 case OE_RR_X1(FINV):
276 case OE_RR_X1(FLUSHWB):
277 case OE_RR_X1(FLUSH):
278 case OE_RR_X0(FSINGLE_PACK1):
279 case OE_RR_Y0(FSINGLE_PACK1):
280 case OE_RR_X1(ICOH):
281 case OE_RR_X1(ILL):
282 case OE_RR_Y1(ILL):
283 case OE_RR_X1(INV):
284 case OE_RR_X1(IRET):
285 case OE_RR_X1(JALRP):
286 case OE_RR_Y1(JALRP):
287 case OE_RR_X1(JALR):
288 case OE_RR_Y1(JALR):
289 case OE_RR_X1(JRP):
290 case OE_RR_Y1(JRP):
291 case OE_RR_X1(JR):
292 case OE_RR_Y1(JR):
0426335d 293 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 294 case OE_RR_X1(LD1S):
0426335d
RH		 295 memop = MO_SB;
296 mnemonic = "ld1s";
297 goto do_load;
8fd29dd7 298 case OE_RR_X1(LD1U):
0426335d
RH		 299 memop = MO_UB;
300 mnemonic = "ld1u";
301 goto do_load;
8fd29dd7 302 case OE_RR_X1(LD2S):
0426335d
RH		 303 memop = MO_TESW;
304 mnemonic = "ld2s";
305 goto do_load;
8fd29dd7 306 case OE_RR_X1(LD2U):
0426335d
RH		 307 memop = MO_TEUW;
308 mnemonic = "ld2u";
309 goto do_load;
8fd29dd7 310 case OE_RR_X1(LD4S):
0426335d
RH		 311 memop = MO_TESL;
312 mnemonic = "ld4s";
313 goto do_load;
8fd29dd7 314 case OE_RR_X1(LD4U):
0426335d
RH		 315 memop = MO_TEUL;
316 mnemonic = "ld4u";
317 goto do_load;
8fd29dd7 318 case OE_RR_X1(LDNT1S):
0426335d
RH		 319 memop = MO_SB;
320 mnemonic = "ldnt1s";
321 goto do_load;
8fd29dd7 322 case OE_RR_X1(LDNT1U):
0426335d
RH		 323 memop = MO_UB;
324 mnemonic = "ldnt1u";
325 goto do_load;
8fd29dd7 326 case OE_RR_X1(LDNT2S):
0426335d
RH		 327 memop = MO_TESW;
328 mnemonic = "ldnt2s";
329 goto do_load;
8fd29dd7 330 case OE_RR_X1(LDNT2U):
0426335d
RH		 331 memop = MO_TEUW;
332 mnemonic = "ldnt2u";
333 goto do_load;
8fd29dd7 334 case OE_RR_X1(LDNT4S):
0426335d
RH		 335 memop = MO_TESL;
336 mnemonic = "ldnt4s";
337 goto do_load;
8fd29dd7 338 case OE_RR_X1(LDNT4U):
0426335d
RH		 339 memop = MO_TEUL;
340 mnemonic = "ldnt4u";
341 goto do_load;
8fd29dd7 342 case OE_RR_X1(LDNT):
0426335d
RH		 343 memop = MO_TEQ;
344 mnemonic = "ldnt";
345 goto do_load;
8fd29dd7 346 case OE_RR_X1(LD):
0426335d
RH		 347 memop = MO_TEQ;
348 mnemonic = "ld";
349 do_load:
350 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
351 break;
352 case OE_RR_X1(LDNA):
353 tcg_gen_andi_tl(tdest, tsrca, ~7);
354 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
355 mnemonic = "ldna";
356 break;
8fd29dd7
RH		 357 case OE_RR_X1(LNK):
358 case OE_RR_Y1(LNK):
359 case OE_RR_X1(MF):
360 case OE_RR_X1(NAP):
7f41a8d6 361 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 362 case OE_RR_X0(PCNT):
363 case OE_RR_Y0(PCNT):
7f41a8d6
RH		 364 gen_helper_pcnt(tdest, tsrca);
365 mnemonic = "pcnt";
366 break;
8fd29dd7
RH		 367 case OE_RR_X0(REVBITS):
368 case OE_RR_Y0(REVBITS):
7f41a8d6
RH		 369 gen_helper_revbits(tdest, tsrca);
370 mnemonic = "revbits";
371 break;
8fd29dd7
RH		 372 case OE_RR_X0(REVBYTES):
373 case OE_RR_Y0(REVBYTES):
a9fdfc7e
RH		 374 tcg_gen_bswap64_tl(tdest, tsrca);
375 mnemonic = "revbytes";
376 break;
8fd29dd7
RH		 377 case OE_RR_X1(SWINT0):
378 case OE_RR_X1(SWINT1):
379 case OE_RR_X1(SWINT2):
380 case OE_RR_X1(SWINT3):
381 case OE_RR_X0(TBLIDXB0):
382 case OE_RR_Y0(TBLIDXB0):
383 case OE_RR_X0(TBLIDXB1):
384 case OE_RR_Y0(TBLIDXB1):
385 case OE_RR_X0(TBLIDXB2):
386 case OE_RR_Y0(TBLIDXB2):
387 case OE_RR_X0(TBLIDXB3):
388 case OE_RR_Y0(TBLIDXB3):
389 case OE_RR_X1(WH64):
390 default:
391 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
392 }
393
394 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
395 reg_names[dest], reg_names[srca]);
396 return TILEGX_EXCP_NONE;
397}
398
399static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
400 unsigned dest, unsigned srca, unsigned srcb)
401{
a9fdfc7e
RH		 402 TCGv tdest = dest_gr(dc, dest);
403 TCGv tsrca = load_gr(dc, srca);
404 TCGv tsrcb = load_gr(dc, srcb);
8fd29dd7
RH		 405 const char *mnemonic;
406
407 switch (opext) {
408 case OE_RRR(ADDXSC, 0, X0):
409 case OE_RRR(ADDXSC, 0, X1):
89b8c750
RH		 410 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
411 mnemonic = "addxsc";
412 break;
8fd29dd7
RH		 413 case OE_RRR(ADDX, 0, X0):
414 case OE_RRR(ADDX, 0, X1):
415 case OE_RRR(ADDX, 0, Y0):
416 case OE_RRR(ADDX, 0, Y1):
89b8c750
RH		 417 tcg_gen_add_tl(tdest, tsrca, tsrcb);
418 tcg_gen_ext32s_tl(tdest, tdest);
419 mnemonic = "addx";
420 break;
8fd29dd7
RH		 421 case OE_RRR(ADD, 0, X0):
422 case OE_RRR(ADD, 0, X1):
423 case OE_RRR(ADD, 0, Y0):
424 case OE_RRR(ADD, 0, Y1):
89b8c750
RH		 425 tcg_gen_add_tl(tdest, tsrca, tsrcb);
426 mnemonic = "add";
427 break;
8fd29dd7
RH		 428 case OE_RRR(AND, 0, X0):
429 case OE_RRR(AND, 0, X1):
430 case OE_RRR(AND, 5, Y0):
431 case OE_RRR(AND, 5, Y1):
a9fdfc7e
RH		 432 tcg_gen_and_tl(tdest, tsrca, tsrcb);
433 mnemonic = "and";
434 break;
8fd29dd7
RH		 435 case OE_RRR(CMOVEQZ, 0, X0):
436 case OE_RRR(CMOVEQZ, 4, Y0):
437 case OE_RRR(CMOVNEZ, 0, X0):
438 case OE_RRR(CMOVNEZ, 4, Y0):
439 case OE_RRR(CMPEQ, 0, X0):
440 case OE_RRR(CMPEQ, 0, X1):
441 case OE_RRR(CMPEQ, 3, Y0):
442 case OE_RRR(CMPEQ, 3, Y1):
443 case OE_RRR(CMPEXCH4, 0, X1):
444 case OE_RRR(CMPEXCH, 0, X1):
445 case OE_RRR(CMPLES, 0, X0):
446 case OE_RRR(CMPLES, 0, X1):
447 case OE_RRR(CMPLES, 2, Y0):
448 case OE_RRR(CMPLES, 2, Y1):
449 case OE_RRR(CMPLEU, 0, X0):
450 case OE_RRR(CMPLEU, 0, X1):
451 case OE_RRR(CMPLEU, 2, Y0):
452 case OE_RRR(CMPLEU, 2, Y1):
453 case OE_RRR(CMPLTS, 0, X0):
454 case OE_RRR(CMPLTS, 0, X1):
455 case OE_RRR(CMPLTS, 2, Y0):
456 case OE_RRR(CMPLTS, 2, Y1):
457 case OE_RRR(CMPLTU, 0, X0):
458 case OE_RRR(CMPLTU, 0, X1):
459 case OE_RRR(CMPLTU, 2, Y0):
460 case OE_RRR(CMPLTU, 2, Y1):
461 case OE_RRR(CMPNE, 0, X0):
462 case OE_RRR(CMPNE, 0, X1):
463 case OE_RRR(CMPNE, 3, Y0):
464 case OE_RRR(CMPNE, 3, Y1):
465 case OE_RRR(CMULAF, 0, X0):
466 case OE_RRR(CMULA, 0, X0):
467 case OE_RRR(CMULFR, 0, X0):
468 case OE_RRR(CMULF, 0, X0):
469 case OE_RRR(CMULHR, 0, X0):
470 case OE_RRR(CMULH, 0, X0):
471 case OE_RRR(CMUL, 0, X0):
472 case OE_RRR(CRC32_32, 0, X0):
473 case OE_RRR(CRC32_8, 0, X0):
7f41a8d6 474 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 475 case OE_RRR(DBLALIGN2, 0, X0):
476 case OE_RRR(DBLALIGN2, 0, X1):
7f41a8d6
RH		 477 gen_dblaligni(tdest, tsrca, tsrcb, 16);
478 mnemonic = "dblalign2";
479 break;
8fd29dd7
RH		 480 case OE_RRR(DBLALIGN4, 0, X0):
481 case OE_RRR(DBLALIGN4, 0, X1):
7f41a8d6
RH		 482 gen_dblaligni(tdest, tsrca, tsrcb, 32);
483 mnemonic = "dblalign4";
484 break;
8fd29dd7
RH		 485 case OE_RRR(DBLALIGN6, 0, X0):
486 case OE_RRR(DBLALIGN6, 0, X1):
7f41a8d6
RH		 487 gen_dblaligni(tdest, tsrca, tsrcb, 48);
488 mnemonic = "dblalign6";
489 break;
8fd29dd7 490 case OE_RRR(DBLALIGN, 0, X0):
7f41a8d6
RH		 491 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
492 mnemonic = "dblalign";
493 break;
8fd29dd7
RH		 494 case OE_RRR(EXCH4, 0, X1):
495 case OE_RRR(EXCH, 0, X1):
496 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
497 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
498 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
499 case OE_RRR(FDOUBLE_PACK1, 0, X0):
500 case OE_RRR(FDOUBLE_PACK2, 0, X0):
501 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
502 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
503 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
504 case OE_RRR(FETCHADD4, 0, X1):
505 case OE_RRR(FETCHADDGEZ4, 0, X1):
506 case OE_RRR(FETCHADDGEZ, 0, X1):
507 case OE_RRR(FETCHADD, 0, X1):
508 case OE_RRR(FETCHAND4, 0, X1):
509 case OE_RRR(FETCHAND, 0, X1):
510 case OE_RRR(FETCHOR4, 0, X1):
511 case OE_RRR(FETCHOR, 0, X1):
512 case OE_RRR(FSINGLE_ADD1, 0, X0):
513 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
514 case OE_RRR(FSINGLE_MUL1, 0, X0):
515 case OE_RRR(FSINGLE_MUL2, 0, X0):
516 case OE_RRR(FSINGLE_PACK2, 0, X0):
517 case OE_RRR(FSINGLE_SUB1, 0, X0):
518 case OE_RRR(MNZ, 0, X0):
519 case OE_RRR(MNZ, 0, X1):
520 case OE_RRR(MNZ, 4, Y0):
521 case OE_RRR(MNZ, 4, Y1):
522 case OE_RRR(MULAX, 0, X0):
523 case OE_RRR(MULAX, 3, Y0):
524 case OE_RRR(MULA_HS_HS, 0, X0):
525 case OE_RRR(MULA_HS_HS, 9, Y0):
526 case OE_RRR(MULA_HS_HU, 0, X0):
527 case OE_RRR(MULA_HS_LS, 0, X0):
528 case OE_RRR(MULA_HS_LU, 0, X0):
529 case OE_RRR(MULA_HU_HU, 0, X0):
530 case OE_RRR(MULA_HU_HU, 9, Y0):
531 case OE_RRR(MULA_HU_LS, 0, X0):
532 case OE_RRR(MULA_HU_LU, 0, X0):
533 case OE_RRR(MULA_LS_LS, 0, X0):
534 case OE_RRR(MULA_LS_LS, 9, Y0):
535 case OE_RRR(MULA_LS_LU, 0, X0):
536 case OE_RRR(MULA_LU_LU, 0, X0):
537 case OE_RRR(MULA_LU_LU, 9, Y0):
538 case OE_RRR(MULX, 0, X0):
539 case OE_RRR(MULX, 3, Y0):
540 case OE_RRR(MUL_HS_HS, 0, X0):
541 case OE_RRR(MUL_HS_HS, 8, Y0):
542 case OE_RRR(MUL_HS_HU, 0, X0):
543 case OE_RRR(MUL_HS_LS, 0, X0):
544 case OE_RRR(MUL_HS_LU, 0, X0):
545 case OE_RRR(MUL_HU_HU, 0, X0):
546 case OE_RRR(MUL_HU_HU, 8, Y0):
547 case OE_RRR(MUL_HU_LS, 0, X0):
548 case OE_RRR(MUL_HU_LU, 0, X0):
549 case OE_RRR(MUL_LS_LS, 0, X0):
550 case OE_RRR(MUL_LS_LS, 8, Y0):
551 case OE_RRR(MUL_LS_LU, 0, X0):
552 case OE_RRR(MUL_LU_LU, 0, X0):
553 case OE_RRR(MUL_LU_LU, 8, Y0):
554 case OE_RRR(MZ, 0, X0):
555 case OE_RRR(MZ, 0, X1):
556 case OE_RRR(MZ, 4, Y0):
557 case OE_RRR(MZ, 4, Y1):
a9fdfc7e 558 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 559 case OE_RRR(NOR, 0, X0):
560 case OE_RRR(NOR, 0, X1):
561 case OE_RRR(NOR, 5, Y0):
562 case OE_RRR(NOR, 5, Y1):
a9fdfc7e
RH		 563 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
564 mnemonic = "nor";
565 break;
8fd29dd7
RH		 566 case OE_RRR(OR, 0, X0):
567 case OE_RRR(OR, 0, X1):
568 case OE_RRR(OR, 5, Y0):
569 case OE_RRR(OR, 5, Y1):
a9fdfc7e
RH		 570 tcg_gen_or_tl(tdest, tsrca, tsrcb);
571 mnemonic = "or";
572 break;
8fd29dd7
RH		 573 case OE_RRR(ROTL, 0, X0):
574 case OE_RRR(ROTL, 0, X1):
575 case OE_RRR(ROTL, 6, Y0):
576 case OE_RRR(ROTL, 6, Y1):
89b8c750 577 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 578 case OE_RRR(SHL1ADDX, 0, X0):
579 case OE_RRR(SHL1ADDX, 0, X1):
580 case OE_RRR(SHL1ADDX, 7, Y0):
581 case OE_RRR(SHL1ADDX, 7, Y1):
89b8c750
RH		 582 tcg_gen_shli_tl(tdest, tsrca, 1);
583 tcg_gen_add_tl(tdest, tdest, tsrcb);
584 tcg_gen_ext32s_tl(tdest, tdest);
585 mnemonic = "shl1addx";
586 break;
8fd29dd7
RH		 587 case OE_RRR(SHL1ADD, 0, X0):
588 case OE_RRR(SHL1ADD, 0, X1):
589 case OE_RRR(SHL1ADD, 1, Y0):
590 case OE_RRR(SHL1ADD, 1, Y1):
89b8c750
RH		 591 tcg_gen_shli_tl(tdest, tsrca, 1);
592 tcg_gen_add_tl(tdest, tdest, tsrcb);
593 mnemonic = "shl1add";
594 break;
8fd29dd7
RH		 595 case OE_RRR(SHL2ADDX, 0, X0):
596 case OE_RRR(SHL2ADDX, 0, X1):
597 case OE_RRR(SHL2ADDX, 7, Y0):
598 case OE_RRR(SHL2ADDX, 7, Y1):
89b8c750
RH		 599 tcg_gen_shli_tl(tdest, tsrca, 2);
600 tcg_gen_add_tl(tdest, tdest, tsrcb);
601 tcg_gen_ext32s_tl(tdest, tdest);
602 mnemonic = "shl2addx";
603 break;
8fd29dd7
RH		 604 case OE_RRR(SHL2ADD, 0, X0):
605 case OE_RRR(SHL2ADD, 0, X1):
606 case OE_RRR(SHL2ADD, 1, Y0):
607 case OE_RRR(SHL2ADD, 1, Y1):
89b8c750
RH		 608 tcg_gen_shli_tl(tdest, tsrca, 2);
609 tcg_gen_add_tl(tdest, tdest, tsrcb);
610 mnemonic = "shl2add";
611 break;
8fd29dd7
RH		 612 case OE_RRR(SHL3ADDX, 0, X0):
613 case OE_RRR(SHL3ADDX, 0, X1):
614 case OE_RRR(SHL3ADDX, 7, Y0):
615 case OE_RRR(SHL3ADDX, 7, Y1):
89b8c750
RH		 616 tcg_gen_shli_tl(tdest, tsrca, 3);
617 tcg_gen_add_tl(tdest, tdest, tsrcb);
618 tcg_gen_ext32s_tl(tdest, tdest);
619 mnemonic = "shl3addx";
620 break;
8fd29dd7
RH		 621 case OE_RRR(SHL3ADD, 0, X0):
622 case OE_RRR(SHL3ADD, 0, X1):
623 case OE_RRR(SHL3ADD, 1, Y0):
624 case OE_RRR(SHL3ADD, 1, Y1):
89b8c750
RH		 625 tcg_gen_shli_tl(tdest, tsrca, 3);
626 tcg_gen_add_tl(tdest, tdest, tsrcb);
627 mnemonic = "shl3add";
628 break;
8fd29dd7
RH		 629 case OE_RRR(SHLX, 0, X0):
630 case OE_RRR(SHLX, 0, X1):
631 case OE_RRR(SHL, 0, X0):
632 case OE_RRR(SHL, 0, X1):
633 case OE_RRR(SHL, 6, Y0):
634 case OE_RRR(SHL, 6, Y1):
635 case OE_RRR(SHRS, 0, X0):
636 case OE_RRR(SHRS, 0, X1):
637 case OE_RRR(SHRS, 6, Y0):
638 case OE_RRR(SHRS, 6, Y1):
639 case OE_RRR(SHRUX, 0, X0):
640 case OE_RRR(SHRUX, 0, X1):
641 case OE_RRR(SHRU, 0, X0):
642 case OE_RRR(SHRU, 0, X1):
643 case OE_RRR(SHRU, 6, Y0):
644 case OE_RRR(SHRU, 6, Y1):
7f41a8d6 645 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 646 case OE_RRR(SHUFFLEBYTES, 0, X0):
7f41a8d6
RH		 647 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
648 mnemonic = "shufflebytes";
649 break;
8fd29dd7
RH		 650 case OE_RRR(SUBXSC, 0, X0):
651 case OE_RRR(SUBXSC, 0, X1):
89b8c750
RH		 652 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
653 mnemonic = "subxsc";
654 break;
8fd29dd7
RH		 655 case OE_RRR(SUBX, 0, X0):
656 case OE_RRR(SUBX, 0, X1):
657 case OE_RRR(SUBX, 0, Y0):
658 case OE_RRR(SUBX, 0, Y1):
89b8c750
RH		 659 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
660 tcg_gen_ext32s_tl(tdest, tdest);
661 mnemonic = "subx";
662 break;
8fd29dd7
RH		 663 case OE_RRR(SUB, 0, X0):
664 case OE_RRR(SUB, 0, X1):
665 case OE_RRR(SUB, 0, Y0):
666 case OE_RRR(SUB, 0, Y1):
89b8c750
RH		 667 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
668 mnemonic = "sub";
669 break;
8fd29dd7
RH		 670 case OE_RRR(V1ADDUC, 0, X0):
671 case OE_RRR(V1ADDUC, 0, X1):
672 case OE_RRR(V1ADD, 0, X0):
673 case OE_RRR(V1ADD, 0, X1):
674 case OE_RRR(V1ADIFFU, 0, X0):
675 case OE_RRR(V1AVGU, 0, X0):
676 case OE_RRR(V1CMPEQ, 0, X0):
677 case OE_RRR(V1CMPEQ, 0, X1):
678 case OE_RRR(V1CMPLES, 0, X0):
679 case OE_RRR(V1CMPLES, 0, X1):
680 case OE_RRR(V1CMPLEU, 0, X0):
681 case OE_RRR(V1CMPLEU, 0, X1):
682 case OE_RRR(V1CMPLTS, 0, X0):
683 case OE_RRR(V1CMPLTS, 0, X1):
684 case OE_RRR(V1CMPLTU, 0, X0):
685 case OE_RRR(V1CMPLTU, 0, X1):
686 case OE_RRR(V1CMPNE, 0, X0):
687 case OE_RRR(V1CMPNE, 0, X1):
688 case OE_RRR(V1DDOTPUA, 0, X0):
689 case OE_RRR(V1DDOTPUSA, 0, X0):
690 case OE_RRR(V1DDOTPUS, 0, X0):
691 case OE_RRR(V1DDOTPU, 0, X0):
692 case OE_RRR(V1DOTPA, 0, X0):
693 case OE_RRR(V1DOTPUA, 0, X0):
694 case OE_RRR(V1DOTPUSA, 0, X0):
695 case OE_RRR(V1DOTPUS, 0, X0):
696 case OE_RRR(V1DOTPU, 0, X0):
697 case OE_RRR(V1DOTP, 0, X0):
698 case OE_RRR(V1INT_H, 0, X0):
699 case OE_RRR(V1INT_H, 0, X1):
700 case OE_RRR(V1INT_L, 0, X0):
701 case OE_RRR(V1INT_L, 0, X1):
702 case OE_RRR(V1MAXU, 0, X0):
703 case OE_RRR(V1MAXU, 0, X1):
704 case OE_RRR(V1MINU, 0, X0):
705 case OE_RRR(V1MINU, 0, X1):
706 case OE_RRR(V1MNZ, 0, X0):
707 case OE_RRR(V1MNZ, 0, X1):
708 case OE_RRR(V1MULTU, 0, X0):
709 case OE_RRR(V1MULUS, 0, X0):
710 case OE_RRR(V1MULU, 0, X0):
711 case OE_RRR(V1MZ, 0, X0):
712 case OE_RRR(V1MZ, 0, X1):
713 case OE_RRR(V1SADAU, 0, X0):
714 case OE_RRR(V1SADU, 0, X0):
715 case OE_RRR(V1SHL, 0, X0):
716 case OE_RRR(V1SHL, 0, X1):
717 case OE_RRR(V1SHRS, 0, X0):
718 case OE_RRR(V1SHRS, 0, X1):
719 case OE_RRR(V1SHRU, 0, X0):
720 case OE_RRR(V1SHRU, 0, X1):
721 case OE_RRR(V1SUBUC, 0, X0):
722 case OE_RRR(V1SUBUC, 0, X1):
723 case OE_RRR(V1SUB, 0, X0):
724 case OE_RRR(V1SUB, 0, X1):
725 case OE_RRR(V2ADDSC, 0, X0):
726 case OE_RRR(V2ADDSC, 0, X1):
727 case OE_RRR(V2ADD, 0, X0):
728 case OE_RRR(V2ADD, 0, X1):
729 case OE_RRR(V2ADIFFS, 0, X0):
730 case OE_RRR(V2AVGS, 0, X0):
731 case OE_RRR(V2CMPEQ, 0, X0):
732 case OE_RRR(V2CMPEQ, 0, X1):
733 case OE_RRR(V2CMPLES, 0, X0):
734 case OE_RRR(V2CMPLES, 0, X1):
735 case OE_RRR(V2CMPLEU, 0, X0):
736 case OE_RRR(V2CMPLEU, 0, X1):
737 case OE_RRR(V2CMPLTS, 0, X0):
738 case OE_RRR(V2CMPLTS, 0, X1):
739 case OE_RRR(V2CMPLTU, 0, X0):
740 case OE_RRR(V2CMPLTU, 0, X1):
741 case OE_RRR(V2CMPNE, 0, X0):
742 case OE_RRR(V2CMPNE, 0, X1):
743 case OE_RRR(V2DOTPA, 0, X0):
744 case OE_RRR(V2DOTP, 0, X0):
745 case OE_RRR(V2INT_H, 0, X0):
746 case OE_RRR(V2INT_H, 0, X1):
747 case OE_RRR(V2INT_L, 0, X0):
748 case OE_RRR(V2INT_L, 0, X1):
749 case OE_RRR(V2MAXS, 0, X0):
750 case OE_RRR(V2MAXS, 0, X1):
751 case OE_RRR(V2MINS, 0, X0):
752 case OE_RRR(V2MINS, 0, X1):
753 case OE_RRR(V2MNZ, 0, X0):
754 case OE_RRR(V2MNZ, 0, X1):
755 case OE_RRR(V2MULFSC, 0, X0):
756 case OE_RRR(V2MULS, 0, X0):
757 case OE_RRR(V2MULTS, 0, X0):
758 case OE_RRR(V2MZ, 0, X0):
759 case OE_RRR(V2MZ, 0, X1):
760 case OE_RRR(V2PACKH, 0, X0):
761 case OE_RRR(V2PACKH, 0, X1):
762 case OE_RRR(V2PACKL, 0, X0):
763 case OE_RRR(V2PACKL, 0, X1):
764 case OE_RRR(V2PACKUC, 0, X0):
765 case OE_RRR(V2PACKUC, 0, X1):
766 case OE_RRR(V2SADAS, 0, X0):
767 case OE_RRR(V2SADAU, 0, X0):
768 case OE_RRR(V2SADS, 0, X0):
769 case OE_RRR(V2SADU, 0, X0):
770 case OE_RRR(V2SHLSC, 0, X0):
771 case OE_RRR(V2SHLSC, 0, X1):
772 case OE_RRR(V2SHL, 0, X0):
773 case OE_RRR(V2SHL, 0, X1):
774 case OE_RRR(V2SHRS, 0, X0):
775 case OE_RRR(V2SHRS, 0, X1):
776 case OE_RRR(V2SHRU, 0, X0):
777 case OE_RRR(V2SHRU, 0, X1):
778 case OE_RRR(V2SUBSC, 0, X0):
779 case OE_RRR(V2SUBSC, 0, X1):
780 case OE_RRR(V2SUB, 0, X0):
781 case OE_RRR(V2SUB, 0, X1):
782 case OE_RRR(V4ADDSC, 0, X0):
783 case OE_RRR(V4ADDSC, 0, X1):
784 case OE_RRR(V4ADD, 0, X0):
785 case OE_RRR(V4ADD, 0, X1):
786 case OE_RRR(V4INT_H, 0, X0):
787 case OE_RRR(V4INT_H, 0, X1):
788 case OE_RRR(V4INT_L, 0, X0):
789 case OE_RRR(V4INT_L, 0, X1):
790 case OE_RRR(V4PACKSC, 0, X0):
791 case OE_RRR(V4PACKSC, 0, X1):
792 case OE_RRR(V4SHLSC, 0, X0):
793 case OE_RRR(V4SHLSC, 0, X1):
794 case OE_RRR(V4SHL, 0, X0):
795 case OE_RRR(V4SHL, 0, X1):
796 case OE_RRR(V4SHRS, 0, X0):
797 case OE_RRR(V4SHRS, 0, X1):
798 case OE_RRR(V4SHRU, 0, X0):
799 case OE_RRR(V4SHRU, 0, X1):
800 case OE_RRR(V4SUBSC, 0, X0):
801 case OE_RRR(V4SUBSC, 0, X1):
802 case OE_RRR(V4SUB, 0, X0):
803 case OE_RRR(V4SUB, 0, X1):
a9fdfc7e 804 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 805 case OE_RRR(XOR, 0, X0):
806 case OE_RRR(XOR, 0, X1):
807 case OE_RRR(XOR, 5, Y0):
808 case OE_RRR(XOR, 5, Y1):
a9fdfc7e
RH		 809 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
810 mnemonic = "xor";
811 break;
8fd29dd7
RH		 812 default:
813 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
814 }
815
816 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
817 reg_names[dest], reg_names[srca], reg_names[srcb]);
818 return TILEGX_EXCP_NONE;
819}
820
821static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
822 unsigned dest, unsigned srca, int imm)
823{
a9fdfc7e
RH		 824 TCGv tdest = dest_gr(dc, dest);
825 TCGv tsrca = load_gr(dc, srca);
8fd29dd7
RH		 826 const char *mnemonic;
827
828 switch (opext) {
89b8c750
RH		 829 case OE(ADDI_OPCODE_Y0, 0, Y0):
830 case OE(ADDI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 831 case OE_IM(ADDI, X0):
832 case OE_IM(ADDI, X1):
89b8c750
RH		 833 tcg_gen_addi_tl(tdest, tsrca, imm);
834 mnemonic = "addi";
835 break;
836 case OE(ADDXI_OPCODE_Y0, 0, Y0):
837 case OE(ADDXI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 838 case OE_IM(ADDXI, X0):
839 case OE_IM(ADDXI, X1):
89b8c750
RH		 840 tcg_gen_addi_tl(tdest, tsrca, imm);
841 tcg_gen_ext32s_tl(tdest, tdest);
842 mnemonic = "addxi";
843 break;
a9fdfc7e
RH		 844 case OE(ANDI_OPCODE_Y0, 0, Y0):
845 case OE(ANDI_OPCODE_Y1, 0, Y1):
8fd29dd7
RH		 846 case OE_IM(ANDI, X0):
847 case OE_IM(ANDI, X1):
a9fdfc7e
RH		 848 tcg_gen_andi_tl(tdest, tsrca, imm);
849 mnemonic = "andi";
850 break;
8fd29dd7
RH		 851 case OE_IM(CMPEQI, X0):
852 case OE_IM(CMPEQI, X1):
853 case OE_IM(CMPLTSI, X0):
854 case OE_IM(CMPLTSI, X1):
855 case OE_IM(CMPLTUI, X0):
856 case OE_IM(CMPLTUI, X1):
857 case OE_IM(LD1S_ADD, X1):
858 case OE_IM(LD1U_ADD, X1):
859 case OE_IM(LD2S_ADD, X1):
860 case OE_IM(LD2U_ADD, X1):
861 case OE_IM(LD4S_ADD, X1):
862 case OE_IM(LD4U_ADD, X1):
863 case OE_IM(LDNT1S_ADD, X1):
864 case OE_IM(LDNT1U_ADD, X1):
865 case OE_IM(LDNT2S_ADD, X1):
866 case OE_IM(LDNT2U_ADD, X1):
867 case OE_IM(LDNT4S_ADD, X1):
868 case OE_IM(LDNT4U_ADD, X1):
869 case OE_IM(LDNT_ADD, X1):
870 case OE_IM(LD_ADD, X1):
871 case OE_IM(LDNA_ADD, X1):
872 case OE_IM(MFSPR, X1):
873 case OE_IM(MTSPR, X1):
a9fdfc7e 874 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 875 case OE_IM(ORI, X0):
876 case OE_IM(ORI, X1):
a9fdfc7e
RH		 877 tcg_gen_ori_tl(tdest, tsrca, imm);
878 mnemonic = "ori";
879 break;
8fd29dd7
RH		 880 case OE_IM(ST1_ADD, X1):
881 case OE_IM(ST2_ADD, X1):
882 case OE_IM(ST4_ADD, X1):
883 case OE_IM(STNT1_ADD, X1):
884 case OE_IM(STNT2_ADD, X1):
885 case OE_IM(STNT4_ADD, X1):
886 case OE_IM(STNT_ADD, X1):
887 case OE_IM(ST_ADD, X1):
888 case OE_IM(V1ADDI, X0):
889 case OE_IM(V1ADDI, X1):
890 case OE_IM(V1CMPEQI, X0):
891 case OE_IM(V1CMPEQI, X1):
892 case OE_IM(V1CMPLTSI, X0):
893 case OE_IM(V1CMPLTSI, X1):
894 case OE_IM(V1CMPLTUI, X0):
895 case OE_IM(V1CMPLTUI, X1):
896 case OE_IM(V1MAXUI, X0):
897 case OE_IM(V1MAXUI, X1):
898 case OE_IM(V1MINUI, X0):
899 case OE_IM(V1MINUI, X1):
900 case OE_IM(V2ADDI, X0):
901 case OE_IM(V2ADDI, X1):
902 case OE_IM(V2CMPEQI, X0):
903 case OE_IM(V2CMPEQI, X1):
904 case OE_IM(V2CMPLTSI, X0):
905 case OE_IM(V2CMPLTSI, X1):
906 case OE_IM(V2CMPLTUI, X0):
907 case OE_IM(V2CMPLTUI, X1):
908 case OE_IM(V2MAXSI, X0):
909 case OE_IM(V2MAXSI, X1):
910 case OE_IM(V2MINSI, X0):
911 case OE_IM(V2MINSI, X1):
a9fdfc7e 912 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 913 case OE_IM(XORI, X0):
914 case OE_IM(XORI, X1):
a9fdfc7e
RH		 915 tcg_gen_xori_tl(tdest, tsrca, imm);
916 mnemonic = "xori";
917 break;
8fd29dd7
RH		 918
919 case OE_SH(ROTLI, X0):
920 case OE_SH(ROTLI, X1):
921 case OE_SH(ROTLI, Y0):
922 case OE_SH(ROTLI, Y1):
923 case OE_SH(SHLI, X0):
924 case OE_SH(SHLI, X1):
925 case OE_SH(SHLI, Y0):
926 case OE_SH(SHLI, Y1):
927 case OE_SH(SHLXI, X0):
928 case OE_SH(SHLXI, X1):
929 case OE_SH(SHRSI, X0):
930 case OE_SH(SHRSI, X1):
931 case OE_SH(SHRSI, Y0):
932 case OE_SH(SHRSI, Y1):
933 case OE_SH(SHRUI, X0):
934 case OE_SH(SHRUI, X1):
935 case OE_SH(SHRUI, Y0):
936 case OE_SH(SHRUI, Y1):
937 case OE_SH(SHRUXI, X0):
938 case OE_SH(SHRUXI, X1):
939 case OE_SH(V1SHLI, X0):
940 case OE_SH(V1SHLI, X1):
941 case OE_SH(V1SHRSI, X0):
942 case OE_SH(V1SHRSI, X1):
943 case OE_SH(V1SHRUI, X0):
944 case OE_SH(V1SHRUI, X1):
945 case OE_SH(V2SHLI, X0):
946 case OE_SH(V2SHLI, X1):
947 case OE_SH(V2SHRSI, X0):
948 case OE_SH(V2SHRSI, X1):
949 case OE_SH(V2SHRUI, X0):
950 case OE_SH(V2SHRUI, X1):
89b8c750 951 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7 952
8fd29dd7
RH		 953 case OE(ADDLI_OPCODE_X0, 0, X0):
954 case OE(ADDLI_OPCODE_X1, 0, X1):
89b8c750
RH		 955 tcg_gen_addi_tl(tdest, tsrca, imm);
956 mnemonic = "addli";
957 break;
8fd29dd7
RH		 958 case OE(ADDXLI_OPCODE_X0, 0, X0):
959 case OE(ADDXLI_OPCODE_X1, 0, X1):
89b8c750
RH		 960 tcg_gen_addi_tl(tdest, tsrca, imm);
961 tcg_gen_ext32s_tl(tdest, tdest);
962 mnemonic = "addxli";
963 break;
8fd29dd7
RH		 964 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
965 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
966 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
967 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
89b8c750 968 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
8fd29dd7
RH		 969 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
970 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
89b8c750
RH		 971 tcg_gen_shli_tl(tdest, tsrca, 16);
972 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
973 mnemonic = "shl16insli";
974 break;
8fd29dd7
RH		 975
976 default:
977 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
978 }
979
980 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
981 reg_names[dest], reg_names[srca], imm);
982 return TILEGX_EXCP_NONE;
983}
984
985static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
986 unsigned dest, unsigned srca,
987 unsigned bfs, unsigned bfe)
988{
989 const char *mnemonic;
990
991 switch (ext) {
992 case BFEXTU_BF_OPCODE_X0:
993 case BFEXTS_BF_OPCODE_X0:
994 case BFINS_BF_OPCODE_X0:
995 case MM_BF_OPCODE_X0:
996 default:
997 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
998 }
999
1000 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
1001 reg_names[dest], reg_names[srca], bfs, bfe);
1002 return TILEGX_EXCP_NONE;
1003}
1004
1005static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
1006 unsigned srca, int off)
1007{
1008 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1009 const char *mnemonic;
1010
1011 switch (ext) {
1012 case BEQZT_BRANCH_OPCODE_X1:
1013 case BEQZ_BRANCH_OPCODE_X1:
1014 case BNEZT_BRANCH_OPCODE_X1:
1015 case BNEZ_BRANCH_OPCODE_X1:
1016 case BLBC_BRANCH_OPCODE_X1:
1017 case BGEZT_BRANCH_OPCODE_X1:
1018 case BGEZ_BRANCH_OPCODE_X1:
1019 case BGTZT_BRANCH_OPCODE_X1:
1020 case BGTZ_BRANCH_OPCODE_X1:
1021 case BLBCT_BRANCH_OPCODE_X1:
1022 case BLBST_BRANCH_OPCODE_X1:
1023 case BLBS_BRANCH_OPCODE_X1:
1024 case BLEZT_BRANCH_OPCODE_X1:
1025 case BLEZ_BRANCH_OPCODE_X1:
1026 case BLTZT_BRANCH_OPCODE_X1:
1027 case BLTZ_BRANCH_OPCODE_X1:
1028 default:
1029 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1030 }
1031
1032 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1033 qemu_log("%s %s, " TARGET_FMT_lx " <%s>",
1034 mnemonic, reg_names[srca], tgt, lookup_symbol(tgt));
1035 }
1036 return TILEGX_EXCP_NONE;
1037}
1038
1039static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext,
1040 int off)
1041{
1042 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1043 const char *mnemonic;
1044
1045 switch (ext) {
1046 case JAL_JUMP_OPCODE_X1:
1047 case J_JUMP_OPCODE_X1:
1048 default:
1049 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1050 }
1051
1052 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1053 qemu_log("%s " TARGET_FMT_lx " <%s>",
1054 mnemonic, tgt, lookup_symbol(tgt));
1055 }
1056 return TILEGX_EXCP_NONE;
1057}
1058
1059static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
1060{
1061 unsigned opc = get_Opcode_Y0(bundle);
1062 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
1063 unsigned dest = get_Dest_Y0(bundle);
1064 unsigned srca = get_SrcA_Y0(bundle);
1065 unsigned srcb;
1066 int imm;
1067
1068 switch (opc) {
1069 case RRR_1_OPCODE_Y0:
1070 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1071 ext = get_UnaryOpcodeExtension_Y0(bundle);
1072 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
1073 }
1074 /* fallthru */
1075 case RRR_0_OPCODE_Y0:
1076 case RRR_2_OPCODE_Y0:
1077 case RRR_3_OPCODE_Y0:
1078 case RRR_4_OPCODE_Y0:
1079 case RRR_5_OPCODE_Y0:
1080 case RRR_6_OPCODE_Y0:
1081 case RRR_7_OPCODE_Y0:
1082 case RRR_8_OPCODE_Y0:
1083 case RRR_9_OPCODE_Y0:
1084 srcb = get_SrcB_Y0(bundle);
1085 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
1086
1087 case SHIFT_OPCODE_Y0:
1088 ext = get_ShiftOpcodeExtension_Y0(bundle);
1089 imm = get_ShAmt_Y0(bundle);
1090 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
1091
1092 case ADDI_OPCODE_Y0:
1093 case ADDXI_OPCODE_Y0:
1094 case ANDI_OPCODE_Y0:
1095 case CMPEQI_OPCODE_Y0:
1096 case CMPLTSI_OPCODE_Y0:
1097 imm = (int8_t)get_Imm8_Y0(bundle);
1098 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
1099
1100 default:
1101 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1102 }
1103}
1104
1105static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
1106{
1107 unsigned opc = get_Opcode_Y1(bundle);
1108 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
1109 unsigned dest = get_Dest_Y1(bundle);
1110 unsigned srca = get_SrcA_Y1(bundle);
1111 unsigned srcb;
1112 int imm;
1113
1114 switch (get_Opcode_Y1(bundle)) {
1115 case RRR_1_OPCODE_Y1:
1116 if (ext == UNARY_RRR_1_OPCODE_Y0) {
1117 ext = get_UnaryOpcodeExtension_Y1(bundle);
1118 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
1119 }
1120 /* fallthru */
1121 case RRR_0_OPCODE_Y1:
1122 case RRR_2_OPCODE_Y1:
1123 case RRR_3_OPCODE_Y1:
1124 case RRR_4_OPCODE_Y1:
1125 case RRR_5_OPCODE_Y1:
1126 case RRR_6_OPCODE_Y1:
1127 case RRR_7_OPCODE_Y1:
1128 srcb = get_SrcB_Y1(bundle);
1129 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
1130
1131 case SHIFT_OPCODE_Y1:
1132 ext = get_ShiftOpcodeExtension_Y1(bundle);
1133 imm = get_ShAmt_Y1(bundle);
1134 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
1135
1136 case ADDI_OPCODE_Y1:
1137 case ADDXI_OPCODE_Y1:
1138 case ANDI_OPCODE_Y1:
1139 case CMPEQI_OPCODE_Y1:
1140 case CMPLTSI_OPCODE_Y1:
1141 imm = (int8_t)get_Imm8_Y1(bundle);
1142 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
1143
1144 default:
1145 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1146 }
1147}
1148
1149static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
1150{
1151 unsigned mode = get_Mode(bundle);
1152 unsigned opc = get_Opcode_Y2(bundle);
1153 unsigned srca = get_SrcA_Y2(bundle);
1154 unsigned srcbdest = get_SrcBDest_Y2(bundle);
1155 const char *mnemonic;
0426335d 1156 TCGMemOp memop;
8fd29dd7
RH		 1157
1158 switch (OEY2(opc, mode)) {
1159 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1160 memop = MO_SB;
1161 mnemonic = "ld1s";
1162 goto do_load;
8fd29dd7 1163 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1164 memop = MO_UB;
1165 mnemonic = "ld1u";
1166 goto do_load;
8fd29dd7 1167 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1168 memop = MO_TESW;
1169 mnemonic = "ld2s";
1170 goto do_load;
8fd29dd7 1171 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
0426335d
RH		 1172 memop = MO_TEUW;
1173 mnemonic = "ld2u";
1174 goto do_load;
8fd29dd7 1175 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
0426335d
RH		 1176 memop = MO_TESL;
1177 mnemonic = "ld4s";
1178 goto do_load;
8fd29dd7 1179 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
0426335d
RH		 1180 memop = MO_TEUL;
1181 mnemonic = "ld4u";
1182 goto do_load;
8fd29dd7 1183 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
0426335d
RH		 1184 memop = MO_TEQ;
1185 mnemonic = "ld";
1186 do_load:
1187 tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
1188 dc->mmuidx, memop);
1189 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
1190 reg_names[srcbdest], reg_names[srca]);
1191 return TILEGX_EXCP_NONE;
8fd29dd7
RH		 1192
1193 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1194 return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
8fd29dd7 1195 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1196 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
8fd29dd7 1197 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1198 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
8fd29dd7 1199 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
0426335d 1200 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
8fd29dd7
RH		 1201
1202 default:
1203 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1204 }
8fd29dd7
RH		 1205}
1206
1207static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
1208{
1209 unsigned opc = get_Opcode_X0(bundle);
1210 unsigned dest = get_Dest_X0(bundle);
1211 unsigned srca = get_SrcA_X0(bundle);
1212 unsigned ext, srcb, bfs, bfe;
1213 int imm;
1214
1215 switch (opc) {
1216 case RRR_0_OPCODE_X0:
1217 ext = get_RRROpcodeExtension_X0(bundle);
1218 if (ext == UNARY_RRR_0_OPCODE_X0) {
1219 ext = get_UnaryOpcodeExtension_X0(bundle);
1220 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
1221 }
1222 srcb = get_SrcB_X0(bundle);
1223 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
1224
1225 case SHIFT_OPCODE_X0:
1226 ext = get_ShiftOpcodeExtension_X0(bundle);
1227 imm = get_ShAmt_X0(bundle);
1228 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1229
1230 case IMM8_OPCODE_X0:
1231 ext = get_Imm8OpcodeExtension_X0(bundle);
1232 imm = (int8_t)get_Imm8_X0(bundle);
1233 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
1234
1235 case BF_OPCODE_X0:
1236 ext = get_BFOpcodeExtension_X0(bundle);
1237 bfs = get_BFStart_X0(bundle);
1238 bfe = get_BFEnd_X0(bundle);
1239 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
1240
1241 case ADDLI_OPCODE_X0:
1242 case SHL16INSLI_OPCODE_X0:
1243 case ADDXLI_OPCODE_X0:
1244 imm = (int16_t)get_Imm16_X0(bundle);
1245 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
1246
1247 default:
1248 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1249 }
1250}
1251
1252static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
1253{
1254 unsigned opc = get_Opcode_X1(bundle);
1255 unsigned dest = get_Dest_X1(bundle);
1256 unsigned srca = get_SrcA_X1(bundle);
1257 unsigned ext, srcb;
1258 int imm;
1259
1260 switch (opc) {
1261 case RRR_0_OPCODE_X1:
1262 ext = get_RRROpcodeExtension_X1(bundle);
0426335d
RH		 1263 srcb = get_SrcB_X1(bundle);
1264 switch (ext) {
1265 case UNARY_RRR_0_OPCODE_X1:
8fd29dd7
RH		 1266 ext = get_UnaryOpcodeExtension_X1(bundle);
1267 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
0426335d
RH		 1268 case ST1_RRR_0_OPCODE_X1:
1269 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
1270 case ST2_RRR_0_OPCODE_X1:
1271 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
1272 case ST4_RRR_0_OPCODE_X1:
1273 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
1274 case STNT1_RRR_0_OPCODE_X1:
1275 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
1276 case STNT2_RRR_0_OPCODE_X1:
1277 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
1278 case STNT4_RRR_0_OPCODE_X1:
1279 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
1280 case STNT_RRR_0_OPCODE_X1:
1281 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
1282 case ST_RRR_0_OPCODE_X1:
1283 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
8fd29dd7 1284 }
8fd29dd7
RH		 1285 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
1286
1287 case SHIFT_OPCODE_X1:
1288 ext = get_ShiftOpcodeExtension_X1(bundle);
1289 imm = get_ShAmt_X1(bundle);
1290 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1291
1292 case IMM8_OPCODE_X1:
1293 ext = get_Imm8OpcodeExtension_X1(bundle);
1294 imm = (int8_t)get_Imm8_X1(bundle);
1295 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
1296
1297 case BRANCH_OPCODE_X1:
1298 ext = get_BrType_X1(bundle);
1299 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
1300 return gen_branch_opcode_x1(dc, ext, srca, imm);
1301
1302 case JUMP_OPCODE_X1:
1303 ext = get_JumpOpcodeExtension_X1(bundle);
1304 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
1305 return gen_jump_opcode_x1(dc, ext, imm);
1306
1307 case ADDLI_OPCODE_X1:
1308 case SHL16INSLI_OPCODE_X1:
1309 case ADDXLI_OPCODE_X1:
1310 imm = (int16_t)get_Imm16_X1(bundle);
1311 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
1312
1313 default:
1314 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1315 }
1316}
1317
1318static void notice_excp(DisasContext *dc, uint64_t bundle,
1319 const char *type, TileExcp excp)
1320{
1321 if (likely(excp == TILEGX_EXCP_NONE)) {
1322 return;
1323 }
1324 gen_exception(dc, excp);
1325 if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
1326 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
1327 }
1328}
1329
1330static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
1331{
1332 int i;
1333
1334 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
1335 DisasContextTemp *wb = &dc->wb[i];
1336 wb->reg = TILEGX_R_NOREG;
1337 TCGV_UNUSED_I64(wb->val);
1338 }
1339 dc->num_wb = 0;
1340
1341 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1342 tcg_gen_debug_insn_start(dc->pc);
1343 }
1344
1345 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
1346 if (get_Mode(bundle)) {
1347 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
1348 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1349 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
1350 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1351 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
1352 } else {
1353 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
1354 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
1355 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
1356 }
1357 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
1358
1359 for (i = dc->num_wb - 1; i >= 0; --i) {
1360 DisasContextTemp *wb = &dc->wb[i];
1361 if (wb->reg < TILEGX_R_COUNT) {
1362 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
1363 }
1364 tcg_temp_free_i64(wb->val);
1365 }
1366
1367 if (dc->jmp.cond != TCG_COND_NEVER) {
1368 if (dc->jmp.cond == TCG_COND_ALWAYS) {
1369 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
1370 } else {
1371 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1372 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
1373 dc->jmp.val1, load_zero(dc),
1374 dc->jmp.dest, next);
1375 tcg_temp_free_i64(dc->jmp.val1);
1376 tcg_temp_free_i64(next);
1377 }
1378 tcg_temp_free_i64(dc->jmp.dest);
1379 tcg_gen_exit_tb(0);
1380 dc->exit_tb = true;
1381 }
1382}
1383
1384static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
1385 TranslationBlock *tb,
1386 bool search_pc)
1387{
1388 DisasContext ctx;
1389 DisasContext *dc = &ctx;
1390 CPUState *cs = CPU(cpu);
1391 CPUTLGState *env = &cpu->env;
1392 uint64_t pc_start = tb->pc;
1393 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1394 int j, lj = -1;
1395 int num_insns = 0;
1396 int max_insns = tb->cflags & CF_COUNT_MASK;
1397
1398 dc->pc = pc_start;
1399 dc->mmuidx = 0;
1400 dc->exit_tb = false;
1401 dc->jmp.cond = TCG_COND_NEVER;
1402 TCGV_UNUSED_I64(dc->jmp.dest);
1403 TCGV_UNUSED_I64(dc->jmp.val1);
8fd29dd7
RH		 1404 TCGV_UNUSED_I64(dc->zero);
1405
1406 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1407 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1408 }
1409 if (!max_insns) {
1410 max_insns = CF_COUNT_MASK;
1411 }
1412 if (cs->singlestep_enabled || singlestep) {
1413 max_insns = 1;
1414 }
1415 gen_tb_start(tb);
1416
1417 while (1) {
1418 if (search_pc) {
1419 j = tcg_op_buf_count();
1420 if (lj < j) {
1421 lj++;
1422 while (lj < j) {
1423 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1424 }
1425 }
1426 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1427 tcg_ctx.gen_opc_instr_start[lj] = 1;
1428 tcg_ctx.gen_opc_icount[lj] = num_insns;
1429 }
1430 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
1431
1432 if (dc->exit_tb) {
1433 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
1434 break;
1435 }
1436 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
1437 if (++num_insns >= max_insns
1438 || dc->pc >= next_page_start
1439 || tcg_op_buf_full()) {
1440 /* Ending the TB due to TB size or page boundary. Set PC. */
1441 tcg_gen_movi_tl(cpu_pc, dc->pc);
1442 tcg_gen_exit_tb(0);
1443 break;
1444 }
1445 }
1446
1447 gen_tb_end(tb, num_insns);
1448 if (search_pc) {
1449 j = tcg_op_buf_count();
1450 lj++;
1451 while (lj <= j) {
1452 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1453 }
1454 } else {
1455 tb->size = dc->pc - pc_start;
1456 tb->icount = num_insns;
1457 }
1458
1459 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1460}
1461
1462void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
1463{
1464 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
1465}
1466
1467void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
1468{
1469 gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
1470}
1471
1472void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
1473{
1474 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1475}
1476
1477void tilegx_tcg_init(void)
1478{
1479 int i;
1480
1481 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1482 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
1483 for (i = 0; i < TILEGX_R_COUNT; i++) {
1484 cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
1485 offsetof(CPUTLGState, regs[i]),
1486 reg_names[i]);
1487 }
1488}
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