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[qemu.git] / target / tricore / helper.c
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1/*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
61d9f32b 18#include "qemu/osdep.h"
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19
20#include "cpu.h"
63c91552 21#include "exec/exec-all.h"
24f91e81 22#include "fpu/softfloat.h"
48e06fe0 23
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24enum {
25 TLBRET_DIRTY = -4,
26 TLBRET_INVALID = -3,
27 TLBRET_NOMATCH = -2,
28 TLBRET_BADADDR = -1,
29 TLBRET_MATCH = 0
30};
31
32#if defined(CONFIG_SOFTMMU)
33static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
34 int *prot, target_ulong address,
35 int rw, int access_type)
36{
37 int ret = TLBRET_MATCH;
38
39 *physical = address & 0xFFFFFFFF;
40 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
41
42 return ret;
43}
44#endif
45
46/* TODO: Add exeption support*/
47static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
48 int rw, int tlb_error)
49{
50}
51
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52int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
53 int rw, int mmu_idx)
54{
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55 TriCoreCPU *cpu = TRICORE_CPU(cs);
56 CPUTriCoreState *env = &cpu->env;
57 hwaddr physical;
58 int prot;
59 int access_type;
60 int ret = 0;
61
62 rw &= 1;
63 access_type = ACCESS_INT;
64 ret = get_physical_address(env, &physical, &prot,
65 address, rw, access_type);
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66 qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
67 " prot %d\n", __func__, address, ret, physical, prot);
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68
69 if (ret == TLBRET_MATCH) {
70 tlb_set_page(cs, address & TARGET_PAGE_MASK,
71 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
72 mmu_idx, TARGET_PAGE_SIZE);
73 ret = 0;
74 } else if (ret < 0) {
75 raise_mmu_exception(env, address, rw, ret);
76 ret = 1;
77 }
78
79 return ret;
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80}
81
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82static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
83{
84 ObjectClass *oc = data;
85 CPUListState *s = user_data;
86 const char *typename;
87 char *name;
88
89 typename = object_class_get_name(oc);
90 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
91 (*s->cpu_fprintf)(s->file, " %s\n",
92 name);
93 g_free(name);
94}
95
96void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
97{
98 CPUListState s = {
99 .file = f,
100 .cpu_fprintf = cpu_fprintf,
101 };
102 GSList *list;
103
47c66009 104 list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false);
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105 (*cpu_fprintf)(f, "Available CPUs:\n");
106 g_slist_foreach(list, tricore_cpu_list_entry, &s);
107 g_slist_free(list);
108}
109
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110void fpu_set_state(CPUTriCoreState *env)
111{
112 set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
113 set_flush_inputs_to_zero(1, &env->fp_status);
114 set_flush_to_zero(1, &env->fp_status);
115 set_default_nan_mode(1, &env->fp_status);
116}
117
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118uint32_t psw_read(CPUTriCoreState *env)
119{
120 /* clear all USB bits */
1bd3e2fc 121 env->PSW &= 0x6ffffff;
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122 /* now set them from the cache */
123 env->PSW |= ((env->PSW_USB_C != 0) << 31);
124 env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
125 env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2);
126 env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3);
127 env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4);
128
129 return env->PSW;
130}
131
132void psw_write(CPUTriCoreState *env, uint32_t val)
133{
134 env->PSW_USB_C = (val & MASK_USB_C);
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135 env->PSW_USB_V = (val & MASK_USB_V) << 1;
136 env->PSW_USB_SV = (val & MASK_USB_SV) << 2;
137 env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
138 env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
48e06fe0 139 env->PSW = val;
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140
141 fpu_set_state(env);
48e06fe0 142}
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