[qemu.git] / target / riscv / instmap.h

/*
 * RISC-V emulation for qemu: Instruction decode helpers
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef TARGET_RISCV_INSTMAP_H
#define TARGET_RISCV_INSTMAP_H

#define MASK_OP_MAJOR(op)  (op & 0x7F)
enum {
    /* rv32i, rv64i, rv32m */
    OPC_RISC_LUI    = (0x37),
    OPC_RISC_AUIPC  = (0x17),
    OPC_RISC_JAL    = (0x6F),
    OPC_RISC_JALR   = (0x67),
    OPC_RISC_BRANCH = (0x63),
    OPC_RISC_LOAD   = (0x03),
    OPC_RISC_STORE  = (0x23),
    OPC_RISC_ARITH_IMM  = (0x13),
    OPC_RISC_ARITH      = (0x33),
    OPC_RISC_FENCE      = (0x0F),
    OPC_RISC_SYSTEM     = (0x73),

    /* rv64i, rv64m */
    OPC_RISC_ARITH_IMM_W = (0x1B),
    OPC_RISC_ARITH_W = (0x3B),

    /* rv32a, rv64a */
    OPC_RISC_ATOMIC = (0x2F),

    /* floating point */
    OPC_RISC_FP_LOAD = (0x7),
    OPC_RISC_FP_STORE = (0x27),

    OPC_RISC_FMADD = (0x43),
    OPC_RISC_FMSUB = (0x47),
    OPC_RISC_FNMSUB = (0x4B),
    OPC_RISC_FNMADD = (0x4F),

    OPC_RISC_FP_ARITH = (0x53),
};

#define MASK_OP_ARITH(op)   (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \
                            (0x7F << 25))))
enum {
    OPC_RISC_ADD   = OPC_RISC_ARITH | (0x0 << 12) | (0x00 << 25),
    OPC_RISC_SUB   = OPC_RISC_ARITH | (0x0 << 12) | (0x20 << 25),
    OPC_RISC_SLL   = OPC_RISC_ARITH | (0x1 << 12) | (0x00 << 25),
    OPC_RISC_SLT   = OPC_RISC_ARITH | (0x2 << 12) | (0x00 << 25),
    OPC_RISC_SLTU  = OPC_RISC_ARITH | (0x3 << 12) | (0x00 << 25),
    OPC_RISC_XOR   = OPC_RISC_ARITH | (0x4 << 12) | (0x00 << 25),
    OPC_RISC_SRL   = OPC_RISC_ARITH | (0x5 << 12) | (0x00 << 25),
    OPC_RISC_SRA   = OPC_RISC_ARITH | (0x5 << 12) | (0x20 << 25),
    OPC_RISC_OR    = OPC_RISC_ARITH | (0x6 << 12) | (0x00 << 25),
    OPC_RISC_AND   = OPC_RISC_ARITH | (0x7 << 12) | (0x00 << 25),

    /* RV64M */
    OPC_RISC_MUL    = OPC_RISC_ARITH | (0x0 << 12) | (0x01 << 25),
    OPC_RISC_MULH   = OPC_RISC_ARITH | (0x1 << 12) | (0x01 << 25),
    OPC_RISC_MULHSU = OPC_RISC_ARITH | (0x2 << 12) | (0x01 << 25),
    OPC_RISC_MULHU  = OPC_RISC_ARITH | (0x3 << 12) | (0x01 << 25),

    OPC_RISC_DIV    = OPC_RISC_ARITH | (0x4 << 12) | (0x01 << 25),
    OPC_RISC_DIVU   = OPC_RISC_ARITH | (0x5 << 12) | (0x01 << 25),
    OPC_RISC_REM    = OPC_RISC_ARITH | (0x6 << 12) | (0x01 << 25),
    OPC_RISC_REMU   = OPC_RISC_ARITH | (0x7 << 12) | (0x01 << 25),
};


#define MASK_OP_ARITH_IMM(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_ADDI   = OPC_RISC_ARITH_IMM | (0x0 << 12),
    OPC_RISC_SLTI   = OPC_RISC_ARITH_IMM | (0x2 << 12),
    OPC_RISC_SLTIU  = OPC_RISC_ARITH_IMM | (0x3 << 12),
    OPC_RISC_XORI   = OPC_RISC_ARITH_IMM | (0x4 << 12),
    OPC_RISC_ORI    = OPC_RISC_ARITH_IMM | (0x6 << 12),
    OPC_RISC_ANDI   = OPC_RISC_ARITH_IMM | (0x7 << 12),
    OPC_RISC_SLLI   = OPC_RISC_ARITH_IMM | (0x1 << 12), /* additional part of
                                                           IMM */
    OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM | (0x5 << 12) /* SRAI, SRLI */
};

#define MASK_OP_BRANCH(op)     (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_BEQ  = OPC_RISC_BRANCH  | (0x0  << 12),
    OPC_RISC_BNE  = OPC_RISC_BRANCH  | (0x1  << 12),
    OPC_RISC_BLT  = OPC_RISC_BRANCH  | (0x4  << 12),
    OPC_RISC_BGE  = OPC_RISC_BRANCH  | (0x5  << 12),
    OPC_RISC_BLTU = OPC_RISC_BRANCH  | (0x6  << 12),
    OPC_RISC_BGEU = OPC_RISC_BRANCH  | (0x7  << 12)
};

enum {
    OPC_RISC_ADDIW   = OPC_RISC_ARITH_IMM_W | (0x0 << 12),
    OPC_RISC_SLLIW   = OPC_RISC_ARITH_IMM_W | (0x1 << 12), /* additional part of
                                                              IMM */
    OPC_RISC_SHIFT_RIGHT_IW = OPC_RISC_ARITH_IMM_W | (0x5 << 12) /* SRAI, SRLI
                                                                  */
};

enum {
    OPC_RISC_ADDW   = OPC_RISC_ARITH_W | (0x0 << 12) | (0x00 << 25),
    OPC_RISC_SUBW   = OPC_RISC_ARITH_W | (0x0 << 12) | (0x20 << 25),
    OPC_RISC_SLLW   = OPC_RISC_ARITH_W | (0x1 << 12) | (0x00 << 25),
    OPC_RISC_SRLW   = OPC_RISC_ARITH_W | (0x5 << 12) | (0x00 << 25),
    OPC_RISC_SRAW   = OPC_RISC_ARITH_W | (0x5 << 12) | (0x20 << 25),

    /* RV64M */
    OPC_RISC_MULW   = OPC_RISC_ARITH_W | (0x0 << 12) | (0x01 << 25),
    OPC_RISC_DIVW   = OPC_RISC_ARITH_W | (0x4 << 12) | (0x01 << 25),
    OPC_RISC_DIVUW  = OPC_RISC_ARITH_W | (0x5 << 12) | (0x01 << 25),
    OPC_RISC_REMW   = OPC_RISC_ARITH_W | (0x6 << 12) | (0x01 << 25),
    OPC_RISC_REMUW  = OPC_RISC_ARITH_W | (0x7 << 12) | (0x01 << 25),
};

#define MASK_OP_LOAD(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_LB   = OPC_RISC_LOAD | (0x0 << 12),
    OPC_RISC_LH   = OPC_RISC_LOAD | (0x1 << 12),
    OPC_RISC_LW   = OPC_RISC_LOAD | (0x2 << 12),
    OPC_RISC_LD   = OPC_RISC_LOAD | (0x3 << 12),
    OPC_RISC_LBU  = OPC_RISC_LOAD | (0x4 << 12),
    OPC_RISC_LHU  = OPC_RISC_LOAD | (0x5 << 12),
    OPC_RISC_LWU  = OPC_RISC_LOAD | (0x6 << 12),
};

#define MASK_OP_STORE(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_SB   = OPC_RISC_STORE | (0x0 << 12),
    OPC_RISC_SH   = OPC_RISC_STORE | (0x1 << 12),
    OPC_RISC_SW   = OPC_RISC_STORE | (0x2 << 12),
    OPC_RISC_SD   = OPC_RISC_STORE | (0x3 << 12),
};

#define MASK_OP_JALR(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
/* no enum since OPC_RISC_JALR is the actual value */

#define MASK_OP_ATOMIC(op) \
    (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | (0x7F << 25))))
#define MASK_OP_ATOMIC_NO_AQ_RL_SZ(op) \
    (MASK_OP_MAJOR(op) | (op & (0x1F << 27)))

enum {
    OPC_RISC_LR          = OPC_RISC_ATOMIC | (0x02 << 27),
    OPC_RISC_SC          = OPC_RISC_ATOMIC | (0x03 << 27),
    OPC_RISC_AMOSWAP     = OPC_RISC_ATOMIC | (0x01 << 27),
    OPC_RISC_AMOADD      = OPC_RISC_ATOMIC | (0x00 << 27),
    OPC_RISC_AMOXOR      = OPC_RISC_ATOMIC | (0x04 << 27),
    OPC_RISC_AMOAND      = OPC_RISC_ATOMIC | (0x0C << 27),
    OPC_RISC_AMOOR       = OPC_RISC_ATOMIC | (0x08 << 27),
    OPC_RISC_AMOMIN      = OPC_RISC_ATOMIC | (0x10 << 27),
    OPC_RISC_AMOMAX      = OPC_RISC_ATOMIC | (0x14 << 27),
    OPC_RISC_AMOMINU     = OPC_RISC_ATOMIC | (0x18 << 27),
    OPC_RISC_AMOMAXU     = OPC_RISC_ATOMIC | (0x1C << 27),
};

#define MASK_OP_SYSTEM(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_ECALL       = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_EBREAK      = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_ERET        = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_MRTS        = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_MRTH        = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_HRTS        = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_WFI         = OPC_RISC_SYSTEM | (0x0 << 12),
    OPC_RISC_SFENCEVM    = OPC_RISC_SYSTEM | (0x0 << 12),

    OPC_RISC_CSRRW       = OPC_RISC_SYSTEM | (0x1 << 12),
    OPC_RISC_CSRRS       = OPC_RISC_SYSTEM | (0x2 << 12),
    OPC_RISC_CSRRC       = OPC_RISC_SYSTEM | (0x3 << 12),
    OPC_RISC_CSRRWI      = OPC_RISC_SYSTEM | (0x5 << 12),
    OPC_RISC_CSRRSI      = OPC_RISC_SYSTEM | (0x6 << 12),
    OPC_RISC_CSRRCI      = OPC_RISC_SYSTEM | (0x7 << 12),
};

#define MASK_OP_FP_LOAD(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_FLW   = OPC_RISC_FP_LOAD | (0x2 << 12),
    OPC_RISC_FLD   = OPC_RISC_FP_LOAD | (0x3 << 12),
};

#define MASK_OP_FP_STORE(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
enum {
    OPC_RISC_FSW   = OPC_RISC_FP_STORE | (0x2 << 12),
    OPC_RISC_FSD   = OPC_RISC_FP_STORE | (0x3 << 12),
};

#define MASK_OP_FP_FMADD(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
    OPC_RISC_FMADD_S = OPC_RISC_FMADD | (0x0 << 25),
    OPC_RISC_FMADD_D = OPC_RISC_FMADD | (0x1 << 25),
};

#define MASK_OP_FP_FMSUB(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
    OPC_RISC_FMSUB_S = OPC_RISC_FMSUB | (0x0 << 25),
    OPC_RISC_FMSUB_D = OPC_RISC_FMSUB | (0x1 << 25),
};

#define MASK_OP_FP_FNMADD(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
    OPC_RISC_FNMADD_S = OPC_RISC_FNMADD | (0x0 << 25),
    OPC_RISC_FNMADD_D = OPC_RISC_FNMADD | (0x1 << 25),
};

#define MASK_OP_FP_FNMSUB(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
enum {
    OPC_RISC_FNMSUB_S = OPC_RISC_FNMSUB | (0x0 << 25),
    OPC_RISC_FNMSUB_D = OPC_RISC_FNMSUB | (0x1 << 25),
};

#define MASK_OP_FP_ARITH(op)   (MASK_OP_MAJOR(op) | (op & (0x7F << 25)))
enum {
    /* float */
    OPC_RISC_FADD_S    = OPC_RISC_FP_ARITH | (0x0 << 25),
    OPC_RISC_FSUB_S    = OPC_RISC_FP_ARITH | (0x4 << 25),
    OPC_RISC_FMUL_S    = OPC_RISC_FP_ARITH | (0x8 << 25),
    OPC_RISC_FDIV_S    = OPC_RISC_FP_ARITH | (0xC << 25),

    OPC_RISC_FSGNJ_S   = OPC_RISC_FP_ARITH | (0x10 << 25),
    OPC_RISC_FSGNJN_S  = OPC_RISC_FP_ARITH | (0x10 << 25),
    OPC_RISC_FSGNJX_S  = OPC_RISC_FP_ARITH | (0x10 << 25),

    OPC_RISC_FMIN_S    = OPC_RISC_FP_ARITH | (0x14 << 25),
    OPC_RISC_FMAX_S    = OPC_RISC_FP_ARITH | (0x14 << 25),

    OPC_RISC_FSQRT_S   = OPC_RISC_FP_ARITH | (0x2C << 25),

    OPC_RISC_FEQ_S     = OPC_RISC_FP_ARITH | (0x50 << 25),
    OPC_RISC_FLT_S     = OPC_RISC_FP_ARITH | (0x50 << 25),
    OPC_RISC_FLE_S     = OPC_RISC_FP_ARITH | (0x50 << 25),

    OPC_RISC_FCVT_W_S  = OPC_RISC_FP_ARITH | (0x60 << 25),
    OPC_RISC_FCVT_WU_S = OPC_RISC_FP_ARITH | (0x60 << 25),
    OPC_RISC_FCVT_L_S  = OPC_RISC_FP_ARITH | (0x60 << 25),
    OPC_RISC_FCVT_LU_S = OPC_RISC_FP_ARITH | (0x60 << 25),

    OPC_RISC_FCVT_S_W  = OPC_RISC_FP_ARITH | (0x68 << 25),
    OPC_RISC_FCVT_S_WU = OPC_RISC_FP_ARITH | (0x68 << 25),
    OPC_RISC_FCVT_S_L  = OPC_RISC_FP_ARITH | (0x68 << 25),
    OPC_RISC_FCVT_S_LU = OPC_RISC_FP_ARITH | (0x68 << 25),

    OPC_RISC_FMV_X_S   = OPC_RISC_FP_ARITH | (0x70 << 25),
    OPC_RISC_FCLASS_S  = OPC_RISC_FP_ARITH | (0x70 << 25),

    OPC_RISC_FMV_S_X   = OPC_RISC_FP_ARITH | (0x78 << 25),

    /* double */
    OPC_RISC_FADD_D    = OPC_RISC_FP_ARITH | (0x1 << 25),
    OPC_RISC_FSUB_D    = OPC_RISC_FP_ARITH | (0x5 << 25),
    OPC_RISC_FMUL_D    = OPC_RISC_FP_ARITH | (0x9 << 25),
    OPC_RISC_FDIV_D    = OPC_RISC_FP_ARITH | (0xD << 25),

    OPC_RISC_FSGNJ_D   = OPC_RISC_FP_ARITH | (0x11 << 25),
    OPC_RISC_FSGNJN_D  = OPC_RISC_FP_ARITH | (0x11 << 25),
    OPC_RISC_FSGNJX_D  = OPC_RISC_FP_ARITH | (0x11 << 25),

    OPC_RISC_FMIN_D    = OPC_RISC_FP_ARITH | (0x15 << 25),
    OPC_RISC_FMAX_D    = OPC_RISC_FP_ARITH | (0x15 << 25),

    OPC_RISC_FCVT_S_D = OPC_RISC_FP_ARITH | (0x20 << 25),

    OPC_RISC_FCVT_D_S = OPC_RISC_FP_ARITH | (0x21 << 25),

    OPC_RISC_FSQRT_D   = OPC_RISC_FP_ARITH | (0x2D << 25),

    OPC_RISC_FEQ_D     = OPC_RISC_FP_ARITH | (0x51 << 25),
    OPC_RISC_FLT_D     = OPC_RISC_FP_ARITH | (0x51 << 25),
    OPC_RISC_FLE_D     = OPC_RISC_FP_ARITH | (0x51 << 25),

    OPC_RISC_FCVT_W_D  = OPC_RISC_FP_ARITH | (0x61 << 25),
    OPC_RISC_FCVT_WU_D = OPC_RISC_FP_ARITH | (0x61 << 25),
    OPC_RISC_FCVT_L_D  = OPC_RISC_FP_ARITH | (0x61 << 25),
    OPC_RISC_FCVT_LU_D = OPC_RISC_FP_ARITH | (0x61 << 25),

    OPC_RISC_FCVT_D_W  = OPC_RISC_FP_ARITH | (0x69 << 25),
    OPC_RISC_FCVT_D_WU = OPC_RISC_FP_ARITH | (0x69 << 25),
    OPC_RISC_FCVT_D_L  = OPC_RISC_FP_ARITH | (0x69 << 25),
    OPC_RISC_FCVT_D_LU = OPC_RISC_FP_ARITH | (0x69 << 25),

    OPC_RISC_FMV_X_D   = OPC_RISC_FP_ARITH | (0x71 << 25),
    OPC_RISC_FCLASS_D  = OPC_RISC_FP_ARITH | (0x71 << 25),

    OPC_RISC_FMV_D_X   = OPC_RISC_FP_ARITH | (0x79 << 25),
};

#define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
                         | (extract32(inst, 25, 6) << 5) \
                         | (extract32(inst, 7, 1) << 11) \
                         | (sextract64(inst, 31, 1) << 12))

#define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
                             | (sextract64(inst, 25, 7) << 5))

#define GET_JAL_IMM(inst) ((extract32(inst, 21, 10) << 1) \
                           | (extract32(inst, 20, 1) << 11) \
                           | (extract32(inst, 12, 8) << 12) \
                           | (sextract64(inst, 31, 1) << 20))

#define GET_RM(inst)   extract32(inst, 12, 3)
#define GET_RS3(inst)  extract32(inst, 27, 5)
#define GET_RS1(inst)  extract32(inst, 15, 5)
#define GET_RS2(inst)  extract32(inst, 20, 5)
#define GET_RD(inst)   extract32(inst, 7, 5)
#define GET_IMM(inst)  sextract64(inst, 20, 12)

/* RVC decoding macros */
#define GET_C_IMM(inst)             (extract32(inst, 2, 5) \
                                    | (sextract64(inst, 12, 1) << 5))
#define GET_C_ZIMM(inst)            (extract32(inst, 2, 5) \
                                    | (extract32(inst, 12, 1) << 5))
#define GET_C_ADDI4SPN_IMM(inst)    ((extract32(inst, 6, 1) << 2) \
                                    | (extract32(inst, 5, 1) << 3) \
                                    | (extract32(inst, 11, 2) << 4) \
                                    | (extract32(inst, 7, 4) << 6))
#define GET_C_ADDI16SP_IMM(inst)    ((extract32(inst, 6, 1) << 4) \
                                    | (extract32(inst, 2, 1) << 5) \
                                    | (extract32(inst, 5, 1) << 6) \
                                    | (extract32(inst, 3, 2) << 7) \
                                    | (sextract64(inst, 12, 1) << 9))
#define GET_C_LWSP_IMM(inst)        ((extract32(inst, 4, 3) << 2) \
                                    | (extract32(inst, 12, 1) << 5) \
                                    | (extract32(inst, 2, 2) << 6))
#define GET_C_LDSP_IMM(inst)        ((extract32(inst, 5, 2) << 3) \
                                    | (extract32(inst, 12, 1) << 5) \
                                    | (extract32(inst, 2, 3) << 6))
#define GET_C_SWSP_IMM(inst)        ((extract32(inst, 9, 4) << 2) \
                                    | (extract32(inst, 7, 2) << 6))
#define GET_C_SDSP_IMM(inst)        ((extract32(inst, 10, 3) << 3) \
                                    | (extract32(inst, 7, 3) << 6))
#define GET_C_LW_IMM(inst)          ((extract32(inst, 6, 1) << 2) \
                                    | (extract32(inst, 10, 3) << 3) \
                                    | (extract32(inst, 5, 1) << 6))
#define GET_C_LD_IMM(inst)          ((extract16(inst, 10, 3) << 3) \
                                    | (extract16(inst, 5, 2) << 6))
#define GET_C_J_IMM(inst)           ((extract32(inst, 3, 3) << 1) \
                                    | (extract32(inst, 11, 1) << 4) \
                                    | (extract32(inst, 2, 1) << 5) \
                                    | (extract32(inst, 7, 1) << 6) \
                                    | (extract32(inst, 6, 1) << 7) \
                                    | (extract32(inst, 9, 2) << 8) \
                                    | (extract32(inst, 8, 1) << 10) \
                                    | (sextract64(inst, 12, 1) << 11))
#define GET_C_B_IMM(inst)           ((extract32(inst, 3, 2) << 1) \
                                    | (extract32(inst, 10, 2) << 3) \
                                    | (extract32(inst, 2, 1) << 5) \
                                    | (extract32(inst, 5, 2) << 6) \
                                    | (sextract64(inst, 12, 1) << 8))
#define GET_C_SIMM3(inst)           extract32(inst, 10, 3)
#define GET_C_RD(inst)              GET_RD(inst)
#define GET_C_RS1(inst)             GET_RD(inst)
#define GET_C_RS2(inst)             extract32(inst, 2, 5)
#define GET_C_RS1S(inst)            (8 + extract16(inst, 7, 3))
#define GET_C_RS2S(inst)            (8 + extract16(inst, 2, 3))

#endif
Commit	Line	Data
55c2a12c MC	1	/*
	2	* RISC-V emulation for qemu: Instruction decode helpers
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
f91005e1 MA	19	#ifndef TARGET_RISCV_INSTMAP_H
	20	#define TARGET_RISCV_INSTMAP_H
	21
55c2a12c MC	22	#define MASK_OP_MAJOR(op) (op & 0x7F)
	23	enum {
	24	/* rv32i, rv64i, rv32m */
	25	OPC_RISC_LUI = (0x37),
	26	OPC_RISC_AUIPC = (0x17),
	27	OPC_RISC_JAL = (0x6F),
	28	OPC_RISC_JALR = (0x67),
	29	OPC_RISC_BRANCH = (0x63),
	30	OPC_RISC_LOAD = (0x03),
	31	OPC_RISC_STORE = (0x23),
	32	OPC_RISC_ARITH_IMM = (0x13),
	33	OPC_RISC_ARITH = (0x33),
	34	OPC_RISC_FENCE = (0x0F),
	35	OPC_RISC_SYSTEM = (0x73),
	36
	37	/* rv64i, rv64m */
	38	OPC_RISC_ARITH_IMM_W = (0x1B),
	39	OPC_RISC_ARITH_W = (0x3B),
	40
	41	/* rv32a, rv64a */
	42	OPC_RISC_ATOMIC = (0x2F),
	43
	44	/* floating point */
	45	OPC_RISC_FP_LOAD = (0x7),
	46	OPC_RISC_FP_STORE = (0x27),
	47
	48	OPC_RISC_FMADD = (0x43),
	49	OPC_RISC_FMSUB = (0x47),
	50	OPC_RISC_FNMSUB = (0x4B),
	51	OPC_RISC_FNMADD = (0x4F),
	52
	53	OPC_RISC_FP_ARITH = (0x53),
	54	};
	55
	56	#define MASK_OP_ARITH(op) (MASK_OP_MAJOR(op) \| (op & ((0x7 << 12) \| \
	57	(0x7F << 25))))
	58	enum {
	59	OPC_RISC_ADD = OPC_RISC_ARITH \| (0x0 << 12) \| (0x00 << 25),
	60	OPC_RISC_SUB = OPC_RISC_ARITH \| (0x0 << 12) \| (0x20 << 25),
	61	OPC_RISC_SLL = OPC_RISC_ARITH \| (0x1 << 12) \| (0x00 << 25),
	62	OPC_RISC_SLT = OPC_RISC_ARITH \| (0x2 << 12) \| (0x00 << 25),
	63	OPC_RISC_SLTU = OPC_RISC_ARITH \| (0x3 << 12) \| (0x00 << 25),
	64	OPC_RISC_XOR = OPC_RISC_ARITH \| (0x4 << 12) \| (0x00 << 25),
	65	OPC_RISC_SRL = OPC_RISC_ARITH \| (0x5 << 12) \| (0x00 << 25),
	66	OPC_RISC_SRA = OPC_RISC_ARITH \| (0x5 << 12) \| (0x20 << 25),
	67	OPC_RISC_OR = OPC_RISC_ARITH \| (0x6 << 12) \| (0x00 << 25),
	68	OPC_RISC_AND = OPC_RISC_ARITH \| (0x7 << 12) \| (0x00 << 25),
	69
	70	/* RV64M */
	71	OPC_RISC_MUL = OPC_RISC_ARITH \| (0x0 << 12) \| (0x01 << 25),
	72	OPC_RISC_MULH = OPC_RISC_ARITH \| (0x1 << 12) \| (0x01 << 25),
	73	OPC_RISC_MULHSU = OPC_RISC_ARITH \| (0x2 << 12) \| (0x01 << 25),
	74	OPC_RISC_MULHU = OPC_RISC_ARITH \| (0x3 << 12) \| (0x01 << 25),
	75
	76	OPC_RISC_DIV = OPC_RISC_ARITH \| (0x4 << 12) \| (0x01 << 25),
	77	OPC_RISC_DIVU = OPC_RISC_ARITH \| (0x5 << 12) \| (0x01 << 25),
	78	OPC_RISC_REM = OPC_RISC_ARITH \| (0x6 << 12) \| (0x01 << 25),
	79	OPC_RISC_REMU = OPC_RISC_ARITH \| (0x7 << 12) \| (0x01 << 25),
	80	};
	81
	82
	83	#define MASK_OP_ARITH_IMM(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
	84	enum {
	85	OPC_RISC_ADDI = OPC_RISC_ARITH_IMM \| (0x0 << 12),
86	OPC_RISC_SLTI = OPC_RISC_ARITH_IMM \| (0x2 << 12),
87	OPC_RISC_SLTIU = OPC_RISC_ARITH_IMM \| (0x3 << 12),
88	OPC_RISC_XORI = OPC_RISC_ARITH_IMM \| (0x4 << 12),
89	OPC_RISC_ORI = OPC_RISC_ARITH_IMM \| (0x6 << 12),
90	OPC_RISC_ANDI = OPC_RISC_ARITH_IMM \| (0x7 << 12),
91	OPC_RISC_SLLI = OPC_RISC_ARITH_IMM \| (0x1 << 12), /* additional part of
92	IMM */
93	OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM \| (0x5 << 12) /* SRAI, SRLI */
94	};
95
96	#define MASK_OP_BRANCH(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
97	enum {
98	OPC_RISC_BEQ = OPC_RISC_BRANCH \| (0x0 << 12),
99	OPC_RISC_BNE = OPC_RISC_BRANCH \| (0x1 << 12),
100	OPC_RISC_BLT = OPC_RISC_BRANCH \| (0x4 << 12),
101	OPC_RISC_BGE = OPC_RISC_BRANCH \| (0x5 << 12),
102	OPC_RISC_BLTU = OPC_RISC_BRANCH \| (0x6 << 12),
103	OPC_RISC_BGEU = OPC_RISC_BRANCH \| (0x7 << 12)
104	};
105
106	enum {
107	OPC_RISC_ADDIW = OPC_RISC_ARITH_IMM_W \| (0x0 << 12),
108	OPC_RISC_SLLIW = OPC_RISC_ARITH_IMM_W \| (0x1 << 12), /* additional part of
109	IMM */
110	OPC_RISC_SHIFT_RIGHT_IW = OPC_RISC_ARITH_IMM_W \| (0x5 << 12) /* SRAI, SRLI
111	*/
112	};
113
114	enum {
115	OPC_RISC_ADDW = OPC_RISC_ARITH_W \| (0x0 << 12) \| (0x00 << 25),
116	OPC_RISC_SUBW = OPC_RISC_ARITH_W \| (0x0 << 12) \| (0x20 << 25),
117	OPC_RISC_SLLW = OPC_RISC_ARITH_W \| (0x1 << 12) \| (0x00 << 25),
118	OPC_RISC_SRLW = OPC_RISC_ARITH_W \| (0x5 << 12) \| (0x00 << 25),
119	OPC_RISC_SRAW = OPC_RISC_ARITH_W \| (0x5 << 12) \| (0x20 << 25),
120
121	/* RV64M */
122	OPC_RISC_MULW = OPC_RISC_ARITH_W \| (0x0 << 12) \| (0x01 << 25),
123	OPC_RISC_DIVW = OPC_RISC_ARITH_W \| (0x4 << 12) \| (0x01 << 25),
124	OPC_RISC_DIVUW = OPC_RISC_ARITH_W \| (0x5 << 12) \| (0x01 << 25),
125	OPC_RISC_REMW = OPC_RISC_ARITH_W \| (0x6 << 12) \| (0x01 << 25),
126	OPC_RISC_REMUW = OPC_RISC_ARITH_W \| (0x7 << 12) \| (0x01 << 25),
127	};
128
129	#define MASK_OP_LOAD(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
130	enum {
131	OPC_RISC_LB = OPC_RISC_LOAD \| (0x0 << 12),
132	OPC_RISC_LH = OPC_RISC_LOAD \| (0x1 << 12),
133	OPC_RISC_LW = OPC_RISC_LOAD \| (0x2 << 12),
134	OPC_RISC_LD = OPC_RISC_LOAD \| (0x3 << 12),
135	OPC_RISC_LBU = OPC_RISC_LOAD \| (0x4 << 12),
136	OPC_RISC_LHU = OPC_RISC_LOAD \| (0x5 << 12),
137	OPC_RISC_LWU = OPC_RISC_LOAD \| (0x6 << 12),
138	};
139
140	#define MASK_OP_STORE(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
141	enum {
142	OPC_RISC_SB = OPC_RISC_STORE \| (0x0 << 12),
143	OPC_RISC_SH = OPC_RISC_STORE \| (0x1 << 12),
144	OPC_RISC_SW = OPC_RISC_STORE \| (0x2 << 12),
145	OPC_RISC_SD = OPC_RISC_STORE \| (0x3 << 12),
146	};
147
148	#define MASK_OP_JALR(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
149	/* no enum since OPC_RISC_JALR is the actual value */
150
151	#define MASK_OP_ATOMIC(op) \
152	(MASK_OP_MAJOR(op) \| (op & ((0x7 << 12) \| (0x7F << 25))))
153	#define MASK_OP_ATOMIC_NO_AQ_RL_SZ(op) \
154	(MASK_OP_MAJOR(op) \| (op & (0x1F << 27)))
155
156	enum {
157	OPC_RISC_LR = OPC_RISC_ATOMIC \| (0x02 << 27),
158	OPC_RISC_SC = OPC_RISC_ATOMIC \| (0x03 << 27),
159	OPC_RISC_AMOSWAP = OPC_RISC_ATOMIC \| (0x01 << 27),
160	OPC_RISC_AMOADD = OPC_RISC_ATOMIC \| (0x00 << 27),
161	OPC_RISC_AMOXOR = OPC_RISC_ATOMIC \| (0x04 << 27),
162	OPC_RISC_AMOAND = OPC_RISC_ATOMIC \| (0x0C << 27),
163	OPC_RISC_AMOOR = OPC_RISC_ATOMIC \| (0x08 << 27),
164	OPC_RISC_AMOMIN = OPC_RISC_ATOMIC \| (0x10 << 27),
165	OPC_RISC_AMOMAX = OPC_RISC_ATOMIC \| (0x14 << 27),
166	OPC_RISC_AMOMINU = OPC_RISC_ATOMIC \| (0x18 << 27),
167	OPC_RISC_AMOMAXU = OPC_RISC_ATOMIC \| (0x1C << 27),
168	};
169
170	#define MASK_OP_SYSTEM(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
171	enum {
172	OPC_RISC_ECALL = OPC_RISC_SYSTEM \| (0x0 << 12),
173	OPC_RISC_EBREAK = OPC_RISC_SYSTEM \| (0x0 << 12),
174	OPC_RISC_ERET = OPC_RISC_SYSTEM \| (0x0 << 12),
175	OPC_RISC_MRTS = OPC_RISC_SYSTEM \| (0x0 << 12),
176	OPC_RISC_MRTH = OPC_RISC_SYSTEM \| (0x0 << 12),
177	OPC_RISC_HRTS = OPC_RISC_SYSTEM \| (0x0 << 12),
178	OPC_RISC_WFI = OPC_RISC_SYSTEM \| (0x0 << 12),
179	OPC_RISC_SFENCEVM = OPC_RISC_SYSTEM \| (0x0 << 12),
180
181	OPC_RISC_CSRRW = OPC_RISC_SYSTEM \| (0x1 << 12),
182	OPC_RISC_CSRRS = OPC_RISC_SYSTEM \| (0x2 << 12),
183	OPC_RISC_CSRRC = OPC_RISC_SYSTEM \| (0x3 << 12),
184	OPC_RISC_CSRRWI = OPC_RISC_SYSTEM \| (0x5 << 12),
185	OPC_RISC_CSRRSI = OPC_RISC_SYSTEM \| (0x6 << 12),
186	OPC_RISC_CSRRCI = OPC_RISC_SYSTEM \| (0x7 << 12),
187	};
188
189	#define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
190	enum {
191	OPC_RISC_FLW = OPC_RISC_FP_LOAD \| (0x2 << 12),
192	OPC_RISC_FLD = OPC_RISC_FP_LOAD \| (0x3 << 12),
193	};
194
195	#define MASK_OP_FP_STORE(op) (MASK_OP_MAJOR(op) \| (op & (0x7 << 12)))
196	enum {
197	OPC_RISC_FSW = OPC_RISC_FP_STORE \| (0x2 << 12),
198	OPC_RISC_FSD = OPC_RISC_FP_STORE \| (0x3 << 12),
199	};
200
201	#define MASK_OP_FP_FMADD(op) (MASK_OP_MAJOR(op) \| (op & (0x3 << 25)))
202	enum {
203	OPC_RISC_FMADD_S = OPC_RISC_FMADD \| (0x0 << 25),
204	OPC_RISC_FMADD_D = OPC_RISC_FMADD \| (0x1 << 25),
205	};
206
207	#define MASK_OP_FP_FMSUB(op) (MASK_OP_MAJOR(op) \| (op & (0x3 << 25)))
208	enum {
209	OPC_RISC_FMSUB_S = OPC_RISC_FMSUB \| (0x0 << 25),
210	OPC_RISC_FMSUB_D = OPC_RISC_FMSUB \| (0x1 << 25),
211	};
212
213	#define MASK_OP_FP_FNMADD(op) (MASK_OP_MAJOR(op) \| (op & (0x3 << 25)))
214	enum {
215	OPC_RISC_FNMADD_S = OPC_RISC_FNMADD \| (0x0 << 25),
216	OPC_RISC_FNMADD_D = OPC_RISC_FNMADD \| (0x1 << 25),
217	};
218
219	#define MASK_OP_FP_FNMSUB(op) (MASK_OP_MAJOR(op) \| (op & (0x3 << 25)))
220	enum {
221	OPC_RISC_FNMSUB_S = OPC_RISC_FNMSUB \| (0x0 << 25),
222	OPC_RISC_FNMSUB_D = OPC_RISC_FNMSUB \| (0x1 << 25),
223	};
224
225	#define MASK_OP_FP_ARITH(op) (MASK_OP_MAJOR(op) \| (op & (0x7F << 25)))
226	enum {
227	/* float */
228	OPC_RISC_FADD_S = OPC_RISC_FP_ARITH \| (0x0 << 25),
229	OPC_RISC_FSUB_S = OPC_RISC_FP_ARITH \| (0x4 << 25),
230	OPC_RISC_FMUL_S = OPC_RISC_FP_ARITH \| (0x8 << 25),
231	OPC_RISC_FDIV_S = OPC_RISC_FP_ARITH \| (0xC << 25),
232
233	OPC_RISC_FSGNJ_S = OPC_RISC_FP_ARITH \| (0x10 << 25),
234	OPC_RISC_FSGNJN_S = OPC_RISC_FP_ARITH \| (0x10 << 25),
235	OPC_RISC_FSGNJX_S = OPC_RISC_FP_ARITH \| (0x10 << 25),
236
237	OPC_RISC_FMIN_S = OPC_RISC_FP_ARITH \| (0x14 << 25),
238	OPC_RISC_FMAX_S = OPC_RISC_FP_ARITH \| (0x14 << 25),
239
240	OPC_RISC_FSQRT_S = OPC_RISC_FP_ARITH \| (0x2C << 25),
241
242	OPC_RISC_FEQ_S = OPC_RISC_FP_ARITH \| (0x50 << 25),
243	OPC_RISC_FLT_S = OPC_RISC_FP_ARITH \| (0x50 << 25),
244	OPC_RISC_FLE_S = OPC_RISC_FP_ARITH \| (0x50 << 25),
245
246	OPC_RISC_FCVT_W_S = OPC_RISC_FP_ARITH \| (0x60 << 25),
247	OPC_RISC_FCVT_WU_S = OPC_RISC_FP_ARITH \| (0x60 << 25),
248	OPC_RISC_FCVT_L_S = OPC_RISC_FP_ARITH \| (0x60 << 25),
249	OPC_RISC_FCVT_LU_S = OPC_RISC_FP_ARITH \| (0x60 << 25),
250
251	OPC_RISC_FCVT_S_W = OPC_RISC_FP_ARITH \| (0x68 << 25),
252	OPC_RISC_FCVT_S_WU = OPC_RISC_FP_ARITH \| (0x68 << 25),
253	OPC_RISC_FCVT_S_L = OPC_RISC_FP_ARITH \| (0x68 << 25),
254	OPC_RISC_FCVT_S_LU = OPC_RISC_FP_ARITH \| (0x68 << 25),
255
256	OPC_RISC_FMV_X_S = OPC_RISC_FP_ARITH \| (0x70 << 25),
257	OPC_RISC_FCLASS_S = OPC_RISC_FP_ARITH \| (0x70 << 25),
258
259	OPC_RISC_FMV_S_X = OPC_RISC_FP_ARITH \| (0x78 << 25),
260
261	/* double */
262	OPC_RISC_FADD_D = OPC_RISC_FP_ARITH \| (0x1 << 25),
263	OPC_RISC_FSUB_D = OPC_RISC_FP_ARITH \| (0x5 << 25),
264	OPC_RISC_FMUL_D = OPC_RISC_FP_ARITH \| (0x9 << 25),
265	OPC_RISC_FDIV_D = OPC_RISC_FP_ARITH \| (0xD << 25),
266
267	OPC_RISC_FSGNJ_D = OPC_RISC_FP_ARITH \| (0x11 << 25),
268	OPC_RISC_FSGNJN_D = OPC_RISC_FP_ARITH \| (0x11 << 25),
269	OPC_RISC_FSGNJX_D = OPC_RISC_FP_ARITH \| (0x11 << 25),
270
271	OPC_RISC_FMIN_D = OPC_RISC_FP_ARITH \| (0x15 << 25),
272	OPC_RISC_FMAX_D = OPC_RISC_FP_ARITH \| (0x15 << 25),
273
274	OPC_RISC_FCVT_S_D = OPC_RISC_FP_ARITH \| (0x20 << 25),
275
276	OPC_RISC_FCVT_D_S = OPC_RISC_FP_ARITH \| (0x21 << 25),
277
278	OPC_RISC_FSQRT_D = OPC_RISC_FP_ARITH \| (0x2D << 25),
279
280	OPC_RISC_FEQ_D = OPC_RISC_FP_ARITH \| (0x51 << 25),
281	OPC_RISC_FLT_D = OPC_RISC_FP_ARITH \| (0x51 << 25),
282	OPC_RISC_FLE_D = OPC_RISC_FP_ARITH \| (0x51 << 25),
283
284	OPC_RISC_FCVT_W_D = OPC_RISC_FP_ARITH \| (0x61 << 25),
285	OPC_RISC_FCVT_WU_D = OPC_RISC_FP_ARITH \| (0x61 << 25),
286	OPC_RISC_FCVT_L_D = OPC_RISC_FP_ARITH \| (0x61 << 25),
287	OPC_RISC_FCVT_LU_D = OPC_RISC_FP_ARITH \| (0x61 << 25),
288
289	OPC_RISC_FCVT_D_W = OPC_RISC_FP_ARITH \| (0x69 << 25),
290	OPC_RISC_FCVT_D_WU = OPC_RISC_FP_ARITH \| (0x69 << 25),
291	OPC_RISC_FCVT_D_L = OPC_RISC_FP_ARITH \| (0x69 << 25),
292	OPC_RISC_FCVT_D_LU = OPC_RISC_FP_ARITH \| (0x69 << 25),
293
294	OPC_RISC_FMV_X_D = OPC_RISC_FP_ARITH \| (0x71 << 25),
295	OPC_RISC_FCLASS_D = OPC_RISC_FP_ARITH \| (0x71 << 25),
296
297	OPC_RISC_FMV_D_X = OPC_RISC_FP_ARITH \| (0x79 << 25),
298	};
299
300	#define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301	\| (extract32(inst, 25, 6) << 5) \
302	\| (extract32(inst, 7, 1) << 11) \
303	\| (sextract64(inst, 31, 1) << 12))
304
305	#define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
306	\| (sextract64(inst, 25, 7) << 5))
307
308	#define GET_JAL_IMM(inst) ((extract32(inst, 21, 10) << 1) \
309	\| (extract32(inst, 20, 1) << 11) \
310	\| (extract32(inst, 12, 8) << 12) \
311	\| (sextract64(inst, 31, 1) << 20))
312
313	#define GET_RM(inst) extract32(inst, 12, 3)
314	#define GET_RS3(inst) extract32(inst, 27, 5)
315	#define GET_RS1(inst) extract32(inst, 15, 5)
316	#define GET_RS2(inst) extract32(inst, 20, 5)
317	#define GET_RD(inst) extract32(inst, 7, 5)
318	#define GET_IMM(inst) sextract64(inst, 20, 12)
319
320	/* RVC decoding macros */
321	#define GET_C_IMM(inst) (extract32(inst, 2, 5) \
322	\| (sextract64(inst, 12, 1) << 5))
323	#define GET_C_ZIMM(inst) (extract32(inst, 2, 5) \
324	\| (extract32(inst, 12, 1) << 5))
325	#define GET_C_ADDI4SPN_IMM(inst) ((extract32(inst, 6, 1) << 2) \
326	\| (extract32(inst, 5, 1) << 3) \
327	\| (extract32(inst, 11, 2) << 4) \
328	\| (extract32(inst, 7, 4) << 6))
329	#define GET_C_ADDI16SP_IMM(inst) ((extract32(inst, 6, 1) << 4) \
330	\| (extract32(inst, 2, 1) << 5) \
331	\| (extract32(inst, 5, 1) << 6) \
332	\| (extract32(inst, 3, 2) << 7) \
333	\| (sextract64(inst, 12, 1) << 9))
334	#define GET_C_LWSP_IMM(inst) ((extract32(inst, 4, 3) << 2) \
335	\| (extract32(inst, 12, 1) << 5) \
336	\| (extract32(inst, 2, 2) << 6))
337	#define GET_C_LDSP_IMM(inst) ((extract32(inst, 5, 2) << 3) \
338	\| (extract32(inst, 12, 1) << 5) \
339	\| (extract32(inst, 2, 3) << 6))
340	#define GET_C_SWSP_IMM(inst) ((extract32(inst, 9, 4) << 2) \
341	\| (extract32(inst, 7, 2) << 6))
342	#define GET_C_SDSP_IMM(inst) ((extract32(inst, 10, 3) << 3) \
343	\| (extract32(inst, 7, 3) << 6))
344	#define GET_C_LW_IMM(inst) ((extract32(inst, 6, 1) << 2) \
345	\| (extract32(inst, 10, 3) << 3) \
346	\| (extract32(inst, 5, 1) << 6))
25139bf7 AB	347	#define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \
25139bf7 AB	348	\| (extract16(inst, 5, 2) << 6))
55c2a12c MC	349	#define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \
	350	\| (extract32(inst, 11, 1) << 4) \
	351	\| (extract32(inst, 2, 1) << 5) \
	352	\| (extract32(inst, 7, 1) << 6) \
	353	\| (extract32(inst, 6, 1) << 7) \
	354	\| (extract32(inst, 9, 2) << 8) \
	355	\| (extract32(inst, 8, 1) << 10) \
	356	\| (sextract64(inst, 12, 1) << 11))
	357	#define GET_C_B_IMM(inst) ((extract32(inst, 3, 2) << 1) \
	358	\| (extract32(inst, 10, 2) << 3) \
	359	\| (extract32(inst, 2, 1) << 5) \
	360	\| (extract32(inst, 5, 2) << 6) \
	361	\| (sextract64(inst, 12, 1) << 8))
	362	#define GET_C_SIMM3(inst) extract32(inst, 10, 3)
	363	#define GET_C_RD(inst) GET_RD(inst)
	364	#define GET_C_RS1(inst) GET_RD(inst)
	365	#define GET_C_RS2(inst) extract32(inst, 2, 5)
25139bf7 AB	366	#define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3))
25139bf7 AB	367	#define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3))
f91005e1 MA	368
f91005e1 MA	369	#endif