[qemu.git] / hw / arm_sysctl.c

/*
 * Status and system control registers for ARM RealView/Versatile boards.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "sysbus.h"
#include "primecell.h"
#include "sysemu.h"

#define LOCK_VALUE 0xa05f

typedef struct {
    SysBusDevice busdev;
    uint32_t sys_id;
    uint32_t leds;
    uint16_t lockval;
    uint32_t cfgdata1;
    uint32_t cfgdata2;
    uint32_t flags;
    uint32_t nvflags;
    uint32_t resetlevel;
} arm_sysctl_state;

static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x00: /* ID */
        return s->sys_id;
    case 0x04: /* SW */
        /* General purpose hardware switches.
           We don't have a useful way of exposing these to the user.  */
        return 0;
    case 0x08: /* LED */
        return s->leds;
    case 0x20: /* LOCK */
        return s->lockval;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
    case 0x24: /* 100HZ */
        /* ??? Implement these.  */
        return 0;
    case 0x28: /* CFGDATA1 */
        return s->cfgdata1;
    case 0x2c: /* CFGDATA2 */
        return s->cfgdata2;
    case 0x30: /* FLAGS */
        return s->flags;
    case 0x38: /* NVFLAGS */
        return s->nvflags;
    case 0x40: /* RESETCTL */
        return s->resetlevel;
    case 0x44: /* PCICTL */
        return 1;
    case 0x48: /* MCI */
        return 0;
    case 0x4c: /* FLASH */
        return 0;
    case 0x50: /* CLCD */
        return 0x1000;
    case 0x54: /* CLCDSER */
        return 0;
    case 0x58: /* BOOTCS */
        return 0;
    case 0x5c: /* 24MHz */
        return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec());
    case 0x60: /* MISC */
        return 0;
    case 0x84: /* PROCID0 */
        /* ??? Don't know what the proper value for the core tile ID is.  */
        return 0x02000000;
    case 0x88: /* PROCID1 */
        return 0xff000000;
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
    case 0xc0: /* SYS_TEST_OSC0 */
    case 0xc4: /* SYS_TEST_OSC1 */
    case 0xc8: /* SYS_TEST_OSC2 */
    case 0xcc: /* SYS_TEST_OSC3 */
    case 0xd0: /* SYS_TEST_OSC4 */
        return 0;
    default:
        printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
                          uint32_t val)
{
    arm_sysctl_state *s = (arm_sysctl_state *)opaque;

    switch (offset) {
    case 0x08: /* LED */
        s->leds = val;
    case 0x0c: /* OSC0 */
    case 0x10: /* OSC1 */
    case 0x14: /* OSC2 */
    case 0x18: /* OSC3 */
    case 0x1c: /* OSC4 */
        /* ??? */
        break;
    case 0x20: /* LOCK */
        if (val == LOCK_VALUE)
            s->lockval = val;
        else
            s->lockval = val & 0x7fff;
        break;
    case 0x28: /* CFGDATA1 */
        /* ??? Need to implement this.  */
        s->cfgdata1 = val;
        break;
    case 0x2c: /* CFGDATA2 */
        /* ??? Need to implement this.  */
        s->cfgdata2 = val;
        break;
    case 0x30: /* FLAGSSET */
        s->flags |= val;
        break;
    case 0x34: /* FLAGSCLR */
        s->flags &= ~val;
        break;
    case 0x38: /* NVFLAGSSET */
        s->nvflags |= val;
        break;
    case 0x3c: /* NVFLAGSCLR */
        s->nvflags &= ~val;
        break;
    case 0x40: /* RESETCTL */
        if (s->lockval == LOCK_VALUE) {
            s->resetlevel = val;
            if (val & 0x100)
                qemu_system_reset_request ();
        }
        break;
    case 0x44: /* PCICTL */
        /* nothing to do.  */
        break;
    case 0x4c: /* FLASH */
    case 0x50: /* CLCD */
    case 0x54: /* CLCDSER */
    case 0x64: /* DMAPSR0 */
    case 0x68: /* DMAPSR1 */
    case 0x6c: /* DMAPSR2 */
    case 0x70: /* IOSEL */
    case 0x74: /* PLDCTL */
    case 0x80: /* BUSID */
    case 0x84: /* PROCID0 */
    case 0x88: /* PROCID1 */
    case 0x8c: /* OSCRESET0 */
    case 0x90: /* OSCRESET1 */
    case 0x94: /* OSCRESET2 */
    case 0x98: /* OSCRESET3 */
    case 0x9c: /* OSCRESET4 */
        break;
    default:
        printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
}

static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
   arm_sysctl_read,
   arm_sysctl_read,
   arm_sysctl_read
};

static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
   arm_sysctl_write,
   arm_sysctl_write,
   arm_sysctl_write
};

static int arm_sysctl_init1(SysBusDevice *dev)
{
    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
    int iomemtype;

    /* The MPcore bootloader uses these flags to start secondary CPUs.
       We don't use a bootloader, so do this here.  */
    s->flags = 3;
    iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
                                       arm_sysctl_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    /* ??? Save/restore.  */
    return 0;
}

/* Legacy helper function.  */
void arm_sysctl_init(uint32_t base, uint32_t sys_id)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(dev, "sys_id", sys_id);
    qdev_init(dev);
    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}

static SysBusDeviceInfo arm_sysctl_info = {
    .init = arm_sysctl_init1,
    .qdev.name  = "realview_sysctl",
    .qdev.size  = sizeof(arm_sysctl_state),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void arm_sysctl_register_devices(void)
{
    sysbus_register_withprop(&arm_sysctl_info);
}

device_init(arm_sysctl_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* Status and system control registers for ARM RealView/Versatile boards.
e69954b9 PB	3	*
9ee6e8bb	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
042eb37a DJ	10	#include "hw.h"
042eb37a DJ	11	#include "qemu-timer.h"
82634c2d	12	#include "sysbus.h"
9596ebb7	13	#include "primecell.h"
87ecb68b	14	#include "sysemu.h"
e69954b9 PB	15
	16	#define LOCK_VALUE 0xa05f
	17
	18	typedef struct {
82634c2d	19	SysBusDevice busdev;
e69954b9 PB	20	uint32_t sys_id;
	21	uint32_t leds;
	22	uint16_t lockval;
	23	uint32_t cfgdata1;
	24	uint32_t cfgdata2;
	25	uint32_t flags;
	26	uint32_t nvflags;
	27	uint32_t resetlevel;
	28	} arm_sysctl_state;
	29
c227f099	30	static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
e69954b9 PB	31	{
	32	arm_sysctl_state s = (arm_sysctl_state )opaque;
	33
e69954b9 PB	34	switch (offset) {
	35	case 0x00: /* ID */
	36	return s->sys_id;
	37	case 0x04: /* SW */
	38	/* General purpose hardware switches.
	39	We don't have a useful way of exposing these to the user. */
	40	return 0;
	41	case 0x08: /* LED */
	42	return s->leds;
	43	case 0x20: /* LOCK */
	44	return s->lockval;
	45	case 0x0c: /* OSC0 */
	46	case 0x10: /* OSC1 */
	47	case 0x14: /* OSC2 */
	48	case 0x18: /* OSC3 */
	49	case 0x1c: /* OSC4 */
	50	case 0x24: /* 100HZ */
	51	/* ??? Implement these. */
	52	return 0;
	53	case 0x28: /* CFGDATA1 */
	54	return s->cfgdata1;
	55	case 0x2c: /* CFGDATA2 */
	56	return s->cfgdata2;
	57	case 0x30: /* FLAGS */
	58	return s->flags;
	59	case 0x38: /* NVFLAGS */
	60	return s->nvflags;
	61	case 0x40: /* RESETCTL */
	62	return s->resetlevel;
	63	case 0x44: /* PCICTL */
	64	return 1;
	65	case 0x48: /* MCI */
	66	return 0;
	67	case 0x4c: /* FLASH */
	68	return 0;
	69	case 0x50: /* CLCD */
	70	return 0x1000;
	71	case 0x54: /* CLCDSER */
	72	return 0;
	73	case 0x58: /* BOOTCS */
	74	return 0;
	75	case 0x5c: /* 24MHz */
042eb37a	76	return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec());
e69954b9 PB	77	case 0x60: /* MISC */
	78	return 0;
	79	case 0x84: /* PROCID0 */
	80	/* ??? Don't know what the proper value for the core tile ID is. */
	81	return 0x02000000;
	82	case 0x88: /* PROCID1 */
	83	return 0xff000000;
	84	case 0x64: /* DMAPSR0 */
	85	case 0x68: /* DMAPSR1 */
	86	case 0x6c: /* DMAPSR2 */
	87	case 0x70: /* IOSEL */
	88	case 0x74: /* PLDCTL */
	89	case 0x80: /* BUSID */
	90	case 0x8c: /* OSCRESET0 */
	91	case 0x90: /* OSCRESET1 */
	92	case 0x94: /* OSCRESET2 */
	93	case 0x98: /* OSCRESET3 */
	94	case 0x9c: /* OSCRESET4 */
	95	case 0xc0: /* SYS_TEST_OSC0 */
	96	case 0xc4: /* SYS_TEST_OSC1 */
	97	case 0xc8: /* SYS_TEST_OSC2 */
	98	case 0xcc: /* SYS_TEST_OSC3 */
	99	case 0xd0: /* SYS_TEST_OSC4 */
	100	return 0;
	101	default:
	102	printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
	103	return 0;
	104	}
	105	}
	106
c227f099	107	static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
e69954b9 PB	108	uint32_t val)
	109	{
	110	arm_sysctl_state s = (arm_sysctl_state )opaque;
e69954b9 PB	111
	112	switch (offset) {
	113	case 0x08: /* LED */
	114	s->leds = val;
	115	case 0x0c: /* OSC0 */
	116	case 0x10: /* OSC1 */
	117	case 0x14: /* OSC2 */
	118	case 0x18: /* OSC3 */
	119	case 0x1c: /* OSC4 */
	120	/* ??? */
	121	break;
	122	case 0x20: /* LOCK */
	123	if (val == LOCK_VALUE)
	124	s->lockval = val;
	125	else
	126	s->lockval = val & 0x7fff;
	127	break;
	128	case 0x28: /* CFGDATA1 */
	129	/* ??? Need to implement this. */
	130	s->cfgdata1 = val;
	131	break;
	132	case 0x2c: /* CFGDATA2 */
	133	/* ??? Need to implement this. */
	134	s->cfgdata2 = val;
	135	break;
	136	case 0x30: /* FLAGSSET */
	137	s->flags \|= val;
	138	break;
	139	case 0x34: /* FLAGSCLR */
	140	s->flags &= ~val;
	141	break;
	142	case 0x38: /* NVFLAGSSET */
	143	s->nvflags \|= val;
	144	break;
	145	case 0x3c: /* NVFLAGSCLR */
	146	s->nvflags &= ~val;
	147	break;
	148	case 0x40: /* RESETCTL */
	149	if (s->lockval == LOCK_VALUE) {
	150	s->resetlevel = val;
	151	if (val & 0x100)
f3d6b95e	152	qemu_system_reset_request ();
e69954b9 PB	153	}
	154	break;
	155	case 0x44: /* PCICTL */
	156	/* nothing to do. */
	157	break;
	158	case 0x4c: /* FLASH */
	159	case 0x50: /* CLCD */
	160	case 0x54: /* CLCDSER */
	161	case 0x64: /* DMAPSR0 */
	162	case 0x68: /* DMAPSR1 */
	163	case 0x6c: /* DMAPSR2 */
	164	case 0x70: /* IOSEL */
	165	case 0x74: /* PLDCTL */
	166	case 0x80: /* BUSID */
	167	case 0x84: /* PROCID0 */
	168	case 0x88: /* PROCID1 */
	169	case 0x8c: /* OSCRESET0 */
	170	case 0x90: /* OSCRESET1 */
	171	case 0x94: /* OSCRESET2 */
	172	case 0x98: /* OSCRESET3 */
	173	case 0x9c: /* OSCRESET4 */
	174	break;
	175	default:
	176	printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
	177	return;
	178	}
	179	}
	180
d60efc6b	181	static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
e69954b9 PB	182	arm_sysctl_read,
	183	arm_sysctl_read,
	184	arm_sysctl_read
	185	};
	186
d60efc6b	187	static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
e69954b9 PB	188	arm_sysctl_write,
	189	arm_sysctl_write,
	190	arm_sysctl_write
	191	};
	192
81a322d4	193	static int arm_sysctl_init1(SysBusDevice *dev)
e69954b9	194	{
82634c2d	195	arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
e69954b9 PB	196	int iomemtype;
e69954b9 PB	197
9ee6e8bb PB	198	/* The MPcore bootloader uses these flags to start secondary CPUs.
	199	We don't use a bootloader, so do this here. */
	200	s->flags = 3;
1eed09cb	201	iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
e69954b9	202	arm_sysctl_writefn, s);
82634c2d	203	sysbus_init_mmio(dev, 0x1000, iomemtype);
e69954b9	204	/* ??? Save/restore. */
81a322d4	205	return 0;
e69954b9	206	}
82634c2d PB	207
	208	/* Legacy helper function. */
	209	void arm_sysctl_init(uint32_t base, uint32_t sys_id)
	210	{
	211	DeviceState *dev;
	212
	213	dev = qdev_create(NULL, "realview_sysctl");
ee6847d1	214	qdev_prop_set_uint32(dev, "sys_id", sys_id);
82634c2d PB	215	qdev_init(dev);
	216	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
	217	}
	218
ee6847d1 GH	219	static SysBusDeviceInfo arm_sysctl_info = {
	220	.init = arm_sysctl_init1,
	221	.qdev.name = "realview_sysctl",
	222	.qdev.size = sizeof(arm_sysctl_state),
	223	.qdev.props = (Property[]) {
e325775b GH	224	DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
e325775b GH	225	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	226	}
	227	};
	228
82634c2d PB	229	static void arm_sysctl_register_devices(void)
82634c2d PB	230	{
ee6847d1	231	sysbus_register_withprop(&arm_sysctl_info);
82634c2d PB	232	}
	233
	234	device_init(arm_sysctl_register_devices)