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target-alpha: convert cmp* instructions to TCG
[qemu.git] / target-alpha / translate.c
CommitLineData
4c9649a9
JM		 1/*
2 * Alpha emulation cpu translation for qemu.
5fafdf24 3 *
4c9649a9
JM		 4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <stdint.h>
22#include <stdlib.h>
23#include <stdio.h>
24
25#include "cpu.h"
26#include "exec-all.h"
27#include "disas.h"
ae8ecd42 28#include "host-utils.h"
496cb5b9 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
4c9649a9
JM		 32
33#define DO_SINGLE_STEP
34#define GENERATE_NOP
35#define ALPHA_DEBUG_DISAS
36#define DO_TB_FLUSH
37
38typedef struct DisasContext DisasContext;
39struct DisasContext {
40 uint64_t pc;
41 int mem_idx;
42#if !defined (CONFIG_USER_ONLY)
43 int pal_mode;
44#endif
45 uint32_t amask;
46};
47
3761035f 48/* global register indexes */
b2437bf2 49static TCGv cpu_env;
496cb5b9
AJ		 50static TCGv cpu_ir[31];
51static TCGv cpu_pc;
52
3761035f
AJ		 53/* dyngen register indexes */
54static TCGv cpu_T[3];
55
56/* register names */
6ba8dcd7 57static char cpu_reg_names[10*4+21*5];
2e70f6ef
PB		 58
59#include "gen-icount.h"
60
a5f1b965 61static void alpha_translate_init(void)
2e70f6ef 62{
496cb5b9
AJ		 63 int i;
64 char *p;
2e70f6ef 65 static int done_init = 0;
496cb5b9 66
2e70f6ef
PB		 67 if (done_init)
68 return;
496cb5b9 69
2e70f6ef 70 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
496cb5b9 71
3761035f
AJ		 72#if TARGET_LONG_BITS > HOST_LONG_BITS
73 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
74 offsetof(CPUState, t0), "T0");
75 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
76 offsetof(CPUState, t1), "T1");
77 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
78 offsetof(CPUState, t2), "T2");
79#else
80 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
81 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
82 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2");
83#endif
84
496cb5b9
AJ		 85 p = cpu_reg_names;
86 for (i = 0; i < 31; i++) {
87 sprintf(p, "ir%d", i);
88 cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
89 offsetof(CPUState, ir[i]), p);
6ba8dcd7 90 p += (i < 10) ? 4 : 5;
496cb5b9
AJ		 91 }
92
93 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
94 offsetof(CPUState, pc), "pc");
95
96 /* register helpers */
97#undef DEF_HELPER
98#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
99#include "helper.h"
100
2e70f6ef
PB		 101 done_init = 1;
102}
103
f071b4d3 104static always_inline void gen_op_nop (void)
4c9649a9
JM		 105{
106#if defined(GENERATE_NOP)
107 gen_op_no_op();
108#endif
109}
110
111#define GEN32(func, NAME) \
112static GenOpFunc *NAME ## _table [32] = { \
113NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
114NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
115NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
116NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
117NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
118NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
119NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
120NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
121}; \
f071b4d3 122static always_inline void func (int n) \
4c9649a9
JM		 123{ \
124 NAME ## _table[n](); \
125}
126
4c9649a9
JM		 127/* FIR moves */
128/* Special hacks for fir31 */
129#define gen_op_load_FT0_fir31 gen_op_reset_FT0
130#define gen_op_load_FT1_fir31 gen_op_reset_FT1
131#define gen_op_load_FT2_fir31 gen_op_reset_FT2
132#define gen_op_store_FT0_fir31 gen_op_nop
133#define gen_op_store_FT1_fir31 gen_op_nop
134#define gen_op_store_FT2_fir31 gen_op_nop
135#define gen_op_cmov_fir31 gen_op_nop
136GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
137GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
138GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
139GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
140GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
141GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
142GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
143
f071b4d3 144static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
4c9649a9
JM		 145{
146 switch (Tn) {
147 case 0:
148 gen_op_load_FT0_fir(firn);
149 break;
150 case 1:
151 gen_op_load_FT1_fir(firn);
152 break;
153 case 2:
154 gen_op_load_FT2_fir(firn);
155 break;
156 }
157}
158
f071b4d3 159static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
4c9649a9
JM		 160{
161 switch (Tn) {
162 case 0:
163 gen_op_store_FT0_fir(firn);
164 break;
165 case 1:
166 gen_op_store_FT1_fir(firn);
167 break;
168 case 2:
169 gen_op_store_FT2_fir(firn);
170 break;
171 }
172}
173
174/* Memory moves */
175#if defined(CONFIG_USER_ONLY)
176#define OP_LD_TABLE(width) \
177static GenOpFunc *gen_op_ld##width[] = { \
178 &gen_op_ld##width##_raw, \
179}
180#define OP_ST_TABLE(width) \
181static GenOpFunc *gen_op_st##width[] = { \
182 &gen_op_st##width##_raw, \
183}
184#else
185#define OP_LD_TABLE(width) \
186static GenOpFunc *gen_op_ld##width[] = { \
187 &gen_op_ld##width##_kernel, \
bb6f6792
JM		 188 &gen_op_ld##width##_executive, \
189 &gen_op_ld##width##_supervisor, \
190 &gen_op_ld##width##_user, \
4c9649a9
JM		 191}
192#define OP_ST_TABLE(width) \
193static GenOpFunc *gen_op_st##width[] = { \
194 &gen_op_st##width##_kernel, \
bb6f6792
JM		 195 &gen_op_st##width##_executive, \
196 &gen_op_st##width##_supervisor, \
197 &gen_op_st##width##_user, \
4c9649a9
JM		 198}
199#endif
200
201#define GEN_LD(width) \
202OP_LD_TABLE(width); \
f071b4d3 203static always_inline void gen_ld##width (DisasContext *ctx) \
4c9649a9
JM		 204{ \
205 (*gen_op_ld##width[ctx->mem_idx])(); \
206}
207
208#define GEN_ST(width) \
209OP_ST_TABLE(width); \
f071b4d3 210static always_inline void gen_st##width (DisasContext *ctx) \
4c9649a9
JM		 211{ \
212 (*gen_op_st##width[ctx->mem_idx])(); \
213}
214
215GEN_LD(bu);
216GEN_ST(b);
217GEN_LD(wu);
218GEN_ST(w);
219GEN_LD(l);
220GEN_ST(l);
221GEN_LD(q);
222GEN_ST(q);
223GEN_LD(q_u);
224GEN_ST(q_u);
225GEN_LD(l_l);
226GEN_ST(l_c);
227GEN_LD(q_l);
228GEN_ST(q_c);
229
08ab123c 230#if 0 /* currently unused */
4c9649a9
JM		 231GEN_LD(f);
232GEN_ST(f);
233GEN_LD(g);
234GEN_ST(g);
08ab123c 235#endif /* 0 */
4c9649a9
JM		 236GEN_LD(s);
237GEN_ST(s);
238GEN_LD(t);
239GEN_ST(t);
240
f071b4d3 241static always_inline void _gen_op_bcond (DisasContext *ctx)
4c9649a9
JM		 242{
243#if 0 // Qemu does not know how to do this...
244 gen_op_bcond(ctx->pc);
245#else
246 gen_op_bcond(ctx->pc >> 32, ctx->pc);
247#endif
248}
249
f071b4d3
JM		 250static always_inline void gen_excp (DisasContext *ctx,
251 int exception, int error_code)
4c9649a9 252{
6ad02592
AJ		 253 TCGv tmp1, tmp2;
254
496cb5b9 255 tcg_gen_movi_i64(cpu_pc, ctx->pc);
6ad02592
AJ		 256 tmp1 = tcg_const_i32(exception);
257 tmp2 = tcg_const_i32(error_code);
258 tcg_gen_helper_0_2(helper_excp, tmp1, tmp2);
259 tcg_temp_free(tmp2);
260 tcg_temp_free(tmp1);
4c9649a9
JM		 261}
262
f071b4d3 263static always_inline void gen_invalid (DisasContext *ctx)
4c9649a9
JM		 264{
265 gen_excp(ctx, EXCP_OPCDEC, 0);
266}
267
f071b4d3
JM		 268static always_inline void gen_load_mem (DisasContext *ctx,
269 void (*gen_load_op)(DisasContext *ctx),
270 int ra, int rb, int32_t disp16,
271 int clear)
4c9649a9
JM		 272{
273 if (ra == 31 && disp16 == 0) {
274 /* UNOP */
275 gen_op_nop();
276 } else {
3761035f 277 if (rb != 31)
4f821e17 278 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 279 else
4f821e17 280 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9 281 if (clear)
4f821e17 282 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
4c9649a9 283 (*gen_load_op)(ctx);
3761035f
AJ		 284 if (ra != 31)
285 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
4c9649a9
JM		 286 }
287}
288
f071b4d3
JM		 289static always_inline void gen_store_mem (DisasContext *ctx,
290 void (*gen_store_op)(DisasContext *ctx),
291 int ra, int rb, int32_t disp16,
292 int clear)
4c9649a9 293{
3761035f 294 if (rb != 31)
4f821e17 295 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 296 else
4f821e17 297 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9 298 if (clear)
4f821e17 299 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
3761035f
AJ		 300 if (ra != 31)
301 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
302 else
303 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9
JM		 304 (*gen_store_op)(ctx);
305}
306
f071b4d3
JM		 307static always_inline void gen_load_fmem (DisasContext *ctx,
308 void (*gen_load_fop)(DisasContext *ctx),
309 int ra, int rb, int32_t disp16)
4c9649a9 310{
3761035f 311 if (rb != 31)
4f821e17 312 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 313 else
4f821e17 314 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9
JM		 315 (*gen_load_fop)(ctx);
316 gen_store_fir(ctx, ra, 1);
317}
318
f071b4d3
JM		 319static always_inline void gen_store_fmem (DisasContext *ctx,
320 void (*gen_store_fop)(DisasContext *ctx),
321 int ra, int rb, int32_t disp16)
4c9649a9 322{
3761035f 323 if (rb != 31)
4f821e17 324 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 325 else
4f821e17 326 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9
JM		 327 gen_load_fir(ctx, ra, 1);
328 (*gen_store_fop)(ctx);
329}
330
f071b4d3 331static always_inline void gen_bcond (DisasContext *ctx,
9c29504e
AJ		 332 TCGCond cond,
333 int ra, int32_t disp16, int mask)
4c9649a9 334{
9c29504e
AJ		 335 int l1, l2;
336
337 l1 = gen_new_label();
338 l2 = gen_new_label();
339 if (likely(ra != 31)) {
340 if (mask) {
341 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
342 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
343 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
344 tcg_temp_free(tmp);
345 } else
346 tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
347 } else {
348 /* Very uncommon case - Do not bother to optimize. */
349 TCGv tmp = tcg_const_i64(0);
350 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
351 tcg_temp_free(tmp);
352 }
353 tcg_gen_movi_i64(cpu_pc, ctx->pc);
354 tcg_gen_br(l2);
355 gen_set_label(l1);
356 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
357 gen_set_label(l2);
4c9649a9
JM		 358}
359
f071b4d3
JM		 360static always_inline void gen_fbcond (DisasContext *ctx,
361 void (*gen_test_op)(void),
362 int ra, int32_t disp16)
4c9649a9 363{
4f821e17 364 tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
4c9649a9
JM		 365 gen_load_fir(ctx, ra, 0);
366 (*gen_test_op)();
367 _gen_op_bcond(ctx);
368}
369
f071b4d3
JM		 370static always_inline void gen_arith3 (DisasContext *ctx,
371 void (*gen_arith_op)(void),
372 int ra, int rb, int rc,
9e85e9bd 373 int islit, uint8_t lit)
4c9649a9 374{
3761035f
AJ		 375 if (ra != 31)
376 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
377 else
378 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 379 if (islit)
3761035f
AJ		 380 tcg_gen_movi_i64(cpu_T[1], lit);
381 else if (rb != 31)
382 tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
4c9649a9 383 else
3761035f 384 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9 385 (*gen_arith_op)();
3761035f
AJ		 386 if (rc != 31)
387 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
4c9649a9
JM		 388}
389
f071b4d3 390static always_inline void gen_cmov (DisasContext *ctx,
9c29504e 391 TCGCond inv_cond,
f071b4d3 392 int ra, int rb, int rc,
adf3c8b6 393 int islit, uint8_t lit, int mask)
4c9649a9 394{
9c29504e
AJ		 395 int l1;
396
397 if (unlikely(rc == 31))
398 return;
399
400 l1 = gen_new_label();
401
402 if (ra != 31) {
403 if (mask) {
404 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
405 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
406 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
407 tcg_temp_free(tmp);
408 } else
409 tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
410 } else {
411 /* Very uncommon case - Do not bother to optimize. */
412 TCGv tmp = tcg_const_i64(0);
413 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
414 tcg_temp_free(tmp);
415 }
416
4c9649a9 417 if (islit)
9c29504e 418 tcg_gen_movi_i64(cpu_ir[rc], lit);
3761035f 419 else if (rb != 31)
9c29504e 420 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
4c9649a9 421 else
9c29504e
AJ		 422 tcg_gen_movi_i64(cpu_ir[rc], 0);
423 gen_set_label(l1);
4c9649a9
JM		 424}
425
f071b4d3
JM		 426static always_inline void gen_farith2 (DisasContext *ctx,
427 void (*gen_arith_fop)(void),
428 int rb, int rc)
4c9649a9
JM		 429{
430 gen_load_fir(ctx, rb, 0);
431 (*gen_arith_fop)();
432 gen_store_fir(ctx, rc, 0);
433}
434
f071b4d3
JM		 435static always_inline void gen_farith3 (DisasContext *ctx,
436 void (*gen_arith_fop)(void),
437 int ra, int rb, int rc)
4c9649a9
JM		 438{
439 gen_load_fir(ctx, ra, 0);
440 gen_load_fir(ctx, rb, 1);
441 (*gen_arith_fop)();
442 gen_store_fir(ctx, rc, 0);
443}
444
f071b4d3
JM		 445static always_inline void gen_fcmov (DisasContext *ctx,
446 void (*gen_test_fop)(void),
447 int ra, int rb, int rc)
4c9649a9
JM		 448{
449 gen_load_fir(ctx, ra, 0);
450 gen_load_fir(ctx, rb, 1);
451 (*gen_test_fop)();
452 gen_op_cmov_fir(rc);
453}
454
f071b4d3
JM		 455static always_inline void gen_fti (DisasContext *ctx,
456 void (*gen_move_fop)(void),
457 int ra, int rc)
4c9649a9
JM		 458{
459 gen_load_fir(ctx, rc, 0);
460 (*gen_move_fop)();
3761035f
AJ		 461 if (ra != 31)
462 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 463}
464
f071b4d3
JM		 465static always_inline void gen_itf (DisasContext *ctx,
466 void (*gen_move_fop)(void),
467 int ra, int rc)
4c9649a9 468{
3761035f
AJ		 469 if (ra != 31)
470 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
471 else
472 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 473 (*gen_move_fop)();
474 gen_store_fir(ctx, rc, 0);
475}
476
b3249f63
AJ		 477/* EXTWH, EXTWH, EXTLH, EXTQH */
478static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
479 int ra, int rb, int rc,
adf3c8b6 480 int islit, uint8_t lit)
b3249f63
AJ		 481{
482 if (unlikely(rc == 31))
483 return;
484
485 if (ra != 31) {
486 if (islit)
487 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
488 else if (rb != 31) {
489 TCGv tmp1, tmp2;
490 tmp1 = tcg_temp_new(TCG_TYPE_I64);
491 tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
492 tcg_gen_shli_i64(tmp1, tmp1, 3);
493 tmp2 = tcg_const_i64(64);
494 tcg_gen_sub_i64(tmp1, tmp2, tmp1);
495 tcg_temp_free(tmp2);
496 if (tcg_gen_ext_i64) {
497 tcg_gen_shl_i64(tmp1, cpu_ir[ra], tmp1);
498 tcg_gen_ext_i64(cpu_ir[rc], tmp1);
499 } else
500 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
501 tcg_temp_free(tmp1);
502 } else
503 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
504 } else
505 tcg_gen_movi_i64(cpu_ir[rc], 0);
506}
507
508/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
509static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
510 int ra, int rb, int rc,
adf3c8b6 511 int islit, uint8_t lit)
b3249f63
AJ		 512{
513 if (unlikely(rc == 31))
514 return;
515
516 if (ra != 31) {
517 if (islit)
518 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
519 else if (rb != 31) {
520 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
521 tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
522 tcg_gen_shli_i64(tmp, tmp, 3);
523 if (tcg_gen_ext_i64) {
524 tcg_gen_shr_i64(tmp, cpu_ir[ra], tmp);
525 tcg_gen_ext_i64(cpu_ir[rc], tmp);
526 } else
527 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
528 tcg_temp_free(tmp);
529 } else
530 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
531 } else
532 tcg_gen_movi_i64(cpu_ir[rc], 0);
533}
534
535/* Code to call byte manipulation helpers, used by:
536 INSWH, INSLH, INSQH, INSBL, INSWL, INSLL, INSQL,
537 MSKWH, MSKLH, MSKQH, MSKBL, MSKWL, MSKLL, MSKQL,
538 ZAP, ZAPNOT
539
540 WARNING: it assumes that when ra31 is used, the result is 0.
541*/
542static always_inline void gen_byte_manipulation(void *helper,
543 int ra, int rb, int rc,
544 int islit, uint8_t lit)
545{
546 if (unlikely(rc == 31))
547 return;
548
549 if (ra != 31) {
550 if (islit || rb == 31) {
551 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
552 if (islit)
553 tcg_gen_movi_i64(tmp, lit);
554 else
555 tcg_gen_movi_i64(tmp, 0);
556 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp);
557 tcg_temp_free(tmp);
558 } else
559 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
560 } else
561 tcg_gen_movi_i64(cpu_ir[rc], 0);
562}
563
01ff9cc8
AJ		 564static always_inline void gen_cmp(TCGCond cond,
565 int ra, int rb, int rc,
566 int islit, int8_t lit)
567{
568 int l1, l2;
569 TCGv tmp;
570
571 if (unlikely(rc == 31))
572 return;
573
574 l1 = gen_new_label();
575 l2 = gen_new_label();
576
577 if (ra != 31) {
578 tmp = tcg_temp_new(TCG_TYPE_I64);
579 tcg_gen_mov_i64(tmp, cpu_ir[ra]);
580 } else
581 tmp = tcg_const_i64(0);
582 if (islit)
583 tcg_gen_brcondi_i64(cond, tmp, lit, l1);
584 else if (rb != 31)
585 tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
586 else
587 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
588
589 tcg_gen_movi_i64(cpu_ir[rc], 0);
590 tcg_gen_br(l2);
591 gen_set_label(l1);
592 tcg_gen_movi_i64(cpu_ir[rc], 1);
593 gen_set_label(l2);
594}
595
f071b4d3 596static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
4c9649a9
JM		 597{
598 uint32_t palcode;
599 int32_t disp21, disp16, disp12;
600 uint16_t fn11, fn16;
601 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
adf3c8b6 602 uint8_t lit;
4c9649a9
JM		 603 int ret;
604
605 /* Decode all instruction fields */
606 opc = insn >> 26;
607 ra = (insn >> 21) & 0x1F;
608 rb = (insn >> 16) & 0x1F;
609 rc = insn & 0x1F;
610 sbz = (insn >> 13) & 0x07;
611 islit = (insn >> 12) & 1;
612 lit = (insn >> 13) & 0xFF;
613 palcode = insn & 0x03FFFFFF;
614 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
615 disp16 = (int16_t)(insn & 0x0000FFFF);
616 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
617 fn16 = insn & 0x0000FFFF;
618 fn11 = (insn >> 5) & 0x000007FF;
619 fpfn = fn11 & 0x3F;
620 fn7 = (insn >> 5) & 0x0000007F;
621 fn2 = (insn >> 5) & 0x00000003;
622 ret = 0;
623#if defined ALPHA_DEBUG_DISAS
624 if (logfile != NULL) {
625 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
626 opc, ra, rb, rc, disp16);
627 }
628#endif
629 switch (opc) {
630 case 0x00:
631 /* CALL_PAL */
632 if (palcode >= 0x80 && palcode < 0xC0) {
633 /* Unprivileged PAL call */
634 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
635#if !defined (CONFIG_USER_ONLY)
636 } else if (palcode < 0x40) {
637 /* Privileged PAL code */
638 if (ctx->mem_idx & 1)
639 goto invalid_opc;
640 else
641 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
642#endif
643 } else {
644 /* Invalid PAL call */
645 goto invalid_opc;
646 }
647 ret = 3;
648 break;
649 case 0x01:
650 /* OPC01 */
651 goto invalid_opc;
652 case 0x02:
653 /* OPC02 */
654 goto invalid_opc;
655 case 0x03:
656 /* OPC03 */
657 goto invalid_opc;
658 case 0x04:
659 /* OPC04 */
660 goto invalid_opc;
661 case 0x05:
662 /* OPC05 */
663 goto invalid_opc;
664 case 0x06:
665 /* OPC06 */
666 goto invalid_opc;
667 case 0x07:
668 /* OPC07 */
669 goto invalid_opc;
670 case 0x08:
671 /* LDA */
1ef4ef4e 672 if (likely(ra != 31)) {
496cb5b9 673 if (rb != 31)
3761035f
AJ		 674 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
675 else
676 tcg_gen_movi_i64(cpu_ir[ra], disp16);
496cb5b9 677 }
4c9649a9
JM		 678 break;
679 case 0x09:
680 /* LDAH */
1ef4ef4e 681 if (likely(ra != 31)) {
496cb5b9 682 if (rb != 31)
3761035f
AJ		 683 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
684 else
685 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
496cb5b9 686 }
4c9649a9
JM		 687 break;
688 case 0x0A:
689 /* LDBU */
690 if (!(ctx->amask & AMASK_BWX))
691 goto invalid_opc;
692 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
693 break;
694 case 0x0B:
695 /* LDQ_U */
696 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
697 break;
698 case 0x0C:
699 /* LDWU */
700 if (!(ctx->amask & AMASK_BWX))
701 goto invalid_opc;
702 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
703 break;
704 case 0x0D:
705 /* STW */
706 if (!(ctx->amask & AMASK_BWX))
707 goto invalid_opc;
708 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
709 break;
710 case 0x0E:
711 /* STB */
712 if (!(ctx->amask & AMASK_BWX))
713 goto invalid_opc;
714 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
715 break;
716 case 0x0F:
717 /* STQ_U */
718 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
719 break;
720 case 0x10:
721 switch (fn7) {
722 case 0x00:
723 /* ADDL */
30c7183b
AJ		 724 if (likely(rc != 31)) {
725 if (ra != 31) {
726 if (islit) {
727 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
728 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
729 } else if (rb != 31) {
730 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
731 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
732 } else
733 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[ra]);
734 } else {
735 if (islit)
736 tcg_gen_movi_i64(cpu_ir[rc], (int32_t)lit);
737 else if (rb != 31)
738 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
739 else
740 tcg_gen_movi_i64(cpu_ir[rc], 0);
741 }
742 }
4c9649a9
JM		 743 break;
744 case 0x02:
745 /* S4ADDL */
30c7183b
AJ		 746 if (likely(rc != 31)) {
747 if (ra != 31) {
748 if (islit || rb != 31) {
749 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
750 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
751 if (islit)
752 tcg_gen_addi_i64(tmp, tmp, lit);
753 else
754 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
755 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
756 tcg_temp_free(tmp);
757 } else {
758 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
759 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
760 }
761 } else {
762 if (islit)
763 tcg_gen_movi_i64(cpu_ir[rc], lit);
764 else if (rb != 31)
765 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
766 else
767 tcg_gen_movi_i64(cpu_ir[rc], 0);
768 }
769 }
4c9649a9
JM		 770 break;
771 case 0x09:
772 /* SUBL */
30c7183b
AJ		 773 if (likely(rc != 31)) {
774 if (ra != 31) {
775 if (islit) {
776 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
777 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
778 } else if (rb != 31) {
779 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
780 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
781 } else
782 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[ra]);
783 } else {
784 if (islit)
785 tcg_gen_movi_i64(cpu_ir[rc], -lit);
786 else if (rb != 31) {
787 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
788 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
789 } else
790 tcg_gen_movi_i64(cpu_ir[rc], 0);
791 }
792 }
4c9649a9
JM		 793 break;
794 case 0x0B:
795 /* S4SUBL */
30c7183b
AJ		 796 if (likely(rc != 31)) {
797 if (ra != 31) {
798 if (islit || rb != 31) {
799 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
800 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
801 if (islit)
802 tcg_gen_subi_i64(tmp, tmp, lit);
803 else
804 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
805 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
806 tcg_temp_free(tmp);
807 } else {
808 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
809 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
810 }
811 } else {
812 if (islit)
813 tcg_gen_movi_i64(cpu_ir[rc], -lit);
814 else if (rb != 31) {
815 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
816 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
817 } else
818 tcg_gen_movi_i64(cpu_ir[rc], 0);
819 }
820 }
4c9649a9
JM		 821 break;
822 case 0x0F:
823 /* CMPBGE */
824 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
825 break;
826 case 0x12:
827 /* S8ADDL */
30c7183b
AJ		 828 if (likely(rc != 31)) {
829 if (ra != 31) {
830 if (islit || rb != 31) {
831 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
832 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
833 if (islit)
834 tcg_gen_addi_i64(tmp, tmp, lit);
835 else
836 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
837 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
838 tcg_temp_free(tmp);
839 } else {
840 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
841 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
842 }
843 } else {
844 if (islit)
845 tcg_gen_movi_i64(cpu_ir[rc], lit);
846 else if (rb != 31)
847 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
848 else
849 tcg_gen_movi_i64(cpu_ir[rc], 0);
850 }
851 }
4c9649a9
JM		 852 break;
853 case 0x1B:
854 /* S8SUBL */
30c7183b
AJ		 855 if (likely(rc != 31)) {
856 if (ra != 31) {
857 if (islit || rb != 31) {
858 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
859 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
860 if (islit)
861 tcg_gen_subi_i64(tmp, tmp, lit);
862 else
863 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
864 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
865 tcg_temp_free(tmp);
866 } else {
867 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
868 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
869 }
870 } else {
871 if (islit)
872 tcg_gen_movi_i64(cpu_ir[rc], -lit);
873 else if (rb != 31) {
874 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
875 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
876 } else
877 tcg_gen_movi_i64(cpu_ir[rc], 0);
878 }
879 }
4c9649a9
JM		 880 break;
881 case 0x1D:
882 /* CMPULT */
01ff9cc8 883 gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
4c9649a9
JM		 884 break;
885 case 0x20:
886 /* ADDQ */
30c7183b
AJ		 887 if (likely(rc != 31)) {
888 if (ra != 31) {
889 if (islit)
890 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
891 else if (rb != 31)
892 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
893 else
894 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
895 } else {
896 if (islit)
897 tcg_gen_movi_i64(cpu_ir[rc], lit);
898 else if (rb != 31)
899 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
900 else
901 tcg_gen_movi_i64(cpu_ir[rc], 0);
902 }
903 }
4c9649a9
JM		 904 break;
905 case 0x22:
906 /* S4ADDQ */
30c7183b
AJ		 907 if (likely(rc != 31)) {
908 if (ra != 31) {
909 if (islit || rb != 31) {
910 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
911 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
912 if (islit)
913 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
914 else
915 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
916 tcg_temp_free(tmp);
917 } else
918 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
919 } else {
920 if (islit)
921 tcg_gen_movi_i64(cpu_ir[rc], lit);
922 else if (rb != 31)
923 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
924 else
925 tcg_gen_movi_i64(cpu_ir[rc], 0);
926 }
927 }
4c9649a9
JM		 928 break;
929 case 0x29:
930 /* SUBQ */
30c7183b
AJ		 931 if (likely(rc != 31)) {
932 if (ra != 31) {
933 if (islit)
934 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
935 else if (rb != 31)
936 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
937 else
938 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
939 } else {
940 if (islit)
941 tcg_gen_movi_i64(cpu_ir[rc], -lit);
942 else if (rb != 31)
943 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
944 else
945 tcg_gen_movi_i64(cpu_ir[rc], 0);
946 }
947 }
4c9649a9
JM		 948 break;
949 case 0x2B:
950 /* S4SUBQ */
30c7183b
AJ		 951 if (likely(rc != 31)) {
952 if (ra != 31) {
953 if (islit || rb != 31) {
954 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
955 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
956 if (islit)
957 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
958 else
959 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
960 tcg_temp_free(tmp);
961 } else
962 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
963 } else {
964 if (islit)
965 tcg_gen_movi_i64(cpu_ir[rc], -lit);
966 else if (rb != 31)
967 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
968 else
969 tcg_gen_movi_i64(cpu_ir[rc], 0);
970 }
971 }
4c9649a9
JM		 972 break;
973 case 0x2D:
974 /* CMPEQ */
01ff9cc8 975 gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
4c9649a9
JM		 976 break;
977 case 0x32:
978 /* S8ADDQ */
30c7183b
AJ		 979 if (likely(rc != 31)) {
980 if (ra != 31) {
981 if (islit || rb != 31) {
982 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
983 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
984 if (islit)
985 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
986 else
987 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
988 tcg_temp_free(tmp);
989 } else
990 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
991 } else {
992 if (islit)
993 tcg_gen_movi_i64(cpu_ir[rc], lit);
994 else if (rb != 31)
995 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
996 else
997 tcg_gen_movi_i64(cpu_ir[rc], 0);
998 }
999 }
4c9649a9
JM		 1000 break;
1001 case 0x3B:
1002 /* S8SUBQ */
30c7183b
AJ		 1003 if (likely(rc != 31)) {
1004 if (ra != 31) {
1005 if (islit || rb != 31) {
1006 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1007 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
1008 if (islit)
1009 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
1010 else
1011 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
1012 tcg_temp_free(tmp);
1013 } else
1014 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
1015 } else {
1016 if (islit)
1017 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1018 else if (rb != 31)
1019 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1020 else
1021 tcg_gen_movi_i64(cpu_ir[rc], 0);
1022 }
1023 }
4c9649a9
JM		 1024 break;
1025 case 0x3D:
1026 /* CMPULE */
01ff9cc8 1027 gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
4c9649a9
JM		 1028 break;
1029 case 0x40:
1030 /* ADDL/V */
1031 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
1032 break;
1033 case 0x49:
1034 /* SUBL/V */
1035 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
1036 break;
1037 case 0x4D:
1038 /* CMPLT */
01ff9cc8 1039 gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
4c9649a9
JM		 1040 break;
1041 case 0x60:
1042 /* ADDQ/V */
1043 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
1044 break;
1045 case 0x69:
1046 /* SUBQ/V */
1047 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
1048 break;
1049 case 0x6D:
1050 /* CMPLE */
01ff9cc8 1051 gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
4c9649a9
JM		 1052 break;
1053 default:
1054 goto invalid_opc;
1055 }
1056 break;
1057 case 0x11:
1058 switch (fn7) {
1059 case 0x00:
1060 /* AND */
30c7183b
AJ		 1061 if (likely(rc != 31)) {
1062 if (ra == 31 || (rb == 31 && !islit))
1063 tcg_gen_movi_i64(cpu_ir[rc], 0);
1064 else if (islit)
1065 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1066 else
1067 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1068 }
4c9649a9
JM		 1069 break;
1070 case 0x08:
1071 /* BIC */
30c7183b
AJ		 1072 if (likely(rc != 31)) {
1073 if (ra != 31) {
1074 if (islit)
1075 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1076 else if (rb != 31) {
1077 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1078 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1079 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1080 tcg_temp_free(tmp);
1081 } else
1082 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1083 } else
1084 tcg_gen_movi_i64(cpu_ir[rc], 0);
1085 }
4c9649a9
JM		 1086 break;
1087 case 0x14:
1088 /* CMOVLBS */
9c29504e 1089 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
4c9649a9
JM		 1090 break;
1091 case 0x16:
1092 /* CMOVLBC */
9c29504e 1093 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1);
4c9649a9
JM		 1094 break;
1095 case 0x20:
1096 /* BIS */
30c7183b
AJ		 1097 if (likely(rc != 31)) {
1098 if (ra != 31) {
1099 if (islit)
1100 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1101 else if (rb != 31)
1102 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1103 else
1104 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
4c9649a9 1105 } else {
30c7183b
AJ		 1106 if (islit)
1107 tcg_gen_movi_i64(cpu_ir[rc], lit);
1108 else if (rb != 31)
1109 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1110 else
1111 tcg_gen_movi_i64(cpu_ir[rc], 0);
4c9649a9 1112 }
4c9649a9
JM		 1113 }
1114 break;
1115 case 0x24:
1116 /* CMOVEQ */
9c29504e 1117 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1118 break;
1119 case 0x26:
1120 /* CMOVNE */
9c29504e 1121 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1122 break;
1123 case 0x28:
1124 /* ORNOT */
30c7183b
AJ		 1125 if (likely(rc != 31)) {
1126 if (rb == 31 && !islit)
1127 tcg_gen_movi_i64(cpu_ir[rc], ~0);
1128 else if (ra != 31) {
1129 if (islit)
1130 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1131 else {
1132 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1133 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1134 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1135 tcg_temp_free(tmp);
1136 }
1137 } else {
1138 if (islit)
1139 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1140 else
1141 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1142 }
1143 }
4c9649a9
JM		 1144 break;
1145 case 0x40:
1146 /* XOR */
30c7183b
AJ		 1147 if (likely(rc != 31)) {
1148 if (ra != 31) {
1149 if (islit)
1150 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1151 else if (rb != 31)
1152 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1153 else
1154 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1155 } else {
1156 if (islit)
1157 tcg_gen_movi_i64(cpu_ir[rc], lit);
1158 else if (rb != 31)
1159 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1160 else
1161 tcg_gen_movi_i64(cpu_ir[rc], 0);
1162 }
1163 }
4c9649a9
JM		 1164 break;
1165 case 0x44:
1166 /* CMOVLT */
9c29504e 1167 gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1168 break;
1169 case 0x46:
1170 /* CMOVGE */
9c29504e 1171 gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1172 break;
1173 case 0x48:
1174 /* EQV */
30c7183b
AJ		 1175 if (likely(rc != 31)) {
1176 if (ra != 31) {
1177 if (islit)
1178 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1179 else if (rb != 31) {
1180 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1181 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1182 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1183 tcg_temp_free(tmp);
1184 } else
1185 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1186 } else {
1187 if (islit)
1188 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1189 else if (rb != 31)
1190 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1191 else
1192 tcg_gen_movi_i64(cpu_ir[rc], ~0);
1193 }
1194 }
4c9649a9
JM		 1195 break;
1196 case 0x61:
1197 /* AMASK */
ae8ecd42
AJ		 1198 if (likely(rc != 31)) {
1199 if (islit)
1200 tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit));
1201 else if (rb != 31)
1202 tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]);
1203 else
1204 tcg_gen_movi_i64(cpu_ir[rc], 0);
1205 }
4c9649a9
JM		 1206 break;
1207 case 0x64:
1208 /* CMOVLE */
9c29504e 1209 gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1210 break;
1211 case 0x66:
1212 /* CMOVGT */
9c29504e 1213 gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1214 break;
1215 case 0x6C:
1216 /* IMPLVER */
3761035f 1217 if (rc != 31)
6ad02592 1218 tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]);
4c9649a9
JM		 1219 break;
1220 default:
1221 goto invalid_opc;
1222 }
1223 break;
1224 case 0x12:
1225 switch (fn7) {
1226 case 0x02:
1227 /* MSKBL */
b3249f63 1228 gen_byte_manipulation(helper_mskbl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1229 break;
1230 case 0x06:
1231 /* EXTBL */
b3249f63 1232 gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1233 break;
1234 case 0x0B:
1235 /* INSBL */
b3249f63 1236 gen_byte_manipulation(helper_insbl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1237 break;
1238 case 0x12:
1239 /* MSKWL */
b3249f63 1240 gen_byte_manipulation(helper_mskwl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1241 break;
1242 case 0x16:
1243 /* EXTWL */
b3249f63 1244 gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1245 break;
1246 case 0x1B:
1247 /* INSWL */
b3249f63 1248 gen_byte_manipulation(helper_inswl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1249 break;
1250 case 0x22:
1251 /* MSKLL */
b3249f63 1252 gen_byte_manipulation(helper_mskll, ra, rb, rc, islit, lit);
4c9649a9
JM		 1253 break;
1254 case 0x26:
1255 /* EXTLL */
b3249f63 1256 gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1257 break;
1258 case 0x2B:
1259 /* INSLL */
b3249f63 1260 gen_byte_manipulation(helper_insll, ra, rb, rc, islit, lit);
4c9649a9
JM		 1261 break;
1262 case 0x30:
1263 /* ZAP */
b3249f63 1264 gen_byte_manipulation(helper_zap, ra, rb, rc, islit, lit);
4c9649a9
JM		 1265 break;
1266 case 0x31:
1267 /* ZAPNOT */
b3249f63 1268 gen_byte_manipulation(helper_zapnot, ra, rb, rc, islit, lit);
4c9649a9
JM		 1269 break;
1270 case 0x32:
1271 /* MSKQL */
b3249f63 1272 gen_byte_manipulation(helper_mskql, ra, rb, rc, islit, lit);
4c9649a9
JM		 1273 break;
1274 case 0x34:
1275 /* SRL */
30c7183b
AJ		 1276 if (likely(rc != 31)) {
1277 if (ra != 31) {
1278 if (islit)
1279 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1280 else if (rb != 31) {
1281 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1282 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1283 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
1284 tcg_temp_free(shift);
1285 } else
1286 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1287 } else
1288 tcg_gen_movi_i64(cpu_ir[rc], 0);
1289 }
4c9649a9
JM		 1290 break;
1291 case 0x36:
1292 /* EXTQL */
b3249f63 1293 gen_ext_l(NULL, ra, rb, rc, islit, lit);
4c9649a9
JM		 1294 break;
1295 case 0x39:
1296 /* SLL */
30c7183b
AJ		 1297 if (likely(rc != 31)) {
1298 if (ra != 31) {
1299 if (islit)
1300 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1301 else if (rb != 31) {
1302 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1303 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1304 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
1305 tcg_temp_free(shift);
1306 } else
1307 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1308 } else
1309 tcg_gen_movi_i64(cpu_ir[rc], 0);
1310 }
4c9649a9
JM		 1311 break;
1312 case 0x3B:
1313 /* INSQL */
b3249f63 1314 gen_byte_manipulation(helper_insql, ra, rb, rc, islit, lit);
4c9649a9
JM		 1315 break;
1316 case 0x3C:
1317 /* SRA */
30c7183b
AJ		 1318 if (likely(rc != 31)) {
1319 if (ra != 31) {
1320 if (islit)
1321 tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1322 else if (rb != 31) {
1323 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1324 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1325 tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
1326 tcg_temp_free(shift);
1327 } else
1328 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1329 } else
1330 tcg_gen_movi_i64(cpu_ir[rc], 0);
1331 }
4c9649a9
JM		 1332 break;
1333 case 0x52:
1334 /* MSKWH */
b3249f63 1335 gen_byte_manipulation(helper_mskwh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1336 break;
1337 case 0x57:
1338 /* INSWH */
b3249f63 1339 gen_byte_manipulation(helper_inswh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1340 break;
1341 case 0x5A:
1342 /* EXTWH */
b3249f63 1343 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1344 break;
1345 case 0x62:
1346 /* MSKLH */
b3249f63 1347 gen_byte_manipulation(helper_msklh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1348 break;
1349 case 0x67:
1350 /* INSLH */
b3249f63 1351 gen_byte_manipulation(helper_inslh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1352 break;
1353 case 0x6A:
1354 /* EXTLH */
b3249f63 1355 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1356 break;
1357 case 0x72:
1358 /* MSKQH */
b3249f63 1359 gen_byte_manipulation(helper_mskqh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1360 break;
1361 case 0x77:
1362 /* INSQH */
b3249f63 1363 gen_byte_manipulation(helper_insqh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1364 break;
1365 case 0x7A:
1366 /* EXTQH */
b3249f63 1367 gen_ext_h(NULL, ra, rb, rc, islit, lit);
4c9649a9
JM		 1368 break;
1369 default:
1370 goto invalid_opc;
1371 }
1372 break;
1373 case 0x13:
1374 switch (fn7) {
1375 case 0x00:
1376 /* MULL */
30c7183b
AJ		 1377 if (likely(rc != 31)) {
1378 if (ra == 31 || (rb == 31 && !islit))
1379 tcg_gen_movi_i64(cpu_ir[rc], 0);
1380 else {
1381 if (islit)
1382 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1383 else
1384 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1385 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1386 }
1387 }
4c9649a9
JM		 1388 break;
1389 case 0x20:
1390 /* MULQ */
30c7183b
AJ		 1391 if (likely(rc != 31)) {
1392 if (ra == 31 || (rb == 31 && !islit))
1393 tcg_gen_movi_i64(cpu_ir[rc], 0);
1394 else if (islit)
1395 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1396 else
1397 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1398 }
4c9649a9
JM		 1399 break;
1400 case 0x30:
1401 /* UMULH */
1402 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
1403 break;
1404 case 0x40:
1405 /* MULL/V */
1406 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
1407 break;
1408 case 0x60:
1409 /* MULQ/V */
1410 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
1411 break;
1412 default:
1413 goto invalid_opc;
1414 }
1415 break;
1416 case 0x14:
1417 switch (fpfn) { /* f11 & 0x3F */
1418 case 0x04:
1419 /* ITOFS */
1420 if (!(ctx->amask & AMASK_FIX))
1421 goto invalid_opc;
1422 gen_itf(ctx, &gen_op_itofs, ra, rc);
1423 break;
1424 case 0x0A:
1425 /* SQRTF */
1426 if (!(ctx->amask & AMASK_FIX))
1427 goto invalid_opc;
1428 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
1429 break;
1430 case 0x0B:
1431 /* SQRTS */
1432 if (!(ctx->amask & AMASK_FIX))
1433 goto invalid_opc;
1434 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
1435 break;
1436 case 0x14:
1437 /* ITOFF */
1438 if (!(ctx->amask & AMASK_FIX))
1439 goto invalid_opc;
1440#if 0 // TODO
1441 gen_itf(ctx, &gen_op_itoff, ra, rc);
1442#else
1443 goto invalid_opc;
1444#endif
1445 break;
1446 case 0x24:
1447 /* ITOFT */
1448 if (!(ctx->amask & AMASK_FIX))
1449 goto invalid_opc;
1450 gen_itf(ctx, &gen_op_itoft, ra, rc);
1451 break;
1452 case 0x2A:
1453 /* SQRTG */
1454 if (!(ctx->amask & AMASK_FIX))
1455 goto invalid_opc;
1456 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1457 break;
1458 case 0x02B:
1459 /* SQRTT */
1460 if (!(ctx->amask & AMASK_FIX))
1461 goto invalid_opc;
1462 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1463 break;
1464 default:
1465 goto invalid_opc;
1466 }
1467 break;
1468 case 0x15:
1469 /* VAX floating point */
1470 /* XXX: rounding mode and trap are ignored (!) */
1471 switch (fpfn) { /* f11 & 0x3F */
1472 case 0x00:
1473 /* ADDF */
1474 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1475 break;
1476 case 0x01:
1477 /* SUBF */
1478 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1479 break;
1480 case 0x02:
1481 /* MULF */
1482 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1483 break;
1484 case 0x03:
1485 /* DIVF */
1486 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1487 break;
1488 case 0x1E:
1489 /* CVTDG */
1490#if 0 // TODO
1491 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1492#else
1493 goto invalid_opc;
1494#endif
1495 break;
1496 case 0x20:
1497 /* ADDG */
1498 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1499 break;
1500 case 0x21:
1501 /* SUBG */
1502 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1503 break;
1504 case 0x22:
1505 /* MULG */
1506 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1507 break;
1508 case 0x23:
1509 /* DIVG */
1510 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1511 break;
1512 case 0x25:
1513 /* CMPGEQ */
1514 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1515 break;
1516 case 0x26:
1517 /* CMPGLT */
1518 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1519 break;
1520 case 0x27:
1521 /* CMPGLE */
1522 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1523 break;
1524 case 0x2C:
1525 /* CVTGF */
1526 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1527 break;
1528 case 0x2D:
1529 /* CVTGD */
1530#if 0 // TODO
1531 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1532#else
1533 goto invalid_opc;
1534#endif
1535 break;
1536 case 0x2F:
1537 /* CVTGQ */
1538 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1539 break;
1540 case 0x3C:
1541 /* CVTQF */
1542 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1543 break;
1544 case 0x3E:
1545 /* CVTQG */
1546 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1547 break;
1548 default:
1549 goto invalid_opc;
1550 }
1551 break;
1552 case 0x16:
1553 /* IEEE floating-point */
1554 /* XXX: rounding mode and traps are ignored (!) */
1555 switch (fpfn) { /* f11 & 0x3F */
1556 case 0x00:
1557 /* ADDS */
1558 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1559 break;
1560 case 0x01:
1561 /* SUBS */
1562 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1563 break;
1564 case 0x02:
1565 /* MULS */
1566 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1567 break;
1568 case 0x03:
1569 /* DIVS */
1570 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1571 break;
1572 case 0x20:
1573 /* ADDT */
1574 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1575 break;
1576 case 0x21:
1577 /* SUBT */
1578 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1579 break;
1580 case 0x22:
1581 /* MULT */
1582 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1583 break;
1584 case 0x23:
1585 /* DIVT */
1586 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1587 break;
1588 case 0x24:
1589 /* CMPTUN */
1590 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1591 break;
1592 case 0x25:
1593 /* CMPTEQ */
1594 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1595 break;
1596 case 0x26:
1597 /* CMPTLT */
1598 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1599 break;
1600 case 0x27:
1601 /* CMPTLE */
1602 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1603 break;
1604 case 0x2C:
1605 /* XXX: incorrect */
1606 if (fn11 == 0x2AC) {
1607 /* CVTST */
1608 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1609 } else {
1610 /* CVTTS */
1611 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1612 }
1613 break;
1614 case 0x2F:
1615 /* CVTTQ */
1616 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1617 break;
1618 case 0x3C:
1619 /* CVTQS */
1620 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1621 break;
1622 case 0x3E:
1623 /* CVTQT */
1624 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1625 break;
1626 default:
1627 goto invalid_opc;
1628 }
1629 break;
1630 case 0x17:
1631 switch (fn11) {
1632 case 0x010:
1633 /* CVTLQ */
1634 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1635 break;
1636 case 0x020:
1637 /* CPYS */
1638 if (ra == rb) {
1639 if (ra == 31 && rc == 31) {
1640 /* FNOP */
1641 gen_op_nop();
1642 } else {
1643 /* FMOV */
1644 gen_load_fir(ctx, rb, 0);
1645 gen_store_fir(ctx, rc, 0);
1646 }
1647 } else {
1648 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1649 }
1650 break;
1651 case 0x021:
1652 /* CPYSN */
1653 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1654 break;
1655 case 0x022:
1656 /* CPYSE */
1657 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1658 break;
1659 case 0x024:
1660 /* MT_FPCR */
1661 gen_load_fir(ctx, ra, 0);
1662 gen_op_store_fpcr();
1663 break;
1664 case 0x025:
1665 /* MF_FPCR */
1666 gen_op_load_fpcr();
1667 gen_store_fir(ctx, ra, 0);
1668 break;
1669 case 0x02A:
1670 /* FCMOVEQ */
1671 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1672 break;
1673 case 0x02B:
1674 /* FCMOVNE */
1675 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1676 break;
1677 case 0x02C:
1678 /* FCMOVLT */
1679 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1680 break;
1681 case 0x02D:
1682 /* FCMOVGE */
1683 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1684 break;
1685 case 0x02E:
1686 /* FCMOVLE */
1687 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1688 break;
1689 case 0x02F:
1690 /* FCMOVGT */
1691 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1692 break;
1693 case 0x030:
1694 /* CVTQL */
1695 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1696 break;
1697 case 0x130:
1698 /* CVTQL/V */
1699 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1700 break;
1701 case 0x530:
1702 /* CVTQL/SV */
1703 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1704 break;
1705 default:
1706 goto invalid_opc;
1707 }
1708 break;
1709 case 0x18:
1710 switch ((uint16_t)disp16) {
1711 case 0x0000:
1712 /* TRAPB */
1713 /* No-op. Just exit from the current tb */
1714 ret = 2;
1715 break;
1716 case 0x0400:
1717 /* EXCB */
1718 /* No-op. Just exit from the current tb */
1719 ret = 2;
1720 break;
1721 case 0x4000:
1722 /* MB */
1723 /* No-op */
1724 break;
1725 case 0x4400:
1726 /* WMB */
1727 /* No-op */
1728 break;
1729 case 0x8000:
1730 /* FETCH */
1731 /* No-op */
1732 break;
1733 case 0xA000:
1734 /* FETCH_M */
1735 /* No-op */
1736 break;
1737 case 0xC000:
1738 /* RPCC */
3761035f 1739 if (ra != 31)
6ad02592 1740 tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]);
4c9649a9
JM		 1741 break;
1742 case 0xE000:
1743 /* RC */
3761035f 1744 if (ra != 31)
6ad02592 1745 tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]);
4c9649a9
JM		 1746 break;
1747 case 0xE800:
1748 /* ECB */
1749 /* XXX: TODO: evict tb cache at address rb */
1750#if 0
1751 ret = 2;
1752#else
1753 goto invalid_opc;
1754#endif
1755 break;
1756 case 0xF000:
1757 /* RS */
3761035f 1758 if (ra != 31)
6ad02592 1759 tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]);
4c9649a9
JM		 1760 break;
1761 case 0xF800:
1762 /* WH64 */
1763 /* No-op */
1764 break;
1765 default:
1766 goto invalid_opc;
1767 }
1768 break;
1769 case 0x19:
1770 /* HW_MFPR (PALcode) */
1771#if defined (CONFIG_USER_ONLY)
1772 goto invalid_opc;
1773#else
1774 if (!ctx->pal_mode)
1775 goto invalid_opc;
1776 gen_op_mfpr(insn & 0xFF);
3761035f
AJ		 1777 if (ra != 31)
1778 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 1779 break;
1780#endif
1781 case 0x1A:
3761035f
AJ		 1782 if (ra != 31)
1783 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1784 if (rb != 31)
1785 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1786 else
1787 tcg_gen_movi_i64(cpu_pc, 0);
4c9649a9
JM		 1788 /* Those four jumps only differ by the branch prediction hint */
1789 switch (fn2) {
1790 case 0x0:
1791 /* JMP */
1792 break;
1793 case 0x1:
1794 /* JSR */
1795 break;
1796 case 0x2:
1797 /* RET */
1798 break;
1799 case 0x3:
1800 /* JSR_COROUTINE */
1801 break;
1802 }
1803 ret = 1;
1804 break;
1805 case 0x1B:
1806 /* HW_LD (PALcode) */
1807#if defined (CONFIG_USER_ONLY)
1808 goto invalid_opc;
1809#else
1810 if (!ctx->pal_mode)
1811 goto invalid_opc;
3761035f
AJ		 1812 if (rb != 31)
1813 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1814 else
1815 tcg_gen_movi_i64(cpu_T[0], 0);
1816 tcg_gen_movi_i64(cpu_T[1], disp12);
4f821e17 1817 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
4c9649a9
JM		 1818 switch ((insn >> 12) & 0xF) {
1819 case 0x0:
1820 /* Longword physical access */
1821 gen_op_ldl_raw();
1822 break;
1823 case 0x1:
1824 /* Quadword physical access */
1825 gen_op_ldq_raw();
1826 break;
1827 case 0x2:
1828 /* Longword physical access with lock */
1829 gen_op_ldl_l_raw();
1830 break;
1831 case 0x3:
1832 /* Quadword physical access with lock */
1833 gen_op_ldq_l_raw();
1834 break;
1835 case 0x4:
1836 /* Longword virtual PTE fetch */
1837 gen_op_ldl_kernel();
1838 break;
1839 case 0x5:
1840 /* Quadword virtual PTE fetch */
1841 gen_op_ldq_kernel();
1842 break;
1843 case 0x6:
1844 /* Invalid */
1845 goto invalid_opc;
1846 case 0x7:
1847 /* Invalid */
1848 goto invalid_opc;
1849 case 0x8:
1850 /* Longword virtual access */
1851 gen_op_ld_phys_to_virt();
1852 gen_op_ldl_raw();
1853 break;
1854 case 0x9:
1855 /* Quadword virtual access */
1856 gen_op_ld_phys_to_virt();
1857 gen_op_ldq_raw();
1858 break;
1859 case 0xA:
1860 /* Longword virtual access with protection check */
1861 gen_ldl(ctx);
1862 break;
1863 case 0xB:
1864 /* Quadword virtual access with protection check */
1865 gen_ldq(ctx);
1866 break;
1867 case 0xC:
1868 /* Longword virtual access with altenate access mode */
1869 gen_op_set_alt_mode();
1870 gen_op_ld_phys_to_virt();
1871 gen_op_ldl_raw();
1872 gen_op_restore_mode();
1873 break;
1874 case 0xD:
1875 /* Quadword virtual access with altenate access mode */
1876 gen_op_set_alt_mode();
1877 gen_op_ld_phys_to_virt();
1878 gen_op_ldq_raw();
1879 gen_op_restore_mode();
1880 break;
1881 case 0xE:
1882 /* Longword virtual access with alternate access mode and
1883 * protection checks
1884 */
1885 gen_op_set_alt_mode();
1886 gen_op_ldl_data();
1887 gen_op_restore_mode();
1888 break;
1889 case 0xF:
1890 /* Quadword virtual access with alternate access mode and
1891 * protection checks
1892 */
1893 gen_op_set_alt_mode();
1894 gen_op_ldq_data();
1895 gen_op_restore_mode();
1896 break;
1897 }
3761035f
AJ		 1898 if (ra != 31)
1899 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
4c9649a9
JM		 1900 break;
1901#endif
1902 case 0x1C:
1903 switch (fn7) {
1904 case 0x00:
1905 /* SEXTB */
1906 if (!(ctx->amask & AMASK_BWX))
1907 goto invalid_opc;
ae8ecd42
AJ		 1908 if (likely(rc != 31)) {
1909 if (islit)
1910 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
1911 else if (rb != 31)
1912 tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
1913 else
1914 tcg_gen_movi_i64(cpu_ir[rc], 0);
1915 }
4c9649a9
JM		 1916 break;
1917 case 0x01:
1918 /* SEXTW */
1919 if (!(ctx->amask & AMASK_BWX))
1920 goto invalid_opc;
ae8ecd42
AJ		 1921 if (likely(rc != 31)) {
1922 if (islit)
1923 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
1924 else if (rb != 31)
1925 tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
1926 else
1927 tcg_gen_movi_i64(cpu_ir[rc], 0);
1928 }
4c9649a9
JM		 1929 break;
1930 case 0x30:
1931 /* CTPOP */
1932 if (!(ctx->amask & AMASK_CIX))
1933 goto invalid_opc;
ae8ecd42
AJ		 1934 if (likely(rc != 31)) {
1935 if (islit)
1936 tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
1937 else if (rb != 31)
1938 tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]);
1939 else
1940 tcg_gen_movi_i64(cpu_ir[rc], 0);
1941 }
4c9649a9
JM		 1942 break;
1943 case 0x31:
1944 /* PERR */
1945 if (!(ctx->amask & AMASK_MVI))
1946 goto invalid_opc;
1947 /* XXX: TODO */
1948 goto invalid_opc;
1949 break;
1950 case 0x32:
1951 /* CTLZ */
1952 if (!(ctx->amask & AMASK_CIX))
1953 goto invalid_opc;
ae8ecd42
AJ		 1954 if (likely(rc != 31)) {
1955 if (islit)
1956 tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
1957 else if (rb != 31)
1958 tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]);
1959 else
1960 tcg_gen_movi_i64(cpu_ir[rc], 0);
1961 }
4c9649a9
JM		 1962 break;
1963 case 0x33:
1964 /* CTTZ */
1965 if (!(ctx->amask & AMASK_CIX))
1966 goto invalid_opc;
ae8ecd42
AJ		 1967 if (likely(rc != 31)) {
1968 if (islit)
1969 tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
1970 else if (rb != 31)
1971 tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]);
1972 else
1973 tcg_gen_movi_i64(cpu_ir[rc], 0);
1974 }
4c9649a9
JM		 1975 break;
1976 case 0x34:
1977 /* UNPKBW */
1978 if (!(ctx->amask & AMASK_MVI))
1979 goto invalid_opc;
1980 /* XXX: TODO */
1981 goto invalid_opc;
1982 break;
1983 case 0x35:
1984 /* UNPKWL */
1985 if (!(ctx->amask & AMASK_MVI))
1986 goto invalid_opc;
1987 /* XXX: TODO */
1988 goto invalid_opc;
1989 break;
1990 case 0x36:
1991 /* PKWB */
1992 if (!(ctx->amask & AMASK_MVI))
1993 goto invalid_opc;
1994 /* XXX: TODO */
1995 goto invalid_opc;
1996 break;
1997 case 0x37:
1998 /* PKLB */
1999 if (!(ctx->amask & AMASK_MVI))
2000 goto invalid_opc;
2001 /* XXX: TODO */
2002 goto invalid_opc;
2003 break;
2004 case 0x38:
2005 /* MINSB8 */
2006 if (!(ctx->amask & AMASK_MVI))
2007 goto invalid_opc;
2008 /* XXX: TODO */
2009 goto invalid_opc;
2010 break;
2011 case 0x39:
2012 /* MINSW4 */
2013 if (!(ctx->amask & AMASK_MVI))
2014 goto invalid_opc;
2015 /* XXX: TODO */
2016 goto invalid_opc;
2017 break;
2018 case 0x3A:
2019 /* MINUB8 */
2020 if (!(ctx->amask & AMASK_MVI))
2021 goto invalid_opc;
2022 /* XXX: TODO */
2023 goto invalid_opc;
2024 break;
2025 case 0x3B:
2026 /* MINUW4 */
2027 if (!(ctx->amask & AMASK_MVI))
2028 goto invalid_opc;
2029 /* XXX: TODO */
2030 goto invalid_opc;
2031 break;
2032 case 0x3C:
2033 /* MAXUB8 */
2034 if (!(ctx->amask & AMASK_MVI))
2035 goto invalid_opc;
2036 /* XXX: TODO */
2037 goto invalid_opc;
2038 break;
2039 case 0x3D:
2040 /* MAXUW4 */
2041 if (!(ctx->amask & AMASK_MVI))
2042 goto invalid_opc;
2043 /* XXX: TODO */
2044 goto invalid_opc;
2045 break;
2046 case 0x3E:
2047 /* MAXSB8 */
2048 if (!(ctx->amask & AMASK_MVI))
2049 goto invalid_opc;
2050 /* XXX: TODO */
2051 goto invalid_opc;
2052 break;
2053 case 0x3F:
2054 /* MAXSW4 */
2055 if (!(ctx->amask & AMASK_MVI))
2056 goto invalid_opc;
2057 /* XXX: TODO */
2058 goto invalid_opc;
2059 break;
2060 case 0x70:
2061 /* FTOIT */
2062 if (!(ctx->amask & AMASK_FIX))
2063 goto invalid_opc;
2064 gen_fti(ctx, &gen_op_ftoit, ra, rb);
2065 break;
2066 case 0x78:
2067 /* FTOIS */
2068 if (!(ctx->amask & AMASK_FIX))
2069 goto invalid_opc;
2070 gen_fti(ctx, &gen_op_ftois, ra, rb);
2071 break;
2072 default:
2073 goto invalid_opc;
2074 }
2075 break;
2076 case 0x1D:
2077 /* HW_MTPR (PALcode) */
2078#if defined (CONFIG_USER_ONLY)
2079 goto invalid_opc;
2080#else
2081 if (!ctx->pal_mode)
2082 goto invalid_opc;
3761035f
AJ		 2083 if (ra != 31)
2084 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
2085 else
2086 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 2087 gen_op_mtpr(insn & 0xFF);
2088 ret = 2;
2089 break;
2090#endif
2091 case 0x1E:
2092 /* HW_REI (PALcode) */
2093#if defined (CONFIG_USER_ONLY)
2094 goto invalid_opc;
2095#else
2096 if (!ctx->pal_mode)
2097 goto invalid_opc;
2098 if (rb == 31) {
2099 /* "Old" alpha */
2100 gen_op_hw_rei();
2101 } else {
3761035f
AJ		 2102 if (ra != 31)
2103 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
2104 else
2105 tcg_gen_movi_i64(cpu_T[0], 0);
2106 tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
4f821e17 2107 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
4c9649a9
JM		 2108 gen_op_hw_ret();
2109 }
2110 ret = 2;
2111 break;
2112#endif
2113 case 0x1F:
2114 /* HW_ST (PALcode) */
2115#if defined (CONFIG_USER_ONLY)
2116 goto invalid_opc;
2117#else
2118 if (!ctx->pal_mode)
2119 goto invalid_opc;
3761035f 2120 if (ra != 31)
4f821e17 2121 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
3761035f 2122 else
4f821e17 2123 tcg_gen_movi_i64(cpu_T[0], disp12);
3761035f
AJ		 2124 if (ra != 31)
2125 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
2126 else
2127 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9
JM		 2128 switch ((insn >> 12) & 0xF) {
2129 case 0x0:
2130 /* Longword physical access */
2131 gen_op_stl_raw();
2132 break;
2133 case 0x1:
2134 /* Quadword physical access */
2135 gen_op_stq_raw();
2136 break;
2137 case 0x2:
2138 /* Longword physical access with lock */
2139 gen_op_stl_c_raw();
2140 break;
2141 case 0x3:
2142 /* Quadword physical access with lock */
2143 gen_op_stq_c_raw();
2144 break;
2145 case 0x4:
2146 /* Longword virtual access */
2147 gen_op_st_phys_to_virt();
2148 gen_op_stl_raw();
2149 break;
2150 case 0x5:
2151 /* Quadword virtual access */
2152 gen_op_st_phys_to_virt();
2153 gen_op_stq_raw();
2154 break;
2155 case 0x6:
2156 /* Invalid */
2157 goto invalid_opc;
2158 case 0x7:
2159 /* Invalid */
2160 goto invalid_opc;
2161 case 0x8:
2162 /* Invalid */
2163 goto invalid_opc;
2164 case 0x9:
2165 /* Invalid */
2166 goto invalid_opc;
2167 case 0xA:
2168 /* Invalid */
2169 goto invalid_opc;
2170 case 0xB:
2171 /* Invalid */
2172 goto invalid_opc;
2173 case 0xC:
2174 /* Longword virtual access with alternate access mode */
2175 gen_op_set_alt_mode();
2176 gen_op_st_phys_to_virt();
2177 gen_op_ldl_raw();
2178 gen_op_restore_mode();
2179 break;
2180 case 0xD:
2181 /* Quadword virtual access with alternate access mode */
2182 gen_op_set_alt_mode();
2183 gen_op_st_phys_to_virt();
2184 gen_op_ldq_raw();
2185 gen_op_restore_mode();
2186 break;
2187 case 0xE:
2188 /* Invalid */
2189 goto invalid_opc;
2190 case 0xF:
2191 /* Invalid */
2192 goto invalid_opc;
2193 }
2194 ret = 2;
2195 break;
2196#endif
2197 case 0x20:
2198 /* LDF */
2199#if 0 // TODO
2200 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
2201#else
2202 goto invalid_opc;
2203#endif
2204 break;
2205 case 0x21:
2206 /* LDG */
2207#if 0 // TODO
2208 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
2209#else
2210 goto invalid_opc;
2211#endif
2212 break;
2213 case 0x22:
2214 /* LDS */
2215 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
2216 break;
2217 case 0x23:
2218 /* LDT */
2219 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
2220 break;
2221 case 0x24:
2222 /* STF */
2223#if 0 // TODO
2224 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
2225#else
2226 goto invalid_opc;
2227#endif
2228 break;
2229 case 0x25:
2230 /* STG */
2231#if 0 // TODO
2232 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
2233#else
2234 goto invalid_opc;
2235#endif
2236 break;
2237 case 0x26:
2238 /* STS */
2239 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
2240 break;
2241 case 0x27:
2242 /* STT */
2243 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
2244 break;
2245 case 0x28:
2246 /* LDL */
2247 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
2248 break;
2249 case 0x29:
2250 /* LDQ */
2251 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
2252 break;
2253 case 0x2A:
2254 /* LDL_L */
2255 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
2256 break;
2257 case 0x2B:
2258 /* LDQ_L */
2259 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
2260 break;
2261 case 0x2C:
2262 /* STL */
2263 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
2264 break;
2265 case 0x2D:
2266 /* STQ */
2267 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
2268 break;
2269 case 0x2E:
2270 /* STL_C */
2271 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
2272 break;
2273 case 0x2F:
2274 /* STQ_C */
2275 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
2276 break;
2277 case 0x30:
2278 /* BR */
3761035f
AJ		 2279 if (ra != 31)
2280 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2281 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
4c9649a9
JM		 2282 ret = 1;
2283 break;
2284 case 0x31:
2285 /* FBEQ */
2286 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
2287 ret = 1;
2288 break;
2289 case 0x32:
2290 /* FBLT */
2291 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
2292 ret = 1;
2293 break;
2294 case 0x33:
2295 /* FBLE */
2296 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
2297 ret = 1;
2298 break;
2299 case 0x34:
2300 /* BSR */
3761035f
AJ		 2301 if (ra != 31)
2302 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2303 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
4c9649a9
JM		 2304 ret = 1;
2305 break;
2306 case 0x35:
2307 /* FBNE */
2308 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
2309 ret = 1;
2310 break;
2311 case 0x36:
2312 /* FBGE */
2313 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
2314 ret = 1;
2315 break;
2316 case 0x37:
2317 /* FBGT */
2318 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
2319 ret = 1;
2320 break;
2321 case 0x38:
2322 /* BLBC */
9c29504e 2323 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
4c9649a9
JM		 2324 ret = 1;
2325 break;
2326 case 0x39:
2327 /* BEQ */
9c29504e 2328 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
4c9649a9
JM		 2329 ret = 1;
2330 break;
2331 case 0x3A:
2332 /* BLT */
9c29504e 2333 gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
4c9649a9
JM		 2334 ret = 1;
2335 break;
2336 case 0x3B:
2337 /* BLE */
9c29504e 2338 gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
4c9649a9
JM		 2339 ret = 1;
2340 break;
2341 case 0x3C:
2342 /* BLBS */
9c29504e 2343 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
4c9649a9
JM		 2344 ret = 1;
2345 break;
2346 case 0x3D:
2347 /* BNE */
9c29504e 2348 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
4c9649a9
JM		 2349 ret = 1;
2350 break;
2351 case 0x3E:
2352 /* BGE */
9c29504e 2353 gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
4c9649a9
JM		 2354 ret = 1;
2355 break;
2356 case 0x3F:
2357 /* BGT */
9c29504e 2358 gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
4c9649a9
JM		 2359 ret = 1;
2360 break;
2361 invalid_opc:
2362 gen_invalid(ctx);
2363 ret = 3;
2364 break;
2365 }
2366
2367 return ret;
2368}
2369
2cfc5f17
TS		 2370static always_inline void gen_intermediate_code_internal (CPUState *env,
2371 TranslationBlock *tb,
2372 int search_pc)
4c9649a9
JM		 2373{
2374#if defined ALPHA_DEBUG_DISAS
2375 static int insn_count;
2376#endif
2377 DisasContext ctx, *ctxp = &ctx;
2378 target_ulong pc_start;
2379 uint32_t insn;
2380 uint16_t *gen_opc_end;
2381 int j, lj = -1;
2382 int ret;
2e70f6ef
PB		 2383 int num_insns;
2384 int max_insns;
4c9649a9
JM		 2385
2386 pc_start = tb->pc;
4c9649a9 2387 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4c9649a9
JM		 2388 ctx.pc = pc_start;
2389 ctx.amask = env->amask;
2390#if defined (CONFIG_USER_ONLY)
2391 ctx.mem_idx = 0;
2392#else
2393 ctx.mem_idx = ((env->ps >> 3) & 3);
2394 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2395#endif
2e70f6ef
PB		 2396 num_insns = 0;
2397 max_insns = tb->cflags & CF_COUNT_MASK;
2398 if (max_insns == 0)
2399 max_insns = CF_COUNT_MASK;
2400
2401 gen_icount_start();
4c9649a9
JM		 2402 for (ret = 0; ret == 0;) {
2403 if (env->nb_breakpoints > 0) {
2404 for(j = 0; j < env->nb_breakpoints; j++) {
2405 if (env->breakpoints[j] == ctx.pc) {
2406 gen_excp(&ctx, EXCP_DEBUG, 0);
2407 break;
2408 }
2409 }
2410 }
2411 if (search_pc) {
2412 j = gen_opc_ptr - gen_opc_buf;
2413 if (lj < j) {
2414 lj++;
2415 while (lj < j)
2416 gen_opc_instr_start[lj++] = 0;
2417 gen_opc_pc[lj] = ctx.pc;
2418 gen_opc_instr_start[lj] = 1;
2e70f6ef 2419 gen_opc_icount[lj] = num_insns;
4c9649a9
JM		 2420 }
2421 }
2e70f6ef
PB		 2422 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
2423 gen_io_start();
4c9649a9
JM		 2424#if defined ALPHA_DEBUG_DISAS
2425 insn_count++;
2426 if (logfile != NULL) {
e96efcfc
JM		 2427 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
2428 ctx.pc, ctx.mem_idx);
4c9649a9
JM		 2429 }
2430#endif
2431 insn = ldl_code(ctx.pc);
2432#if defined ALPHA_DEBUG_DISAS
2433 insn_count++;
2434 if (logfile != NULL) {
2435 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
2436 }
2437#endif
2e70f6ef 2438 num_insns++;
4c9649a9
JM		 2439 ctx.pc += 4;
2440 ret = translate_one(ctxp, insn);
2441 if (ret != 0)
2442 break;
2443 /* if we reach a page boundary or are single stepping, stop
2444 * generation
2445 */
2446 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 2447 (env->singlestep_enabled) ||
2448 num_insns >= max_insns) {
4c9649a9
JM		 2449 break;
2450 }
2451#if defined (DO_SINGLE_STEP)
2452 break;
2453#endif
2454 }
2455 if (ret != 1 && ret != 3) {
496cb5b9 2456 tcg_gen_movi_i64(cpu_pc, ctx.pc);
4c9649a9 2457 }
4c9649a9 2458#if defined (DO_TB_FLUSH)
496cb5b9 2459 tcg_gen_helper_0_0(helper_tb_flush);
4c9649a9 2460#endif
2e70f6ef
PB		 2461 if (tb->cflags & CF_LAST_IO)
2462 gen_io_end();
4c9649a9 2463 /* Generate the return instruction */
57fec1fe 2464 tcg_gen_exit_tb(0);
2e70f6ef 2465 gen_icount_end(tb, num_insns);
4c9649a9
JM		 2466 *gen_opc_ptr = INDEX_op_end;
2467 if (search_pc) {
2468 j = gen_opc_ptr - gen_opc_buf;
2469 lj++;
2470 while (lj <= j)
2471 gen_opc_instr_start[lj++] = 0;
4c9649a9
JM		 2472 } else {
2473 tb->size = ctx.pc - pc_start;
2e70f6ef 2474 tb->icount = num_insns;
4c9649a9
JM		 2475 }
2476#if defined ALPHA_DEBUG_DISAS
2477 if (loglevel & CPU_LOG_TB_CPU) {
2478 cpu_dump_state(env, logfile, fprintf, 0);
2479 }
2480 if (loglevel & CPU_LOG_TB_IN_ASM) {
2481 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2482 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2483 fprintf(logfile, "\n");
2484 }
4c9649a9 2485#endif
4c9649a9
JM		 2486}
2487
2cfc5f17 2488void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
4c9649a9 2489{
2cfc5f17 2490 gen_intermediate_code_internal(env, tb, 0);
4c9649a9
JM		 2491}
2492
2cfc5f17 2493void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
4c9649a9 2494{
2cfc5f17 2495 gen_intermediate_code_internal(env, tb, 1);
4c9649a9
JM		 2496}
2497
aaed909a 2498CPUAlphaState * cpu_alpha_init (const char *cpu_model)
4c9649a9
JM		 2499{
2500 CPUAlphaState *env;
2501 uint64_t hwpcb;
2502
2503 env = qemu_mallocz(sizeof(CPUAlphaState));
2504 if (!env)
2505 return NULL;
2506 cpu_exec_init(env);
2e70f6ef 2507 alpha_translate_init();
4c9649a9
JM		 2508 tlb_flush(env, 1);
2509 /* XXX: should not be hardcoded */
2510 env->implver = IMPLVER_2106x;
2511 env->ps = 0x1F00;
2512#if defined (CONFIG_USER_ONLY)
2513 env->ps |= 1 << 3;
2514#endif
2515 pal_init(env);
2516 /* Initialize IPR */
2517 hwpcb = env->ipr[IPR_PCBB];
2518 env->ipr[IPR_ASN] = 0;
2519 env->ipr[IPR_ASTEN] = 0;
2520 env->ipr[IPR_ASTSR] = 0;
2521 env->ipr[IPR_DATFX] = 0;
2522 /* XXX: fix this */
2523 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2524 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2525 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2526 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2527 env->ipr[IPR_FEN] = 0;
2528 env->ipr[IPR_IPL] = 31;
2529 env->ipr[IPR_MCES] = 0;
2530 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2531 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2532 env->ipr[IPR_SISR] = 0;
2533 env->ipr[IPR_VIRBND] = -1ULL;
2534
2535 return env;
2536}
aaed909a 2537
d2856f1a
AJ		 2538void gen_pc_load(CPUState *env, TranslationBlock *tb,
2539 unsigned long searched_pc, int pc_pos, void *puc)
2540{
2541 env->pc = gen_opc_pc[pc_pos];
2542}
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