[qemu.git] / hw / ide / via.c

/*
 * QEMU IDE Emulation: PCI VIA82C686B support.
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2010 Huacai Chen <[email protected]>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/pc.h>
#include <hw/pci.h>
#include <hw/isa.h>
#include "block.h"
#include "block_int.h"
#include "sysemu.h"
#include "dma.h"

#include <hw/ide/pci.h>

static uint32_t bmdma_readb(void *opaque, uint32_t addr)
{
    BMDMAState *bm = opaque;
    uint32_t val;

    switch (addr & 3) {
    case 0:
        val = bm->cmd;
        break;
    case 2:
        val = bm->status;
        break;
    default:
        val = 0xff;
        break;
    }
#ifdef DEBUG_IDE
    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
#endif
    return val;
}

static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    BMDMAState *bm = opaque;
#ifdef DEBUG_IDE
    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
#endif
    switch (addr & 3) {
    case 2:
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
        break;
    default:;
    }
}

static void bmdma_map(PCIDevice *pci_dev, int region_num,
                    pcibus_t addr, pcibus_t size, int type)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
    int i;

    for(i = 0;i < 2; i++) {
        BMDMAState *bm = &d->bmdma[i];
        d->bus[i].bmdma = bm;
        bm->bus = d->bus+i;
        qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);

        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);

        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
        register_ioport_read(addr, 4, 1, bmdma_readb, bm);

        register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
        register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
        register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
        register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
        addr += 8;
    }
}

static void via_reset(void *opaque)
{
    PCIIDEState *d = opaque;
    uint8_t *pci_conf = d->dev.config;
    int i;

    for (i = 0; i < 2; i++) {
        ide_bus_reset(&d->bus[i]);
        ide_dma_reset(&d->bmdma[i]);
    }

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
                 PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
    pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
    pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);

    /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
    pci_set_long(pci_conf + 0x40, 0x0a090600);
    /* IDE misc configuration 1/2/3 */
    pci_set_long(pci_conf + 0x44, 0x00c00068);
    /* IDE Timing control */
    pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
    /* IDE Address Setup Time */
    pci_set_long(pci_conf + 0x4c, 0x000000ff);
    /* UltraDMA Extended Timing Control*/
    pci_set_long(pci_conf + 0x50, 0x07070707);
    /* UltraDMA FIFO Control */
    pci_set_long(pci_conf + 0x54, 0x00000004);
    /* IDE primary sector size */
    pci_set_long(pci_conf + 0x60, 0x00000200);
    /* IDE secondary sector size */
    pci_set_long(pci_conf + 0x68, 0x00000200);
    /* PCI PM Block */
    pci_set_long(pci_conf + 0xc0, 0x00020001);
}

/* via ide func */
static int vt82c686b_ide_initfn(PCIDevice *dev)
{
    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
    uint8_t *pci_conf = d->dev.config;

    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
    pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
    pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);

    qemu_register_reset(via_reset, d);
    pci_register_bar((PCIDevice *)d, 4, 0x10,
                           PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);

    vmstate_register(0, &vmstate_ide_pci, d);

    ide_bus_new(&d->bus[0], &d->dev.qdev);
    ide_bus_new(&d->bus[1], &d->dev.qdev);
    ide_init2(&d->bus[0], isa_reserve_irq(14));
    ide_init2(&d->bus[1], isa_reserve_irq(15));
    ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
    ide_init_ioport(&d->bus[1], 0x170, 0x376);

    return 0;
}

void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
    PCIDevice *dev;

    dev = pci_create_simple(bus, devfn, "via-ide");
    pci_ide_create_devs(dev, hd_table);
}

static PCIDeviceInfo via_ide_info = {
    .qdev.name    = "via-ide",
    .qdev.size    = sizeof(PCIIDEState),
    .qdev.no_user = 1,
    .init         = vt82c686b_ide_initfn,
};

static void via_ide_register(void)
{
    pci_qdev_register(&via_ide_info);
}
device_init(via_ide_register);
Commit	Line	Data
016512f3 HC	1	/*
	2	* QEMU IDE Emulation: PCI VIA82C686B support.
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	* Copyright (c) 2010 Huacai Chen <[email protected]>
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26	#include <hw/hw.h>
	27	#include <hw/pc.h>
	28	#include <hw/pci.h>
	29	#include <hw/isa.h>
	30	#include "block.h"
	31	#include "block_int.h"
	32	#include "sysemu.h"
	33	#include "dma.h"
	34
	35	#include <hw/ide/pci.h>
	36
	37	static uint32_t bmdma_readb(void *opaque, uint32_t addr)
	38	{
	39	BMDMAState *bm = opaque;
	40	uint32_t val;
	41
	42	switch (addr & 3) {
	43	case 0:
	44	val = bm->cmd;
	45	break;
	46	case 2:
	47	val = bm->status;
	48	break;
	49	default:
	50	val = 0xff;
	51	break;
	52	}
	53	#ifdef DEBUG_IDE
	54	printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
	55	#endif
	56	return val;
	57	}
	58
	59	static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
	60	{
	61	BMDMAState *bm = opaque;
	62	#ifdef DEBUG_IDE
	63	printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
	64	#endif
65	switch (addr & 3) {
66	case 2:
67	bm->status = (val & 0x60) \| (bm->status & 1) \| (bm->status & ~val & 0x06);
68	break;
69	default:;
70	}
71	}
72
73	static void bmdma_map(PCIDevice *pci_dev, int region_num,
74	pcibus_t addr, pcibus_t size, int type)
75	{
76	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
77	int i;
78
79	for(i = 0;i < 2; i++) {
80	BMDMAState *bm = &d->bmdma[i];
81	d->bus[i].bmdma = bm;
82	bm->bus = d->bus+i;
83	qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
84
85	register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
86
87	register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
88	register_ioport_read(addr, 4, 1, bmdma_readb, bm);
89
90	register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
91	register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
92	register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
93	register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
94	register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
95	register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
96	addr += 8;
97	}
98	}
99
100	static void via_reset(void *opaque)
101	{
102	PCIIDEState *d = opaque;
103	uint8_t *pci_conf = d->dev.config;
104	int i;
105
106	for (i = 0; i < 2; i++) {
107	ide_bus_reset(&d->bus[i]);
108	ide_dma_reset(&d->bmdma[i]);
109	}
110
111	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
112	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK \|
113	PCI_STATUS_DEVSEL_MEDIUM);
114
115	pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
116	pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
117	pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
118	pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
119	pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
120	pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
121
122	/* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
123	pci_set_long(pci_conf + 0x40, 0x0a090600);
124	/* IDE misc configuration 1/2/3 */
125	pci_set_long(pci_conf + 0x44, 0x00c00068);
126	/* IDE Timing control */
127	pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
128	/* IDE Address Setup Time */
129	pci_set_long(pci_conf + 0x4c, 0x000000ff);
130	/* UltraDMA Extended Timing Control*/
131	pci_set_long(pci_conf + 0x50, 0x07070707);
132	/* UltraDMA FIFO Control */
133	pci_set_long(pci_conf + 0x54, 0x00000004);
134	/* IDE primary sector size */
135	pci_set_long(pci_conf + 0x60, 0x00000200);
136	/* IDE secondary sector size */
137	pci_set_long(pci_conf + 0x68, 0x00000200);
138	/* PCI PM Block */
139	pci_set_long(pci_conf + 0xc0, 0x00020001);
140	}
141
142	/* via ide func */
143	static int vt82c686b_ide_initfn(PCIDevice *dev)
144	{
145	PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
146	uint8_t *pci_conf = d->dev.config;
147
148	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
149	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
150	pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
151	pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
152	pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
153	pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
154	pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
155
156	qemu_register_reset(via_reset, d);
157	pci_register_bar((PCIDevice *)d, 4, 0x10,
158	PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
159
160	vmstate_register(0, &vmstate_ide_pci, d);
161
162	ide_bus_new(&d->bus[0], &d->dev.qdev);
163	ide_bus_new(&d->bus[1], &d->dev.qdev);
164	ide_init2(&d->bus[0], isa_reserve_irq(14));
165	ide_init2(&d->bus[1], isa_reserve_irq(15));
166	ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
167	ide_init_ioport(&d->bus[1], 0x170, 0x376);
168
169	return 0;
170	}
171
172	void vt82c686b_ide_init(PCIBus bus, DriveInfo *hd_table, int devfn)
173	{
174	PCIDevice *dev;
175
176	dev = pci_create_simple(bus, devfn, "via-ide");
177	pci_ide_create_devs(dev, hd_table);
178	}
179
180	static PCIDeviceInfo via_ide_info = {
181	.qdev.name = "via-ide",
182	.qdev.size = sizeof(PCIIDEState),
183	.qdev.no_user = 1,
184	.init = vt82c686b_ide_initfn,
185	};
186
187	static void via_ide_register(void)
188	{
189	pci_qdev_register(&via_ide_info);
190	}
191	device_init(via_ide_register);