]> Git Repo - qemu.git/blame - cpu-exec.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: add the support for -netdev socket, listen
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
1d93f0f0 23#include "qemu-barrier.h"
c7f0f3b1 24#include "qtest.h"
7d13299d 25
36bdbe54
FB		 26int tb_invalidated_flag;
27
f0667e66 28//#define CONFIG_DEBUG_EXEC
7d13299d 29
9349b4f9 30bool qemu_cpu_has_work(CPUArchState *env)
6a4955a8
AL		 31{
32 return cpu_has_work(env);
33}
34
9349b4f9 35void cpu_loop_exit(CPUArchState *env)
e4533c7a 36{
cea5f9a2
BS		 37 env->current_tb = NULL;
38 longjmp(env->jmp_env, 1);
e4533c7a 39}
bfed01fc 40
fbf9eeb3
FB		 41/* exit the current TB from a signal handler. The host registers are
42 restored in a state compatible with the CPU emulator
43 */
9eff14f3 44#if defined(CONFIG_SOFTMMU)
9349b4f9 45void cpu_resume_from_signal(CPUArchState *env, void *puc)
9eff14f3 46{
9eff14f3
BS		 47 /* XXX: restore cpu registers saved in host registers */
48
49 env->exception_index = -1;
50 longjmp(env->jmp_env, 1);
51}
9eff14f3 52#endif
fbf9eeb3 53
2e70f6ef
PB		 54/* Execute the code without caching the generated code. An interpreter
55 could be used if available. */
9349b4f9 56static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
cea5f9a2 57 TranslationBlock *orig_tb)
2e70f6ef 58{
69784eae 59 tcg_target_ulong next_tb;
2e70f6ef
PB		 60 TranslationBlock *tb;
61
62 /* Should never happen.
63 We only end up here when an existing TB is too long. */
64 if (max_cycles > CF_COUNT_MASK)
65 max_cycles = CF_COUNT_MASK;
66
67 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
68 max_cycles);
69 env->current_tb = tb;
70 /* execute the generated code */
cea5f9a2 71 next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr);
1c3569fe 72 env->current_tb = NULL;
2e70f6ef
PB		 73
74 if ((next_tb & 3) == 2) {
75 /* Restore PC. This may happen if async event occurs before
76 the TB starts executing. */
622ed360 77 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 78 }
79 tb_phys_invalidate(tb, -1);
80 tb_free(tb);
81}
82
9349b4f9 83static TranslationBlock *tb_find_slow(CPUArchState *env,
cea5f9a2 84 target_ulong pc,
8a40a180 85 target_ulong cs_base,
c068688b 86 uint64_t flags)
8a40a180
FB		 87{
88 TranslationBlock *tb, **ptb1;
8a40a180 89 unsigned int h;
337fc758 90 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 91 target_ulong virt_page2;
3b46e624 92
8a40a180 93 tb_invalidated_flag = 0;
3b46e624 94
8a40a180 95 /* find translated block using physical mappings */
41c1b1c9 96 phys_pc = get_page_addr_code(env, pc);
8a40a180 97 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180
FB		 98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
5fafdf24 104 if (tb->pc == pc &&
8a40a180 105 tb->page_addr[0] == phys_page1 &&
5fafdf24 106 tb->cs_base == cs_base &&
8a40a180
FB		 107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
337fc758
BS		 110 tb_page_addr_t phys_page2;
111
5fafdf24 112 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 113 TARGET_PAGE_SIZE;
41c1b1c9 114 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 115 if (tb->page_addr[1] == phys_page2)
116 goto found;
117 } else {
118 goto found;
119 }
120 }
121 ptb1 = &tb->phys_hash_next;
122 }
123 not_found:
2e70f6ef
PB		 124 /* if no translated code available, then translate it now */
125 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 126
8a40a180 127 found:
2c90fe2b
KB		 128 /* Move the last found TB to the head of the list */
129 if (likely(*ptb1)) {
130 *ptb1 = tb->phys_hash_next;
131 tb->phys_hash_next = tb_phys_hash[h];
132 tb_phys_hash[h] = tb;
133 }
8a40a180
FB		 134 /* we add the TB in the virtual pc hash table */
135 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 136 return tb;
137}
138
9349b4f9 139static inline TranslationBlock *tb_find_fast(CPUArchState *env)
8a40a180
FB		 140{
141 TranslationBlock *tb;
142 target_ulong cs_base, pc;
6b917547 143 int flags;
8a40a180
FB		 144
145 /* we record a subset of the CPU state. It will
146 always be the same before a given translated block
147 is executed. */
6b917547 148 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 149 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 150 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
151 tb->flags != flags)) {
cea5f9a2 152 tb = tb_find_slow(env, pc, cs_base, flags);
8a40a180
FB		 153 }
154 return tb;
155}
156
1009d2ed
JK		 157static CPUDebugExcpHandler *debug_excp_handler;
158
159CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
160{
161 CPUDebugExcpHandler *old_handler = debug_excp_handler;
162
163 debug_excp_handler = handler;
164 return old_handler;
165}
166
9349b4f9 167static void cpu_handle_debug_exception(CPUArchState *env)
1009d2ed
JK		 168{
169 CPUWatchpoint *wp;
170
171 if (!env->watchpoint_hit) {
172 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
173 wp->flags &= ~BP_WATCHPOINT_HIT;
174 }
175 }
176 if (debug_excp_handler) {
177 debug_excp_handler(env);
178 }
179}
180
7d13299d
FB		 181/* main execution loop */
182
1a28cac3
MT		 183volatile sig_atomic_t exit_request;
184
9349b4f9 185int cpu_exec(CPUArchState *env)
7d13299d 186{
c356a1bc
AF		 187#ifdef TARGET_PPC
188 CPUState *cpu = ENV_GET_CPU(env);
189#endif
8a40a180 190 int ret, interrupt_request;
8a40a180 191 TranslationBlock *tb;
c27004ec 192 uint8_t *tc_ptr;
69784eae 193 tcg_target_ulong next_tb;
8c6939c0 194
cea5f9a2
BS		 195 if (env->halted) {
196 if (!cpu_has_work(env)) {
eda48c34
PB		 197 return EXCP_HALTED;
198 }
199
cea5f9a2 200 env->halted = 0;
eda48c34 201 }
5a1e3cfc 202
cea5f9a2 203 cpu_single_env = env;
e4533c7a 204
c629a4bc 205 if (unlikely(exit_request)) {
1a28cac3 206 env->exit_request = 1;
1a28cac3
MT		 207 }
208
ecb644f4 209#if defined(TARGET_I386)
6792a57b
JK		 210 /* put eflags in CPU temporary format */
211 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
212 DF = 1 - (2 * ((env->eflags >> 10) & 1));
213 CC_OP = CC_OP_EFLAGS;
214 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 215#elif defined(TARGET_SPARC)
e6e5906b
PB		 216#elif defined(TARGET_M68K)
217 env->cc_op = CC_OP_FLAGS;
218 env->cc_dest = env->sr & 0xf;
219 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 220#elif defined(TARGET_ALPHA)
221#elif defined(TARGET_ARM)
d2fbca94 222#elif defined(TARGET_UNICORE32)
ecb644f4 223#elif defined(TARGET_PPC)
4e85f82c 224 env->reserve_addr = -1;
81ea0e13 225#elif defined(TARGET_LM32)
b779e29e 226#elif defined(TARGET_MICROBLAZE)
6af0bf9c 227#elif defined(TARGET_MIPS)
e67db06e 228#elif defined(TARGET_OPENRISC)
fdf9b3e8 229#elif defined(TARGET_SH4)
f1ccf904 230#elif defined(TARGET_CRIS)
10ec5117 231#elif defined(TARGET_S390X)
2328826b 232#elif defined(TARGET_XTENSA)
fdf9b3e8 233 /* XXXXX */
e4533c7a
FB		 234#else
235#error unsupported target CPU
236#endif
3fb2ded1 237 env->exception_index = -1;
9d27abd9 238
7d13299d 239 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 240 for(;;) {
241 if (setjmp(env->jmp_env) == 0) {
242 /* if an exception is pending, we execute it here */
243 if (env->exception_index >= 0) {
244 if (env->exception_index >= EXCP_INTERRUPT) {
245 /* exit request from the cpu execution loop */
246 ret = env->exception_index;
1009d2ed
JK		 247 if (ret == EXCP_DEBUG) {
248 cpu_handle_debug_exception(env);
249 }
3fb2ded1 250 break;
72d239ed
AJ		 251 } else {
252#if defined(CONFIG_USER_ONLY)
3fb2ded1 253 /* if user mode only, we simulate a fake exception
9f083493 254 which will be handled outside the cpu execution
3fb2ded1 255 loop */
83479e77 256#if defined(TARGET_I386)
e694d4e2 257 do_interrupt(env);
83479e77 258#endif
3fb2ded1
FB		 259 ret = env->exception_index;
260 break;
72d239ed 261#else
b5ff1b31 262 do_interrupt(env);
301d2908 263 env->exception_index = -1;
83479e77 264#endif
3fb2ded1 265 }
5fafdf24 266 }
9df217a3 267
b5fc09ae 268 next_tb = 0; /* force lookup of first TB */
3fb2ded1 269 for(;;) {
68a79315 270 interrupt_request = env->interrupt_request;
e1638bd8 271 if (unlikely(interrupt_request)) {
272 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
273 /* Mask out external interrupts for this step. */
3125f763 274 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 275 }
6658ffb8
PB		 276 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
277 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
278 env->exception_index = EXCP_DEBUG;
1162c041 279 cpu_loop_exit(env);
6658ffb8 280 }
a90b7318 281#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 282 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
d2fbca94 283 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
a90b7318
AZ		 284 if (interrupt_request & CPU_INTERRUPT_HALT) {
285 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
286 env->halted = 1;
287 env->exception_index = EXCP_HLT;
1162c041 288 cpu_loop_exit(env);
a90b7318
AZ		 289 }
290#endif
68a79315 291#if defined(TARGET_I386)
5d62c43a
JK		 292#if !defined(CONFIG_USER_ONLY)
293 if (interrupt_request & CPU_INTERRUPT_POLL) {
294 env->interrupt_request &= ~CPU_INTERRUPT_POLL;
295 apic_poll_irq(env->apic_state);
296 }
297#endif
b09ea7d5 298 if (interrupt_request & CPU_INTERRUPT_INIT) {
77b2bc2c
BS		 299 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
300 0);
232fc23b 301 do_cpu_init(x86_env_get_cpu(env));
b09ea7d5 302 env->exception_index = EXCP_HALTED;
1162c041 303 cpu_loop_exit(env);
b09ea7d5 304 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
232fc23b 305 do_cpu_sipi(x86_env_get_cpu(env));
b09ea7d5 306 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 307 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
308 !(env->hflags & HF_SMM_MASK)) {
77b2bc2c
BS		 309 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
310 0);
db620f46 311 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
e694d4e2 312 do_smm_enter(env);
db620f46
FB		 313 next_tb = 0;
314 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
315 !(env->hflags2 & HF2_NMI_MASK)) {
316 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
317 env->hflags2 |= HF2_NMI_MASK;
e694d4e2 318 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
db620f46 319 next_tb = 0;
e965fc38 320 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
79c4f6b0 321 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
e694d4e2 322 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
79c4f6b0 323 next_tb = 0;
db620f46
FB		 324 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
325 (((env->hflags2 & HF2_VINTR_MASK) &&
326 (env->hflags2 & HF2_HIF_MASK)) ||
327 (!(env->hflags2 & HF2_VINTR_MASK) &&
328 (env->eflags & IF_MASK &&
329 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
330 int intno;
77b2bc2c
BS		 331 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
332 0);
db620f46
FB		 333 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
334 intno = cpu_get_pic_interrupt(env);
93fcfe39 335 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
e694d4e2 336 do_interrupt_x86_hardirq(env, intno, 1);
db620f46
FB		 337 /* ensure that no TB jump will be modified as
338 the program flow was changed */
339 next_tb = 0;
0573fbfc 340#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 341 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
342 (env->eflags & IF_MASK) &&
343 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
344 int intno;
345 /* FIXME: this should respect TPR */
77b2bc2c
BS		 346 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
347 0);
db620f46 348 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 349 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
e694d4e2 350 do_interrupt_x86_hardirq(env, intno, 1);
d40c54d6 351 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 352 next_tb = 0;
907a5b26 353#endif
db620f46 354 }
68a79315 355 }
ce09776b 356#elif defined(TARGET_PPC)
9fddaa0c 357 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
c356a1bc 358 cpu_reset(cpu);
9fddaa0c 359 }
47103572 360 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 361 ppc_hw_interrupt(env);
362 if (env->pending_interrupts == 0)
363 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 364 next_tb = 0;
ce09776b 365 }
81ea0e13
MW		 366#elif defined(TARGET_LM32)
367 if ((interrupt_request & CPU_INTERRUPT_HARD)
368 && (env->ie & IE_IE)) {
369 env->exception_index = EXCP_IRQ;
370 do_interrupt(env);
371 next_tb = 0;
372 }
b779e29e
EI		 373#elif defined(TARGET_MICROBLAZE)
374 if ((interrupt_request & CPU_INTERRUPT_HARD)
375 && (env->sregs[SR_MSR] & MSR_IE)
376 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
377 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
378 env->exception_index = EXCP_IRQ;
379 do_interrupt(env);
380 next_tb = 0;
381 }
6af0bf9c
FB		 382#elif defined(TARGET_MIPS)
383 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 384 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 385 /* Raise it */
386 env->exception_index = EXCP_EXT_INTERRUPT;
387 env->error_code = 0;
388 do_interrupt(env);
b5fc09ae 389 next_tb = 0;
6af0bf9c 390 }
b6a71ef7
JL		 391#elif defined(TARGET_OPENRISC)
392 {
393 int idx = -1;
394 if ((interrupt_request & CPU_INTERRUPT_HARD)
395 && (env->sr & SR_IEE)) {
396 idx = EXCP_INT;
397 }
398 if ((interrupt_request & CPU_INTERRUPT_TIMER)
399 && (env->sr & SR_TEE)) {
400 idx = EXCP_TICK;
401 }
402 if (idx >= 0) {
403 env->exception_index = idx;
404 do_interrupt(env);
405 next_tb = 0;
406 }
407 }
e95c8d51 408#elif defined(TARGET_SPARC)
d532b26c
IK		 409 if (interrupt_request & CPU_INTERRUPT_HARD) {
410 if (cpu_interrupts_enabled(env) &&
411 env->interrupt_index > 0) {
412 int pil = env->interrupt_index & 0xf;
413 int type = env->interrupt_index & 0xf0;
414
415 if (((type == TT_EXTINT) &&
416 cpu_pil_allowed(env, pil)) ||
417 type != TT_EXTINT) {
418 env->exception_index = env->interrupt_index;
419 do_interrupt(env);
420 next_tb = 0;
421 }
422 }
e965fc38 423 }
b5ff1b31
FB		 424#elif defined(TARGET_ARM)
425 if (interrupt_request & CPU_INTERRUPT_FIQ
426 && !(env->uncached_cpsr & CPSR_F)) {
427 env->exception_index = EXCP_FIQ;
428 do_interrupt(env);
b5fc09ae 429 next_tb = 0;
b5ff1b31 430 }
9ee6e8bb
PB		 431 /* ARMv7-M interrupt return works by loading a magic value
432 into the PC. On real hardware the load causes the
433 return to occur. The qemu implementation performs the
434 jump normally, then does the exception return when the
435 CPU tries to execute code at the magic address.
436 This will cause the magic PC value to be pushed to
a1c7273b 437 the stack if an interrupt occurred at the wrong time.
9ee6e8bb
PB		 438 We avoid this by disabling interrupts when
439 pc contains a magic address. */
b5ff1b31 440 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 441 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
442 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 443 env->exception_index = EXCP_IRQ;
444 do_interrupt(env);
b5fc09ae 445 next_tb = 0;
b5ff1b31 446 }
d2fbca94
GX		 447#elif defined(TARGET_UNICORE32)
448 if (interrupt_request & CPU_INTERRUPT_HARD
449 && !(env->uncached_asr & ASR_I)) {
450 do_interrupt(env);
451 next_tb = 0;
452 }
fdf9b3e8 453#elif defined(TARGET_SH4)
e96e2044
TS		 454 if (interrupt_request & CPU_INTERRUPT_HARD) {
455 do_interrupt(env);
b5fc09ae 456 next_tb = 0;
e96e2044 457 }
eddf68a6 458#elif defined(TARGET_ALPHA)
6a80e088
RH		 459 {
460 int idx = -1;
461 /* ??? This hard-codes the OSF/1 interrupt levels. */
e965fc38 462 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
6a80e088
RH		 463 case 0 ... 3:
464 if (interrupt_request & CPU_INTERRUPT_HARD) {
465 idx = EXCP_DEV_INTERRUPT;
466 }
467 /* FALLTHRU */
468 case 4:
469 if (interrupt_request & CPU_INTERRUPT_TIMER) {
470 idx = EXCP_CLK_INTERRUPT;
471 }
472 /* FALLTHRU */
473 case 5:
474 if (interrupt_request & CPU_INTERRUPT_SMP) {
475 idx = EXCP_SMP_INTERRUPT;
476 }
477 /* FALLTHRU */
478 case 6:
479 if (interrupt_request & CPU_INTERRUPT_MCHK) {
480 idx = EXCP_MCHK;
481 }
482 }
483 if (idx >= 0) {
484 env->exception_index = idx;
485 env->error_code = 0;
486 do_interrupt(env);
487 next_tb = 0;
488 }
eddf68a6 489 }
f1ccf904 490#elif defined(TARGET_CRIS)
1b1a38b0 491 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 492 && (env->pregs[PR_CCS] & I_FLAG)
493 && !env->locked_irq) {
1b1a38b0
EI		 494 env->exception_index = EXCP_IRQ;
495 do_interrupt(env);
496 next_tb = 0;
497 }
8219314b
LP		 498 if (interrupt_request & CPU_INTERRUPT_NMI) {
499 unsigned int m_flag_archval;
500 if (env->pregs[PR_VR] < 32) {
501 m_flag_archval = M_FLAG_V10;
502 } else {
503 m_flag_archval = M_FLAG_V32;
504 }
505 if ((env->pregs[PR_CCS] & m_flag_archval)) {
506 env->exception_index = EXCP_NMI;
507 do_interrupt(env);
508 next_tb = 0;
509 }
f1ccf904 510 }
0633879f
PB		 511#elif defined(TARGET_M68K)
512 if (interrupt_request & CPU_INTERRUPT_HARD
513 && ((env->sr & SR_I) >> SR_I_SHIFT)
514 < env->pending_level) {
515 /* Real hardware gets the interrupt vector via an
516 IACK cycle at this point. Current emulated
517 hardware doesn't rely on this, so we
518 provide/save the vector when the interrupt is
519 first signalled. */
520 env->exception_index = env->pending_vector;
3c688828 521 do_interrupt_m68k_hardirq(env);
b5fc09ae 522 next_tb = 0;
0633879f 523 }
3110e292
AG		 524#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
525 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
526 (env->psw.mask & PSW_MASK_EXT)) {
527 do_interrupt(env);
528 next_tb = 0;
529 }
40643d7c
MF		 530#elif defined(TARGET_XTENSA)
531 if (interrupt_request & CPU_INTERRUPT_HARD) {
532 env->exception_index = EXC_IRQ;
533 do_interrupt(env);
534 next_tb = 0;
535 }
68a79315 536#endif
ff2712ba 537 /* Don't use the cached interrupt_request value,
9d05095e 538 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 539 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 540 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
541 /* ensure that no TB jump will be modified as
542 the program flow was changed */
b5fc09ae 543 next_tb = 0;
bf3e8bf1 544 }
be214e6c
AJ		 545 }
546 if (unlikely(env->exit_request)) {
547 env->exit_request = 0;
548 env->exception_index = EXCP_INTERRUPT;
1162c041 549 cpu_loop_exit(env);
3fb2ded1 550 }
a73b1fd9 551#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 552 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 553 /* restore flags in standard format */
ecb644f4 554#if defined(TARGET_I386)
e694d4e2
BS		 555 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
556 | (DF & DF_MASK);
93fcfe39 557 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 558 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 559#elif defined(TARGET_M68K)
560 cpu_m68k_flush_flags(env, env->cc_op);
561 env->cc_op = CC_OP_FLAGS;
562 env->sr = (env->sr & 0xffe0)
563 | env->cc_dest | (env->cc_x << 4);
93fcfe39 564 log_cpu_state(env, 0);
e4533c7a 565#else
a73b1fd9 566 log_cpu_state(env, 0);
e4533c7a 567#endif
3fb2ded1 568 }
a73b1fd9 569#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 570 spin_lock(&tb_lock);
cea5f9a2 571 tb = tb_find_fast(env);
d5975363
PB		 572 /* Note: we do it here to avoid a gcc bug on Mac OS X when
573 doing it in tb_find_slow */
574 if (tb_invalidated_flag) {
575 /* as some TB could have been invalidated because
576 of memory exceptions while generating the code, we
577 must recompute the hash index here */
578 next_tb = 0;
2e70f6ef 579 tb_invalidated_flag = 0;
d5975363 580 }
f0667e66 581#ifdef CONFIG_DEBUG_EXEC
3ba19255
SW		 582 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
583 tb->tc_ptr, tb->pc,
93fcfe39 584 lookup_symbol(tb->pc));
9d27abd9 585#endif
8a40a180
FB		 586 /* see if we can patch the calling TB. When the TB
587 spans two pages, we cannot safely do a direct
588 jump. */
040f2fb2 589 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 590 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 591 }
d5975363 592 spin_unlock(&tb_lock);
55e8b85e 593
594 /* cpu_interrupt might be called while translating the
595 TB, but before it is linked into a potentially
596 infinite loop and becomes env->current_tb. Avoid
597 starting execution if there is a pending interrupt. */
b0052d15
JK		 598 env->current_tb = tb;
599 barrier();
600 if (likely(!env->exit_request)) {
2e70f6ef 601 tc_ptr = tb->tc_ptr;
e965fc38 602 /* execute the generated code */
cea5f9a2 603 next_tb = tcg_qemu_tb_exec(env, tc_ptr);
2e70f6ef 604 if ((next_tb & 3) == 2) {
bf20dc07 605 /* Instruction counter expired. */
2e70f6ef 606 int insns_left;
69784eae 607 tb = (TranslationBlock *)(next_tb & ~3);
2e70f6ef 608 /* Restore PC. */
622ed360 609 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 610 insns_left = env->icount_decr.u32;
611 if (env->icount_extra && insns_left >= 0) {
612 /* Refill decrementer and continue execution. */
613 env->icount_extra += insns_left;
614 if (env->icount_extra > 0xffff) {
615 insns_left = 0xffff;
616 } else {
617 insns_left = env->icount_extra;
618 }
619 env->icount_extra -= insns_left;
620 env->icount_decr.u16.low = insns_left;
621 } else {
622 if (insns_left > 0) {
623 /* Execute remaining instructions. */
cea5f9a2 624 cpu_exec_nocache(env, insns_left, tb);
2e70f6ef
PB		 625 }
626 env->exception_index = EXCP_INTERRUPT;
627 next_tb = 0;
1162c041 628 cpu_loop_exit(env);
2e70f6ef
PB		 629 }
630 }
631 }
b0052d15 632 env->current_tb = NULL;
4cbf74b6
FB		 633 /* reset soft MMU for next block (it can currently
634 only be set by a memory fault) */
50a518e3 635 } /* for(;;) */
0d101938
JK		 636 } else {
637 /* Reload env after longjmp - the compiler may have smashed all
638 * local variables as longjmp is marked 'noreturn'. */
639 env = cpu_single_env;
7d13299d 640 }
3fb2ded1
FB		 641 } /* for(;;) */
642
7d13299d 643
e4533c7a 644#if defined(TARGET_I386)
9de5e440 645 /* restore flags in standard format */
e694d4e2
BS		 646 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
647 | (DF & DF_MASK);
e4533c7a 648#elif defined(TARGET_ARM)
b7bcbe95 649 /* XXX: Save/restore host fpu exception state?. */
d2fbca94 650#elif defined(TARGET_UNICORE32)
93ac68bc 651#elif defined(TARGET_SPARC)
67867308 652#elif defined(TARGET_PPC)
81ea0e13 653#elif defined(TARGET_LM32)
e6e5906b
PB		 654#elif defined(TARGET_M68K)
655 cpu_m68k_flush_flags(env, env->cc_op);
656 env->cc_op = CC_OP_FLAGS;
657 env->sr = (env->sr & 0xffe0)
658 | env->cc_dest | (env->cc_x << 4);
b779e29e 659#elif defined(TARGET_MICROBLAZE)
6af0bf9c 660#elif defined(TARGET_MIPS)
e67db06e 661#elif defined(TARGET_OPENRISC)
fdf9b3e8 662#elif defined(TARGET_SH4)
eddf68a6 663#elif defined(TARGET_ALPHA)
f1ccf904 664#elif defined(TARGET_CRIS)
10ec5117 665#elif defined(TARGET_S390X)
2328826b 666#elif defined(TARGET_XTENSA)
fdf9b3e8 667 /* XXXXX */
e4533c7a
FB		 668#else
669#error unsupported target CPU
670#endif
1057eaa7 671
6a00d601 672 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 673 cpu_single_env = NULL;
7d13299d
FB		 674 return ret;
675}
Empty description
This page took 0.615998 seconds and 4 git commands to generate.