[qemu.git] / hw / versatilepb.c

/*
 * ARM Versatile Platform/Application Baseboard System emulation.
 *
 * Copyright (c) 2005-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "net.h"
#include "sysemu.h"
#include "pci.h"
#include "usb-ohci.h"
#include "boards.h"
#include "blockdev.h"

/* Primary interrupt controller.  */

typedef struct vpb_sic_state
{
  SysBusDevice busdev;
  uint32_t level;
  uint32_t mask;
  uint32_t pic_enable;
  qemu_irq parent[32];
  int irq;
} vpb_sic_state;

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    qemu_set_irq(s->parent[s->irq], flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        qemu_set_irq(s->parent[irq], level);
    vpb_sic_update(s);
}

static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
    vpb_sic_update(s);
}

static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
   vpb_sic_read,
   vpb_sic_read,
   vpb_sic_read
};

static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
   vpb_sic_write,
   vpb_sic_write,
   vpb_sic_write
};

static int vpb_sic_init(SysBusDevice *dev)
{
    vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
    int iomemtype;
    int i;

    qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->parent[i]);
    }
    s->irq = 31;
    iomemtype = cpu_register_io_memory(vpb_sic_readfn,
                                       vpb_sic_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    /* ??? Save/restore.  */
    return 0;
}

/* Board init.  */

/* The AB and PB boards both use the same core, just with different
   peripherans and expansion busses.  For now we emulate a subset of the
   PB peripherals and just change the board ID.  */

static struct arm_boot_info versatile_binfo;

static void versatile_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     int board_id)
{
    CPUState *env;
    ram_addr_t ram_offset;
    qemu_irq *cpu_pic;
    qemu_irq pic[32];
    qemu_irq sic[32];
    DeviceState *dev;
    PCIBus *pci_bus;
    NICInfo *nd;
    int n;
    int done_smc = 0;

    if (!cpu_model)
        cpu_model = "arm926";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
    /* ??? RAM should repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

    arm_sysctl_init(0x10000000, 0x41007004, 0x02000000);
    cpu_pic = arm_pic_init_cpu(env);
    dev = sysbus_create_varargs("pl190", 0x10140000,
                                cpu_pic[0], cpu_pic[1], NULL);
    for (n = 0; n < 32; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }
    dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
    for (n = 0; n < 32; n++) {
        sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
        sic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
    sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);

    dev = sysbus_create_varargs("versatile_pci", 0x40000000,
                                sic[27], sic[28], sic[29], sic[30], NULL);
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");

    /* The Versatile PCI bridge does not provide access to PCI IO space,
       so many of the qemu PCI devices are not useable.  */
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) {
            smc91c111_init(nd, 0x10010000, sic[25]);
            done_smc = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }
    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, -1);
    }
    n = drive_get_max_bus(IF_SCSI);
    while (n >= 0) {
        pci_create_simple(pci_bus, -1, "lsi53c895a");
        n--;
    }

    sysbus_create_simple("pl011", 0x101f1000, pic[12]);
    sysbus_create_simple("pl011", 0x101f2000, pic[13]);
    sysbus_create_simple("pl011", 0x101f3000, pic[14]);
    sysbus_create_simple("pl011", 0x10009000, sic[6]);

    sysbus_create_simple("pl080", 0x10130000, pic[17]);
    sysbus_create_simple("sp804", 0x101e2000, pic[4]);
    sysbus_create_simple("sp804", 0x101e3000, pic[5]);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);

    sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
    sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);

    /* Add PL031 Real Time Clock. */
    sysbus_create_simple("pl031", 0x101e8000, pic[10]);

    /* Memory map for Versatile/PB:  */
    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /*  0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /*  0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */

    versatile_binfo.ram_size = ram_size;
    versatile_binfo.kernel_filename = kernel_filename;
    versatile_binfo.kernel_cmdline = kernel_cmdline;
    versatile_binfo.initrd_filename = initrd_filename;
    versatile_binfo.board_id = board_id;
    arm_load_kernel(env, &versatile_binfo);
}

static void vpb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size,
                   boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x183);
}

static void vab_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size,
                   boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x25e);
}

static QEMUMachine versatilepb_machine = {
    .name = "versatilepb",
    .desc = "ARM Versatile/PB (ARM926EJ-S)",
    .init = vpb_init,
    .use_scsi = 1,
};

static QEMUMachine versatileab_machine = {
    .name = "versatileab",
    .desc = "ARM Versatile/AB (ARM926EJ-S)",
    .init = vab_init,
    .use_scsi = 1,
};

static void versatile_machine_init(void)
{
    qemu_register_machine(&versatilepb_machine);
    qemu_register_machine(&versatileab_machine);
}

machine_init(versatile_machine_init);

static void versatilepb_register_devices(void)
{
    sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state),
                        vpb_sic_init);
}

device_init(versatilepb_register_devices)
Commit	Line	Data
5fafdf24	1	/*
16406950	2	* ARM Versatile Platform/Application Baseboard System emulation.
cdbdb648	3	*
a1bb27b1	4	* Copyright (c) 2005-2007 CodeSourcery.
cdbdb648 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "net.h"
	15	#include "sysemu.h"
	16	#include "pci.h"
18e08a55	17	#include "usb-ohci.h"
87ecb68b	18	#include "boards.h"
2446333c	19	#include "blockdev.h"
cdbdb648	20
cdbdb648 PB	21	/* Primary interrupt controller. */
	22
	23	typedef struct vpb_sic_state
	24	{
3950f18b	25	SysBusDevice busdev;
cdbdb648 PB	26	uint32_t level;
	27	uint32_t mask;
	28	uint32_t pic_enable;
97aff481	29	qemu_irq parent[32];
cdbdb648 PB	30	int irq;
	31	} vpb_sic_state;
	32
	33	static void vpb_sic_update(vpb_sic_state *s)
	34	{
	35	uint32_t flags;
	36
	37	flags = s->level & s->mask;
d537cf6c	38	qemu_set_irq(s->parent[s->irq], flags != 0);
cdbdb648 PB	39	}
	40
	41	static void vpb_sic_update_pic(vpb_sic_state *s)
	42	{
	43	int i;
	44	uint32_t mask;
	45
	46	for (i = 21; i <= 30; i++) {
	47	mask = 1u << i;
	48	if (!(s->pic_enable & mask))
	49	continue;
d537cf6c	50	qemu_set_irq(s->parent[i], (s->level & mask) != 0);
cdbdb648 PB	51	}
	52	}
	53
	54	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	55	{
	56	vpb_sic_state s = (vpb_sic_state )opaque;
	57	if (level)
	58	s->level \|= 1u << irq;
	59	else
	60	s->level &= ~(1u << irq);
	61	if (s->pic_enable & (1u << irq))
d537cf6c	62	qemu_set_irq(s->parent[irq], level);
cdbdb648 PB	63	vpb_sic_update(s);
	64	}
	65
c227f099	66	static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	67	{
	68	vpb_sic_state s = (vpb_sic_state )opaque;
	69
cdbdb648 PB	70	switch (offset >> 2) {
	71	case 0: /* STATUS */
	72	return s->level & s->mask;
	73	case 1: /* RAWSTAT */
	74	return s->level;
	75	case 2: /* ENABLE */
	76	return s->mask;
	77	case 4: /* SOFTINT */
	78	return s->level & 1;
	79	case 8: /* PICENABLE */
	80	return s->pic_enable;
	81	default:
e69954b9	82	printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	83	return 0;
	84	}
	85	}
	86
c227f099	87	static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	88	uint32_t value)
	89	{
	90	vpb_sic_state s = (vpb_sic_state )opaque;
cdbdb648 PB	91
	92	switch (offset >> 2) {
	93	case 2: /* ENSET */
	94	s->mask \|= value;
	95	break;
	96	case 3: /* ENCLR */
	97	s->mask &= ~value;
	98	break;
	99	case 4: /* SOFTINTSET */
	100	if (value)
	101	s->mask \|= 1;
	102	break;
	103	case 5: /* SOFTINTCLR */
	104	if (value)
	105	s->mask &= ~1u;
	106	break;
	107	case 8: /* PICENSET */
	108	s->pic_enable \|= (value & 0x7fe00000);
	109	vpb_sic_update_pic(s);
	110	break;
	111	case 9: /* PICENCLR */
	112	s->pic_enable &= ~value;
	113	vpb_sic_update_pic(s);
	114	break;
	115	default:
e69954b9	116	printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	117	return;
	118	}
	119	vpb_sic_update(s);
	120	}
	121
d60efc6b	122	static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
cdbdb648 PB	123	vpb_sic_read,
	124	vpb_sic_read,
	125	vpb_sic_read
	126	};
	127
d60efc6b	128	static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
cdbdb648 PB	129	vpb_sic_write,
	130	vpb_sic_write,
	131	vpb_sic_write
	132	};
	133
81a322d4	134	static int vpb_sic_init(SysBusDevice *dev)
cdbdb648	135	{
3950f18b	136	vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
cdbdb648	137	int iomemtype;
97aff481	138	int i;
cdbdb648	139
067a3ddc	140	qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
97aff481	141	for (i = 0; i < 32; i++) {
3950f18b	142	sysbus_init_irq(dev, &s->parent[i]);
97aff481	143	}
3950f18b	144	s->irq = 31;
1eed09cb	145	iomemtype = cpu_register_io_memory(vpb_sic_readfn,
cdbdb648	146	vpb_sic_writefn, s);
3950f18b	147	sysbus_init_mmio(dev, 0x1000, iomemtype);
cdbdb648	148	/* ??? Save/restore. */
81a322d4	149	return 0;
cdbdb648 PB	150	}
	151
	152	/* Board init. */
	153
16406950 PB	154	/* The AB and PB boards both use the same core, just with different
	155	peripherans and expansion busses. For now we emulate a subset of the
	156	PB peripherals and just change the board ID. */
cdbdb648	157
f93eb9ff AZ	158	static struct arm_boot_info versatile_binfo;
f93eb9ff AZ	159
c227f099	160	static void versatile_init(ram_addr_t ram_size,
3023f332	161	const char *boot_device,
cdbdb648	162	const char kernel_filename, const char kernel_cmdline,
3371d272 PB	163	const char initrd_filename, const char cpu_model,
3371d272 PB	164	int board_id)
cdbdb648 PB	165	{
cdbdb648 PB	166	CPUState *env;
c227f099	167	ram_addr_t ram_offset;
97aff481 PB	168	qemu_irq *cpu_pic;
97aff481 PB	169	qemu_irq pic[32];
3950f18b	170	qemu_irq sic[32];
97aff481	171	DeviceState *dev;
502a5395 PB	172	PCIBus *pci_bus;
	173	NICInfo *nd;
	174	int n;
	175	int done_smc = 0;
cdbdb648	176
3371d272 PB	177	if (!cpu_model)
3371d272 PB	178	cpu_model = "arm926";
aaed909a FB	179	env = cpu_init(cpu_model);
	180	if (!env) {
	181	fprintf(stderr, "Unable to find CPU definition\n");
	182	exit(1);
	183	}
1724f049	184	ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
1235fc06	185	/* ??? RAM should repeat to fill physical memory space. */
cdbdb648	186	/* SDRAM at address zero. */
7ffab4d7	187	cpu_register_physical_memory(0, ram_size, ram_offset \| IO_MEM_RAM);
cdbdb648	188
26e92f65	189	arm_sysctl_init(0x10000000, 0x41007004, 0x02000000);
97aff481 PB	190	cpu_pic = arm_pic_init_cpu(env);
	191	dev = sysbus_create_varargs("pl190", 0x10140000,
	192	cpu_pic[0], cpu_pic[1], NULL);
	193	for (n = 0; n < 32; n++) {
067a3ddc	194	pic[n] = qdev_get_gpio_in(dev, n);
97aff481	195	}
3950f18b PB	196	dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
	197	for (n = 0; n < 32; n++) {
	198	sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
067a3ddc	199	sic[n] = qdev_get_gpio_in(dev, n);
3950f18b	200	}
86394e96 PB	201
	202	sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
	203	sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
cdbdb648	204
0027b06d PB	205	dev = sysbus_create_varargs("versatile_pci", 0x40000000,
0027b06d PB	206	sic[27], sic[28], sic[29], sic[30], NULL);
02e2da45	207	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
0027b06d	208
502a5395 PB	209	/* The Versatile PCI bridge does not provide access to PCI IO space,
	210	so many of the qemu PCI devices are not useable. */
	211	for(n = 0; n < nb_nics; n++) {
	212	nd = &nd_table[n];
0ae18cee AL	213
0ae18cee AL	214	if ((!nd->model && !done_smc) \|\| strcmp(nd->model, "smc91c111") == 0) {
d537cf6c	215	smc91c111_init(nd, 0x10010000, sic[25]);
0ae18cee	216	done_smc = 1;
cdbdb648	217	} else {
07caea31	218	pci_nic_init_nofail(nd, "rtl8139", NULL);
cdbdb648 PB	219	}
cdbdb648 PB	220	}
0d92ed30	221	if (usb_enabled) {
a67ba3b6	222	usb_ohci_init_pci(pci_bus, -1);
0d92ed30	223	}
9be5dafe PB	224	n = drive_get_max_bus(IF_SCSI);
	225	while (n >= 0) {
	226	pci_create_simple(pci_bus, -1, "lsi53c895a");
	227	n--;
7d8406be	228	}
cdbdb648	229
a7d518a6 PB	230	sysbus_create_simple("pl011", 0x101f1000, pic[12]);
	231	sysbus_create_simple("pl011", 0x101f2000, pic[13]);
	232	sysbus_create_simple("pl011", 0x101f3000, pic[14]);
	233	sysbus_create_simple("pl011", 0x10009000, sic[6]);
cdbdb648	234
b4496b13	235	sysbus_create_simple("pl080", 0x10130000, pic[17]);
6a824ec3 PB	236	sysbus_create_simple("sp804", 0x101e2000, pic[4]);
6a824ec3 PB	237	sysbus_create_simple("sp804", 0x101e3000, pic[5]);
cdbdb648 PB	238
	239	/* The versatile/PB actually has a modified Color LCD controller
	240	that includes hardware cursor support from the PL111. */
2e9bdce5	241	sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
cdbdb648	242
aa9311d8 PB	243	sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
aa9311d8 PB	244	sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
a1bb27b1	245
7e1543c2	246	/* Add PL031 Real Time Clock. */
a63bdb31	247	sysbus_create_simple("pl031", 0x101e8000, pic[10]);
7e1543c2	248
16406950	249	/* Memory map for Versatile/PB: */
cdbdb648 PB	250	/* 0x10000000 System registers. */
	251	/* 0x10001000 PCI controller config registers. */
	252	/* 0x10002000 Serial bus interface. */
	253	/* 0x10003000 Secondary interrupt controller. */
	254	/* 0x10004000 AACI (audio). */
a1bb27b1	255	/* 0x10005000 MMCI0. */
cdbdb648 PB	256	/* 0x10006000 KMI0 (keyboard). */
	257	/* 0x10007000 KMI1 (mouse). */
	258	/* 0x10008000 Character LCD Interface. */
	259	/* 0x10009000 UART3. */
	260	/* 0x1000a000 Smart card 1. */
a1bb27b1	261	/* 0x1000b000 MMCI1. */
cdbdb648 PB	262	/* 0x10010000 Ethernet. */
	263	/* 0x10020000 USB. */
	264	/* 0x10100000 SSMC. */
	265	/* 0x10110000 MPMC. */
	266	/* 0x10120000 CLCD Controller. */
	267	/* 0x10130000 DMA Controller. */
	268	/* 0x10140000 Vectored interrupt controller. */
	269	/* 0x101d0000 AHB Monitor Interface. */
	270	/* 0x101e0000 System Controller. */
	271	/* 0x101e1000 Watchdog Interface. */
	272	/* 0x101e2000 Timer 0/1. */
	273	/* 0x101e3000 Timer 2/3. */
	274	/* 0x101e4000 GPIO port 0. */
	275	/* 0x101e5000 GPIO port 1. */
	276	/* 0x101e6000 GPIO port 2. */
	277	/* 0x101e7000 GPIO port 3. */
	278	/* 0x101e8000 RTC. */
	279	/* 0x101f0000 Smart card 0. */
	280	/* 0x101f1000 UART0. */
	281	/* 0x101f2000 UART1. */
	282	/* 0x101f3000 UART2. */
	283	/* 0x101f4000 SSPI. */
	284
f93eb9ff AZ	285	versatile_binfo.ram_size = ram_size;
	286	versatile_binfo.kernel_filename = kernel_filename;
	287	versatile_binfo.kernel_cmdline = kernel_cmdline;
	288	versatile_binfo.initrd_filename = initrd_filename;
	289	versatile_binfo.board_id = board_id;
	290	arm_load_kernel(env, &versatile_binfo);
16406950 PB	291	}
16406950 PB	292
c227f099	293	static void vpb_init(ram_addr_t ram_size,
3023f332	294	const char *boot_device,
16406950	295	const char kernel_filename, const char kernel_cmdline,
94fc95cd	296	const char initrd_filename, const char cpu_model)
16406950	297	{
fbe1b595	298	versatile_init(ram_size,
3023f332	299	boot_device,
16406950	300	kernel_filename, kernel_cmdline,
3371d272	301	initrd_filename, cpu_model, 0x183);
16406950 PB	302	}
16406950 PB	303
c227f099	304	static void vab_init(ram_addr_t ram_size,
3023f332	305	const char *boot_device,
16406950	306	const char kernel_filename, const char kernel_cmdline,
94fc95cd	307	const char initrd_filename, const char cpu_model)
16406950	308	{
fbe1b595	309	versatile_init(ram_size,
3023f332	310	boot_device,
16406950	311	kernel_filename, kernel_cmdline,
3371d272	312	initrd_filename, cpu_model, 0x25e);
cdbdb648 PB	313	}
cdbdb648 PB	314
f80f9ec9	315	static QEMUMachine versatilepb_machine = {
c9b1ae2c BS	316	.name = "versatilepb",
	317	.desc = "ARM Versatile/PB (ARM926EJ-S)",
	318	.init = vpb_init,
	319	.use_scsi = 1,
cdbdb648	320	};
16406950	321
f80f9ec9	322	static QEMUMachine versatileab_machine = {
c9b1ae2c BS	323	.name = "versatileab",
	324	.desc = "ARM Versatile/AB (ARM926EJ-S)",
	325	.init = vab_init,
	326	.use_scsi = 1,
16406950	327	};
3950f18b	328
f80f9ec9 AL	329	static void versatile_machine_init(void)
	330	{
	331	qemu_register_machine(&versatilepb_machine);
	332	qemu_register_machine(&versatileab_machine);
	333	}
	334
	335	machine_init(versatile_machine_init);
	336
3950f18b PB	337	static void versatilepb_register_devices(void)
	338	{
	339	sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state),
	340	vpb_sic_init);
	341	}
	342
	343	device_init(versatilepb_register_devices)