[qemu.git] / target-i386 / misc_helper.c

/*
 *  x86 misc helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/ioport.h"
#include "helper.h"

#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */

/* check if Port I/O is allowed in TSS */
static inline void check_io(CPUX86State *env, int addr, int size)
{
    int io_offset, val, mask;

    /* TSS must be a valid 32 bit one */
    if (!(env->tr.flags & DESC_P_MASK) ||
        ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
        env->tr.limit < 103) {
        goto fail;
    }
    io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
    io_offset += (addr >> 3);
    /* Note: the check needs two bytes */
    if ((io_offset + 1) > env->tr.limit) {
        goto fail;
    }
    val = cpu_lduw_kernel(env, env->tr.base + io_offset);
    val >>= (addr & 7);
    mask = (1 << size) - 1;
    /* all bits must be zero to allow the I/O */
    if ((val & mask) != 0) {
    fail:
        raise_exception_err(env, EXCP0D_GPF, 0);
    }
}

void helper_check_iob(CPUX86State *env, uint32_t t0)
{
    check_io(env, t0, 1);
}

void helper_check_iow(CPUX86State *env, uint32_t t0)
{
    check_io(env, t0, 2);
}

void helper_check_iol(CPUX86State *env, uint32_t t0)
{
    check_io(env, t0, 4);
}

void helper_outb(uint32_t port, uint32_t data)
{
    cpu_outb(port, data & 0xff);
}

target_ulong helper_inb(uint32_t port)
{
    return cpu_inb(port);
}

void helper_outw(uint32_t port, uint32_t data)
{
    cpu_outw(port, data & 0xffff);
}

target_ulong helper_inw(uint32_t port)
{
    return cpu_inw(port);
}

void helper_outl(uint32_t port, uint32_t data)
{
    cpu_outl(port, data);
}

target_ulong helper_inl(uint32_t port)
{
    return cpu_inl(port);
}

void helper_into(CPUX86State *env, int next_eip_addend)
{
    int eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    if (eflags & CC_O) {
        raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
    }
}

void helper_single_step(CPUX86State *env)
{
#ifndef CONFIG_USER_ONLY
    check_hw_breakpoints(env, true);
    env->dr[6] |= DR6_BS;
#endif
    raise_exception(env, EXCP01_DB);
}

void helper_cpuid(CPUX86State *env)
{
    uint32_t eax, ebx, ecx, edx;

    cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);

    cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx);
    env->regs[R_EAX] = eax;
    env->regs[R_EBX] = ebx;
    env->regs[R_ECX] = ecx;
    env->regs[R_EDX] = edx;
}

#if defined(CONFIG_USER_ONLY)
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    return 0;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
}

void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
}
#else
target_ulong helper_read_crN(CPUX86State *env, int reg)
{
    target_ulong val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
    switch (reg) {
    default:
        val = env->cr[reg];
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            val = cpu_get_apic_tpr(env->apic_state);
        } else {
            val = env->v_tpr;
        }
        break;
    }
    return val;
}

void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
    switch (reg) {
    case 0:
        cpu_x86_update_cr0(env, t0);
        break;
    case 3:
        cpu_x86_update_cr3(env, t0);
        break;
    case 4:
        cpu_x86_update_cr4(env, t0);
        break;
    case 8:
        if (!(env->hflags2 & HF2_VINTR_MASK)) {
            cpu_set_apic_tpr(env->apic_state, t0);
        }
        env->v_tpr = t0 & 0x0f;
        break;
    default:
        env->cr[reg] = t0;
        break;
    }
}

void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
    int i;

    if (reg < 4) {
        hw_breakpoint_remove(env, reg);
        env->dr[reg] = t0;
        hw_breakpoint_insert(env, reg);
    } else if (reg == 7) {
        for (i = 0; i < DR7_MAX_BP; i++) {
            hw_breakpoint_remove(env, i);
        }
        env->dr[7] = t0;
        for (i = 0; i < DR7_MAX_BP; i++) {
            hw_breakpoint_insert(env, i);
        }
    } else {
        env->dr[reg] = t0;
    }
}
#endif

void helper_lmsw(CPUX86State *env, target_ulong t0)
{
    /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
       if already set to one. */
    t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
    helper_write_crN(env, 0, t0);
}

void helper_invlpg(CPUX86State *env, target_ulong addr)
{
    cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
    tlb_flush_page(env, addr);
}

void helper_rdtsc(CPUX86State *env)
{
    uint64_t val;

    if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception(env, EXCP0D_GPF);
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);

    val = cpu_get_tsc(env) + env->tsc_offset;
    env->regs[R_EAX] = (uint32_t)(val);
    env->regs[R_EDX] = (uint32_t)(val >> 32);
}

void helper_rdtscp(CPUX86State *env)
{
    helper_rdtsc(env);
    env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
}

void helper_rdpmc(CPUX86State *env)
{
    if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
        raise_exception(env, EXCP0D_GPF);
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);

    /* currently unimplemented */
    qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
    raise_exception_err(env, EXCP06_ILLOP, 0);
}

#if defined(CONFIG_USER_ONLY)
void helper_wrmsr(CPUX86State *env)
{
}

void helper_rdmsr(CPUX86State *env)
{
}
#else
void helper_wrmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);

    val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);

    switch ((uint32_t)env->regs[R_ECX]) {
    case MSR_IA32_SYSENTER_CS:
        env->sysenter_cs = val & 0xffff;
        break;
    case MSR_IA32_SYSENTER_ESP:
        env->sysenter_esp = val;
        break;
    case MSR_IA32_SYSENTER_EIP:
        env->sysenter_eip = val;
        break;
    case MSR_IA32_APICBASE:
        cpu_set_apic_base(env->apic_state, val);
        break;
    case MSR_EFER:
        {
            uint64_t update_mask;

            update_mask = 0;
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
                update_mask |= MSR_EFER_SCE;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
                update_mask |= MSR_EFER_LME;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
                update_mask |= MSR_EFER_NXE;
            }
            if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
                update_mask |= MSR_EFER_SVME;
            }
            if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
                update_mask |= MSR_EFER_FFXSR;
            }
            cpu_load_efer(env, (env->efer & ~update_mask) |
                          (val & update_mask));
        }
        break;
    case MSR_STAR:
        env->star = val;
        break;
    case MSR_PAT:
        env->pat = val;
        break;
    case MSR_VM_HSAVE_PA:
        env->vm_hsave = val;
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        env->lstar = val;
        break;
    case MSR_CSTAR:
        env->cstar = val;
        break;
    case MSR_FMASK:
        env->fmask = val;
        break;
    case MSR_FSBASE:
        env->segs[R_FS].base = val;
        break;
    case MSR_GSBASE:
        env->segs[R_GS].base = val;
        break;
    case MSR_KERNELGSBASE:
        env->kernelgsbase = val;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val;
        break;
    case MSR_MTRRfix64K_00000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val;
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val;
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val;
        break;
    case MSR_MTRRdefType:
        env->mtrr_deftype = val;
        break;
    case MSR_MCG_STATUS:
        env->mcg_status = val;
        break;
    case MSR_MCG_CTL:
        if ((env->mcg_cap & MCG_CTL_P)
            && (val == 0 || val == ~(uint64_t)0)) {
            env->mcg_ctl = val;
        }
        break;
    case MSR_TSC_AUX:
        env->tsc_aux = val;
        break;
    case MSR_IA32_MISC_ENABLE:
        env->msr_ia32_misc_enable = val;
        break;
    default:
        if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
            && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
            if ((offset & 0x3) != 0
                || (val == 0 || val == ~(uint64_t)0)) {
                env->mce_banks[offset] = val;
            }
            break;
        }
        /* XXX: exception? */
        break;
    }
}

void helper_rdmsr(CPUX86State *env)
{
    uint64_t val;

    cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);

    switch ((uint32_t)env->regs[R_ECX]) {
    case MSR_IA32_SYSENTER_CS:
        val = env->sysenter_cs;
        break;
    case MSR_IA32_SYSENTER_ESP:
        val = env->sysenter_esp;
        break;
    case MSR_IA32_SYSENTER_EIP:
        val = env->sysenter_eip;
        break;
    case MSR_IA32_APICBASE:
        val = cpu_get_apic_base(env->apic_state);
        break;
    case MSR_EFER:
        val = env->efer;
        break;
    case MSR_STAR:
        val = env->star;
        break;
    case MSR_PAT:
        val = env->pat;
        break;
    case MSR_VM_HSAVE_PA:
        val = env->vm_hsave;
        break;
    case MSR_IA32_PERF_STATUS:
        /* tsc_increment_by_tick */
        val = 1000ULL;
        /* CPU multiplier */
        val |= (((uint64_t)4ULL) << 40);
        break;
#ifdef TARGET_X86_64
    case MSR_LSTAR:
        val = env->lstar;
        break;
    case MSR_CSTAR:
        val = env->cstar;
        break;
    case MSR_FMASK:
        val = env->fmask;
        break;
    case MSR_FSBASE:
        val = env->segs[R_FS].base;
        break;
    case MSR_GSBASE:
        val = env->segs[R_GS].base;
        break;
    case MSR_KERNELGSBASE:
        val = env->kernelgsbase;
        break;
    case MSR_TSC_AUX:
        val = env->tsc_aux;
        break;
#endif
    case MSR_MTRRphysBase(0):
    case MSR_MTRRphysBase(1):
    case MSR_MTRRphysBase(2):
    case MSR_MTRRphysBase(3):
    case MSR_MTRRphysBase(4):
    case MSR_MTRRphysBase(5):
    case MSR_MTRRphysBase(6):
    case MSR_MTRRphysBase(7):
        val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base;
        break;
    case MSR_MTRRphysMask(0):
    case MSR_MTRRphysMask(1):
    case MSR_MTRRphysMask(2):
    case MSR_MTRRphysMask(3):
    case MSR_MTRRphysMask(4):
    case MSR_MTRRphysMask(5):
    case MSR_MTRRphysMask(6):
    case MSR_MTRRphysMask(7):
        val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask;
        break;
    case MSR_MTRRfix64K_00000:
        val = env->mtrr_fixed[0];
        break;
    case MSR_MTRRfix16K_80000:
    case MSR_MTRRfix16K_A0000:
        val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1];
        break;
    case MSR_MTRRfix4K_C0000:
    case MSR_MTRRfix4K_C8000:
    case MSR_MTRRfix4K_D0000:
    case MSR_MTRRfix4K_D8000:
    case MSR_MTRRfix4K_E0000:
    case MSR_MTRRfix4K_E8000:
    case MSR_MTRRfix4K_F0000:
    case MSR_MTRRfix4K_F8000:
        val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3];
        break;
    case MSR_MTRRdefType:
        val = env->mtrr_deftype;
        break;
    case MSR_MTRRcap:
        if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
            val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
                MSR_MTRRcap_WC_SUPPORTED;
        } else {
            /* XXX: exception? */
            val = 0;
        }
        break;
    case MSR_MCG_CAP:
        val = env->mcg_cap;
        break;
    case MSR_MCG_CTL:
        if (env->mcg_cap & MCG_CTL_P) {
            val = env->mcg_ctl;
        } else {
            val = 0;
        }
        break;
    case MSR_MCG_STATUS:
        val = env->mcg_status;
        break;
    case MSR_IA32_MISC_ENABLE:
        val = env->msr_ia32_misc_enable;
        break;
    default:
        if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
            && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
            uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
            val = env->mce_banks[offset];
            break;
        }
        /* XXX: exception? */
        val = 0;
        break;
    }
    env->regs[R_EAX] = (uint32_t)(val);
    env->regs[R_EDX] = (uint32_t)(val >> 32);
}
#endif

static void do_hlt(X86CPU *cpu)
{
    CPUState *cs = CPU(cpu);
    CPUX86State *env = &cpu->env;

    env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
    cs->halted = 1;
    env->exception_index = EXCP_HLT;
    cpu_loop_exit(env);
}

void helper_hlt(CPUX86State *env, int next_eip_addend)
{
    X86CPU *cpu = x86_env_get_cpu(env);

    cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
    EIP += next_eip_addend;

    do_hlt(cpu);
}

void helper_monitor(CPUX86State *env, target_ulong ptr)
{
    if ((uint32_t)env->regs[R_ECX] != 0) {
        raise_exception(env, EXCP0D_GPF);
    }
    /* XXX: store address? */
    cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
}

void helper_mwait(CPUX86State *env, int next_eip_addend)
{
    CPUState *cs;
    X86CPU *cpu;

    if ((uint32_t)env->regs[R_ECX] != 0) {
        raise_exception(env, EXCP0D_GPF);
    }
    cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
    EIP += next_eip_addend;

    cpu = x86_env_get_cpu(env);
    cs = CPU(cpu);
    /* XXX: not complete but not completely erroneous */
    if (cs->cpu_index != 0 || env->next_cpu != NULL) {
        /* more than one CPU: do not sleep because another CPU may
           wake this one */
    } else {
        do_hlt(cpu);
    }
}

void helper_debug(CPUX86State *env)
{
    env->exception_index = EXCP_DEBUG;
    cpu_loop_exit(env);
}
Commit	Line	Data
f7b2429f BS	1	/*
	2	* x86 misc helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
022c62cb	21	#include "exec/ioport.h"
f7b2429f BS	22	#include "helper.h"
f7b2429f BS	23
92fc4b58	24	#if !defined(CONFIG_USER_ONLY)
022c62cb	25	#include "exec/softmmu_exec.h"
92fc4b58 BS	26	#endif /* !defined(CONFIG_USER_ONLY) */
92fc4b58 BS	27
f7b2429f	28	/* check if Port I/O is allowed in TSS */
4a7443be	29	static inline void check_io(CPUX86State *env, int addr, int size)
f7b2429f BS	30	{
	31	int io_offset, val, mask;
	32
	33	/* TSS must be a valid 32 bit one */
	34	if (!(env->tr.flags & DESC_P_MASK) \|\|
	35	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
	36	env->tr.limit < 103) {
	37	goto fail;
	38	}
4a7443be	39	io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
f7b2429f BS	40	io_offset += (addr >> 3);
	41	/* Note: the check needs two bytes */
	42	if ((io_offset + 1) > env->tr.limit) {
	43	goto fail;
	44	}
4a7443be	45	val = cpu_lduw_kernel(env, env->tr.base + io_offset);
f7b2429f BS	46	val >>= (addr & 7);
	47	mask = (1 << size) - 1;
	48	/* all bits must be zero to allow the I/O */
	49	if ((val & mask) != 0) {
	50	fail:
	51	raise_exception_err(env, EXCP0D_GPF, 0);
	52	}
	53	}
	54
4a7443be	55	void helper_check_iob(CPUX86State *env, uint32_t t0)
f7b2429f	56	{
4a7443be	57	check_io(env, t0, 1);
f7b2429f BS	58	}
f7b2429f BS	59
4a7443be	60	void helper_check_iow(CPUX86State *env, uint32_t t0)
f7b2429f	61	{
4a7443be	62	check_io(env, t0, 2);
f7b2429f BS	63	}
f7b2429f BS	64
4a7443be	65	void helper_check_iol(CPUX86State *env, uint32_t t0)
f7b2429f	66	{
4a7443be	67	check_io(env, t0, 4);
f7b2429f BS	68	}
	69
	70	void helper_outb(uint32_t port, uint32_t data)
	71	{
	72	cpu_outb(port, data & 0xff);
	73	}
	74
	75	target_ulong helper_inb(uint32_t port)
	76	{
	77	return cpu_inb(port);
	78	}
	79
	80	void helper_outw(uint32_t port, uint32_t data)
	81	{
	82	cpu_outw(port, data & 0xffff);
	83	}
	84
	85	target_ulong helper_inw(uint32_t port)
	86	{
	87	return cpu_inw(port);
	88	}
	89
	90	void helper_outl(uint32_t port, uint32_t data)
	91	{
	92	cpu_outl(port, data);
	93	}
	94
	95	target_ulong helper_inl(uint32_t port)
	96	{
	97	return cpu_inl(port);
	98	}
	99
4a7443be	100	void helper_into(CPUX86State *env, int next_eip_addend)
f7b2429f BS	101	{
	102	int eflags;
	103
f0967a1a	104	eflags = cpu_cc_compute_all(env, CC_OP);
f7b2429f BS	105	if (eflags & CC_O) {
	106	raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
	107	}
	108	}
	109
4a7443be	110	void helper_single_step(CPUX86State *env)
f7b2429f BS	111	{
f7b2429f BS	112	#ifndef CONFIG_USER_ONLY
e175bce5	113	check_hw_breakpoints(env, true);
f7b2429f BS	114	env->dr[6] \|= DR6_BS;
	115	#endif
	116	raise_exception(env, EXCP01_DB);
	117	}
	118
4a7443be	119	void helper_cpuid(CPUX86State *env)
f7b2429f BS	120	{
	121	uint32_t eax, ebx, ecx, edx;
	122
	123	cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
	124
a4165610	125	cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx);
4b34e3ad	126	env->regs[R_EAX] = eax;
70b51365	127	env->regs[R_EBX] = ebx;
a4165610	128	env->regs[R_ECX] = ecx;
00f5e6f2	129	env->regs[R_EDX] = edx;
f7b2429f BS	130	}
	131
	132	#if defined(CONFIG_USER_ONLY)
4a7443be	133	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	134	{
	135	return 0;
	136	}
	137
4a7443be	138	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	139	{
	140	}
	141
4a7443be	142	void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	143	{
	144	}
	145	#else
4a7443be	146	target_ulong helper_read_crN(CPUX86State *env, int reg)
f7b2429f BS	147	{
	148	target_ulong val;
	149
	150	cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
	151	switch (reg) {
	152	default:
	153	val = env->cr[reg];
	154	break;
	155	case 8:
	156	if (!(env->hflags2 & HF2_VINTR_MASK)) {
	157	val = cpu_get_apic_tpr(env->apic_state);
	158	} else {
	159	val = env->v_tpr;
	160	}
	161	break;
	162	}
	163	return val;
	164	}
	165
4a7443be	166	void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	167	{
	168	cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
	169	switch (reg) {
	170	case 0:
	171	cpu_x86_update_cr0(env, t0);
	172	break;
	173	case 3:
	174	cpu_x86_update_cr3(env, t0);
	175	break;
	176	case 4:
	177	cpu_x86_update_cr4(env, t0);
	178	break;
	179	case 8:
	180	if (!(env->hflags2 & HF2_VINTR_MASK)) {
	181	cpu_set_apic_tpr(env->apic_state, t0);
	182	}
	183	env->v_tpr = t0 & 0x0f;
	184	break;
	185	default:
	186	env->cr[reg] = t0;
	187	break;
	188	}
	189	}
	190
4a7443be	191	void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
f7b2429f BS	192	{
	193	int i;
	194
	195	if (reg < 4) {
	196	hw_breakpoint_remove(env, reg);
	197	env->dr[reg] = t0;
	198	hw_breakpoint_insert(env, reg);
	199	} else if (reg == 7) {
428065ce	200	for (i = 0; i < DR7_MAX_BP; i++) {
f7b2429f BS	201	hw_breakpoint_remove(env, i);
	202	}
	203	env->dr[7] = t0;
428065ce	204	for (i = 0; i < DR7_MAX_BP; i++) {
f7b2429f BS	205	hw_breakpoint_insert(env, i);
	206	}
	207	} else {
	208	env->dr[reg] = t0;
	209	}
	210	}
	211	#endif
	212
4a7443be	213	void helper_lmsw(CPUX86State *env, target_ulong t0)
f7b2429f BS	214	{
	215	/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
	216	if already set to one. */
	217	t0 = (env->cr[0] & ~0xe) \| (t0 & 0xf);
4a7443be	218	helper_write_crN(env, 0, t0);
f7b2429f BS	219	}
f7b2429f BS	220
4a7443be	221	void helper_invlpg(CPUX86State *env, target_ulong addr)
f7b2429f BS	222	{
	223	cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
	224	tlb_flush_page(env, addr);
	225	}
	226
4a7443be	227	void helper_rdtsc(CPUX86State *env)
f7b2429f BS	228	{
	229	uint64_t val;
	230
	231	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
	232	raise_exception(env, EXCP0D_GPF);
	233	}
	234	cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
	235
	236	val = cpu_get_tsc(env) + env->tsc_offset;
4b34e3ad	237	env->regs[R_EAX] = (uint32_t)(val);
00f5e6f2	238	env->regs[R_EDX] = (uint32_t)(val >> 32);
f7b2429f BS	239	}
f7b2429f BS	240
4a7443be	241	void helper_rdtscp(CPUX86State *env)
f7b2429f	242	{
4a7443be	243	helper_rdtsc(env);
a4165610	244	env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
f7b2429f BS	245	}
f7b2429f BS	246
4a7443be	247	void helper_rdpmc(CPUX86State *env)
f7b2429f BS	248	{
	249	if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
	250	raise_exception(env, EXCP0D_GPF);
	251	}
	252	cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
	253
	254	/* currently unimplemented */
	255	qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
	256	raise_exception_err(env, EXCP06_ILLOP, 0);
	257	}
	258
	259	#if defined(CONFIG_USER_ONLY)
4a7443be	260	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	261	{
	262	}
	263
4a7443be	264	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	265	{
	266	}
	267	#else
4a7443be	268	void helper_wrmsr(CPUX86State *env)
f7b2429f BS	269	{
	270	uint64_t val;
	271
	272	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
	273
00f5e6f2	274	val = ((uint32_t)env->regs[R_EAX]) \| ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
f7b2429f	275
a4165610	276	switch ((uint32_t)env->regs[R_ECX]) {
f7b2429f BS	277	case MSR_IA32_SYSENTER_CS:
	278	env->sysenter_cs = val & 0xffff;
	279	break;
	280	case MSR_IA32_SYSENTER_ESP:
	281	env->sysenter_esp = val;
	282	break;
	283	case MSR_IA32_SYSENTER_EIP:
	284	env->sysenter_eip = val;
	285	break;
	286	case MSR_IA32_APICBASE:
	287	cpu_set_apic_base(env->apic_state, val);
	288	break;
	289	case MSR_EFER:
	290	{
	291	uint64_t update_mask;
	292
	293	update_mask = 0;
0514ef2f	294	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
f7b2429f BS	295	update_mask \|= MSR_EFER_SCE;
f7b2429f BS	296	}
0514ef2f	297	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
f7b2429f BS	298	update_mask \|= MSR_EFER_LME;
f7b2429f BS	299	}
0514ef2f	300	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
f7b2429f BS	301	update_mask \|= MSR_EFER_FFXSR;
f7b2429f BS	302	}
0514ef2f	303	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
f7b2429f BS	304	update_mask \|= MSR_EFER_NXE;
f7b2429f BS	305	}
0514ef2f	306	if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
f7b2429f BS	307	update_mask \|= MSR_EFER_SVME;
f7b2429f BS	308	}
0514ef2f	309	if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
f7b2429f BS	310	update_mask \|= MSR_EFER_FFXSR;
	311	}
	312	cpu_load_efer(env, (env->efer & ~update_mask) \|
	313	(val & update_mask));
	314	}
	315	break;
	316	case MSR_STAR:
	317	env->star = val;
	318	break;
	319	case MSR_PAT:
	320	env->pat = val;
	321	break;
	322	case MSR_VM_HSAVE_PA:
	323	env->vm_hsave = val;
	324	break;
	325	#ifdef TARGET_X86_64
	326	case MSR_LSTAR:
	327	env->lstar = val;
	328	break;
	329	case MSR_CSTAR:
	330	env->cstar = val;
	331	break;
	332	case MSR_FMASK:
	333	env->fmask = val;
	334	break;
	335	case MSR_FSBASE:
	336	env->segs[R_FS].base = val;
	337	break;
	338	case MSR_GSBASE:
	339	env->segs[R_GS].base = val;
	340	break;
	341	case MSR_KERNELGSBASE:
	342	env->kernelgsbase = val;
	343	break;
	344	#endif
	345	case MSR_MTRRphysBase(0):
	346	case MSR_MTRRphysBase(1):
	347	case MSR_MTRRphysBase(2):
	348	case MSR_MTRRphysBase(3):
	349	case MSR_MTRRphysBase(4):
	350	case MSR_MTRRphysBase(5):
	351	case MSR_MTRRphysBase(6):
	352	case MSR_MTRRphysBase(7):
a4165610	353	env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val;
f7b2429f BS	354	break;
	355	case MSR_MTRRphysMask(0):
	356	case MSR_MTRRphysMask(1):
	357	case MSR_MTRRphysMask(2):
	358	case MSR_MTRRphysMask(3):
	359	case MSR_MTRRphysMask(4):
	360	case MSR_MTRRphysMask(5):
	361	case MSR_MTRRphysMask(6):
	362	case MSR_MTRRphysMask(7):
a4165610	363	env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val;
f7b2429f BS	364	break;
f7b2429f BS	365	case MSR_MTRRfix64K_00000:
a4165610	366	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val;
f7b2429f BS	367	break;
	368	case MSR_MTRRfix16K_80000:
	369	case MSR_MTRRfix16K_A0000:
a4165610	370	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val;
f7b2429f BS	371	break;
	372	case MSR_MTRRfix4K_C0000:
	373	case MSR_MTRRfix4K_C8000:
	374	case MSR_MTRRfix4K_D0000:
	375	case MSR_MTRRfix4K_D8000:
	376	case MSR_MTRRfix4K_E0000:
	377	case MSR_MTRRfix4K_E8000:
	378	case MSR_MTRRfix4K_F0000:
	379	case MSR_MTRRfix4K_F8000:
a4165610	380	env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val;
f7b2429f BS	381	break;
	382	case MSR_MTRRdefType:
	383	env->mtrr_deftype = val;
	384	break;
	385	case MSR_MCG_STATUS:
	386	env->mcg_status = val;
	387	break;
	388	case MSR_MCG_CTL:
	389	if ((env->mcg_cap & MCG_CTL_P)
	390	&& (val == 0 \|\| val == ~(uint64_t)0)) {
	391	env->mcg_ctl = val;
	392	}
	393	break;
	394	case MSR_TSC_AUX:
	395	env->tsc_aux = val;
	396	break;
	397	case MSR_IA32_MISC_ENABLE:
	398	env->msr_ia32_misc_enable = val;
	399	break;
	400	default:
a4165610 LG	401	if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
	402	&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
	403	uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
f7b2429f BS	404	if ((offset & 0x3) != 0
	405	\|\| (val == 0 \|\| val == ~(uint64_t)0)) {
	406	env->mce_banks[offset] = val;
	407	}
	408	break;
	409	}
	410	/* XXX: exception? */
	411	break;
	412	}
	413	}
	414
4a7443be	415	void helper_rdmsr(CPUX86State *env)
f7b2429f BS	416	{
	417	uint64_t val;
	418
	419	cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
	420
a4165610	421	switch ((uint32_t)env->regs[R_ECX]) {
f7b2429f BS	422	case MSR_IA32_SYSENTER_CS:
	423	val = env->sysenter_cs;
	424	break;
	425	case MSR_IA32_SYSENTER_ESP:
	426	val = env->sysenter_esp;
	427	break;
	428	case MSR_IA32_SYSENTER_EIP:
	429	val = env->sysenter_eip;
	430	break;
	431	case MSR_IA32_APICBASE:
	432	val = cpu_get_apic_base(env->apic_state);
	433	break;
	434	case MSR_EFER:
	435	val = env->efer;
	436	break;
	437	case MSR_STAR:
	438	val = env->star;
	439	break;
	440	case MSR_PAT:
	441	val = env->pat;
	442	break;
	443	case MSR_VM_HSAVE_PA:
	444	val = env->vm_hsave;
	445	break;
	446	case MSR_IA32_PERF_STATUS:
	447	/* tsc_increment_by_tick */
	448	val = 1000ULL;
	449	/* CPU multiplier */
	450	val \|= (((uint64_t)4ULL) << 40);
	451	break;
	452	#ifdef TARGET_X86_64
	453	case MSR_LSTAR:
	454	val = env->lstar;
	455	break;
	456	case MSR_CSTAR:
	457	val = env->cstar;
	458	break;
	459	case MSR_FMASK:
	460	val = env->fmask;
	461	break;
	462	case MSR_FSBASE:
	463	val = env->segs[R_FS].base;
	464	break;
	465	case MSR_GSBASE:
	466	val = env->segs[R_GS].base;
	467	break;
	468	case MSR_KERNELGSBASE:
	469	val = env->kernelgsbase;
	470	break;
	471	case MSR_TSC_AUX:
	472	val = env->tsc_aux;
	473	break;
	474	#endif
	475	case MSR_MTRRphysBase(0):
	476	case MSR_MTRRphysBase(1):
	477	case MSR_MTRRphysBase(2):
	478	case MSR_MTRRphysBase(3):
	479	case MSR_MTRRphysBase(4):
	480	case MSR_MTRRphysBase(5):
	481	case MSR_MTRRphysBase(6):
	482	case MSR_MTRRphysBase(7):
a4165610	483	val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base;
f7b2429f BS	484	break;
	485	case MSR_MTRRphysMask(0):
	486	case MSR_MTRRphysMask(1):
	487	case MSR_MTRRphysMask(2):
	488	case MSR_MTRRphysMask(3):
	489	case MSR_MTRRphysMask(4):
	490	case MSR_MTRRphysMask(5):
	491	case MSR_MTRRphysMask(6):
	492	case MSR_MTRRphysMask(7):
a4165610	493	val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask;
f7b2429f BS	494	break;
	495	case MSR_MTRRfix64K_00000:
	496	val = env->mtrr_fixed[0];
	497	break;
	498	case MSR_MTRRfix16K_80000:
	499	case MSR_MTRRfix16K_A0000:
a4165610	500	val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1];
f7b2429f BS	501	break;
	502	case MSR_MTRRfix4K_C0000:
	503	case MSR_MTRRfix4K_C8000:
	504	case MSR_MTRRfix4K_D0000:
	505	case MSR_MTRRfix4K_D8000:
	506	case MSR_MTRRfix4K_E0000:
	507	case MSR_MTRRfix4K_E8000:
	508	case MSR_MTRRfix4K_F0000:
	509	case MSR_MTRRfix4K_F8000:
a4165610	510	val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3];
f7b2429f BS	511	break;
	512	case MSR_MTRRdefType:
	513	val = env->mtrr_deftype;
	514	break;
	515	case MSR_MTRRcap:
0514ef2f	516	if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
f7b2429f BS	517	val = MSR_MTRRcap_VCNT \| MSR_MTRRcap_FIXRANGE_SUPPORT \|
	518	MSR_MTRRcap_WC_SUPPORTED;
	519	} else {
	520	/* XXX: exception? */
	521	val = 0;
	522	}
	523	break;
	524	case MSR_MCG_CAP:
	525	val = env->mcg_cap;
	526	break;
	527	case MSR_MCG_CTL:
	528	if (env->mcg_cap & MCG_CTL_P) {
	529	val = env->mcg_ctl;
	530	} else {
	531	val = 0;
	532	}
	533	break;
	534	case MSR_MCG_STATUS:
	535	val = env->mcg_status;
	536	break;
	537	case MSR_IA32_MISC_ENABLE:
	538	val = env->msr_ia32_misc_enable;
	539	break;
	540	default:
a4165610 LG	541	if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
	542	&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
	543	uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
f7b2429f BS	544	val = env->mce_banks[offset];
	545	break;
	546	}
	547	/* XXX: exception? */
	548	val = 0;
	549	break;
	550	}
4b34e3ad	551	env->regs[R_EAX] = (uint32_t)(val);
00f5e6f2	552	env->regs[R_EDX] = (uint32_t)(val >> 32);
f7b2429f BS	553	}
	554	#endif
	555
259186a7	556	static void do_hlt(X86CPU *cpu)
f7b2429f	557	{
259186a7 AF	558	CPUState *cs = CPU(cpu);
	559	CPUX86State *env = &cpu->env;
	560
f7b2429f	561	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
259186a7	562	cs->halted = 1;
f7b2429f BS	563	env->exception_index = EXCP_HLT;
	564	cpu_loop_exit(env);
	565	}
	566
4a7443be	567	void helper_hlt(CPUX86State *env, int next_eip_addend)
f7b2429f	568	{
259186a7 AF	569	X86CPU *cpu = x86_env_get_cpu(env);
259186a7 AF	570
f7b2429f BS	571	cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
	572	EIP += next_eip_addend;
	573
259186a7	574	do_hlt(cpu);
f7b2429f BS	575	}
f7b2429f BS	576
4a7443be	577	void helper_monitor(CPUX86State *env, target_ulong ptr)
f7b2429f	578	{
a4165610	579	if ((uint32_t)env->regs[R_ECX] != 0) {
f7b2429f BS	580	raise_exception(env, EXCP0D_GPF);
	581	}
	582	/* XXX: store address? */
	583	cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
	584	}
	585
4a7443be	586	void helper_mwait(CPUX86State *env, int next_eip_addend)
f7b2429f	587	{
259186a7 AF	588	CPUState *cs;
259186a7 AF	589	X86CPU *cpu;
55e5c285	590
a4165610	591	if ((uint32_t)env->regs[R_ECX] != 0) {
f7b2429f BS	592	raise_exception(env, EXCP0D_GPF);
	593	}
	594	cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
	595	EIP += next_eip_addend;
	596
259186a7 AF	597	cpu = x86_env_get_cpu(env);
259186a7 AF	598	cs = CPU(cpu);
f7b2429f	599	/* XXX: not complete but not completely erroneous */
259186a7	600	if (cs->cpu_index != 0 \|\| env->next_cpu != NULL) {
f7b2429f BS	601	/* more than one CPU: do not sleep because another CPU may
	602	wake this one */
	603	} else {
259186a7	604	do_hlt(cpu);
f7b2429f BS	605	}
	606	}
	607
4a7443be	608	void helper_debug(CPUX86State *env)
f7b2429f BS	609	{
	610	env->exception_index = EXCP_DEBUG;
	611	cpu_loop_exit(env);
	612	}