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<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span> </div>
-<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">/*</span></div>
-<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment"> * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.</span></div>
-<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment"> *</span></div>
-<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment"> * SPDX-License-Identifier: BSD-3-Clause</span></div>
-<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment"> */</span></div>
-<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div>
-<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_SCB_H</span></div>
-<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="preprocessor">#define _HARDWARE_STRUCTS_SCB_H</span></div>
-<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span> </div>
-<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="preprocessor">#include "<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>"</span></div>
-<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span><span class="preprocessor">#include "hardware/regs/m0plus.h"</span></div>
-<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span> </div>
-<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus</span></div>
-<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">//</span></div>
-<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)</span></div>
-<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.</span></div>
-<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">//</span></div>
-<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
-<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION</span></div>
-<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div>
-<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"><a class="line" href="structarmv6m__scb__t.html"> 23</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
-<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span> _REG_(M0PLUS_CPUID_OFFSET) <span class="comment">// M0PLUS_CPUID</span></div>
-<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span> <span class="comment">// Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor...</span></div>
-<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> <span class="comment">// 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM</span></div>
-<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> <span class="comment">// 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status:</span></div>
-<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> <span class="comment">// 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor:</span></div>
-<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> <span class="comment">// 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+</span></div>
-<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span> <span class="comment">// 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status:</span></div>
-<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> io_ro_32 cpuid;</div>
-<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> </div>
-<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> _REG_(M0PLUS_ICSR_OFFSET) <span class="comment">// M0PLUS_ICSR</span></div>
-<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> <span class="comment">// Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending...</span></div>
-<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> <span class="comment">// 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI</span></div>
-<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> <span class="comment">// 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit</span></div>
-<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> <span class="comment">// 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit</span></div>
-<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> <span class="comment">// 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit</span></div>
-<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> <span class="comment">// 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit</span></div>
-<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> <span class="comment">// 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted</span></div>
-<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> <span class="comment">// 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag</span></div>
-<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> <span class="comment">// 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =...</span></div>
-<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> <span class="comment">// 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field</span></div>
-<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> io_rw_32 icsr;</div>
-<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span> </div>
-<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> _REG_(M0PLUS_VTOR_OFFSET) <span class="comment">// M0PLUS_VTOR</span></div>
-<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> <span class="comment">// The VTOR holds the vector table offset address</span></div>
-<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <span class="comment">// 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address</span></div>
-<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span> io_rw_32 vtor;</div>
-<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> </div>
-<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span> _REG_(M0PLUS_AIRCR_OFFSET) <span class="comment">// M0PLUS_AIRCR</span></div>
-<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> <span class="comment">// Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state...</span></div>
-<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> <span class="comment">// 0xffff0000 [31:16] : VECTKEY (0): Register key:</span></div>
-<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> <span class="comment">// 0x00008000 [15] : ENDIANESS (0): Data endianness implemented:</span></div>
-<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> <span class="comment">// 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be...</span></div>
-<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> <span class="comment">// 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions</span></div>
-<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> io_rw_32 aircr;</div>
-<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> </div>
-<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> _REG_(M0PLUS_SCR_OFFSET) <span class="comment">// M0PLUS_SCR</span></div>
-<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> <span class="comment">// System Control Register</span></div>
-<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span> <span class="comment">// 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit:</span></div>
-<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> <span class="comment">// 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode:</span></div>
-<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> <span class="comment">// 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode:</span></div>
-<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> io_rw_32 scr;</div>
-<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span>} <a class="code hl_struct" href="structarmv6m__scb__t.html">armv6m_scb_t</a>;</div>
-<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> </div>
-<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span><span class="preprocessor">#define scb_hw ((armv6m_scb_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))</span></div>
+<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_SCB_H</span></div>
+<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_SCB_H</span></div>
+<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span> </div>
+<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="preprocessor">#include "<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>"</span></div>
+<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="preprocessor">#include "hardware/regs/m33.h"</span></div>
+<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span> </div>
+<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33</span></div>
+<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">//</span></div>
+<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)</span></div>
+<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.</span></div>
+<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">//</span></div>
+<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
+<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
+<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div>
+<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="preprocessor">#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV</span></div>
+<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="preprocessor">#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"</span></div>
+<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="preprocessor">#endif</span></div>
+<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span> </div>
+<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structarmv8m__scb__hw__t.html"> 26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
+<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> _REG_(M33_CPUID_OFFSET) <span class="comment">// M33_CPUID</span></div>
+<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> <span class="comment">// Provides identification information for the PE, including an implementer code for the device and...</span></div>
+<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> <span class="comment">// 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been...</span></div>
+<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span> <span class="comment">// 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number</span></div>
+<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> <span class="comment">// 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE</span></div>
+<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> <span class="comment">// 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device</span></div>
+<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> <span class="comment">// 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device</span></div>
+<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> io_ro_32 cpuid;</div>
+<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> </div>
+<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> _REG_(M33_ICSR_OFFSET) <span class="comment">// M33_ICSR</span></div>
+<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> <span class="comment">// Controls and provides status information for NMI, PendSV, SysTick and interrupts</span></div>
+<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> <span class="comment">// 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending</span></div>
+<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> <span class="comment">// 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared</span></div>
+<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> <span class="comment">// 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending</span></div>
+<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> <span class="comment">// 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS</span></div>
+<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> <span class="comment">// 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending</span></div>
+<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> <span class="comment">// 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS</span></div>
+<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> <span class="comment">// 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the...</span></div>
+<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span> <span class="comment">// 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced...</span></div>
+<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> <span class="comment">// 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by...</span></div>
+<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> <span class="comment">// 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and...</span></div>
+<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <span class="comment">// 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than...</span></div>
+<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span> <span class="comment">// 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception</span></div>
+<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> io_rw_32 icsr;</div>
+<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span> </div>
+<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> _REG_(M33_VTOR_OFFSET) <span class="comment">// M33_VTOR</span></div>
+<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> <span class="comment">// Vector Table Offset Register</span></div>
+<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> <span class="comment">// 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field</span></div>
+<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> io_rw_32 vtor;</div>
+<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> </div>
+<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> _REG_(M33_AIRCR_OFFSET) <span class="comment">// M33_AIRCR</span></div>
+<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> <span class="comment">// Application Interrupt and Reset Control Register</span></div>
+<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> <span class="comment">// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +</span></div>
+<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> <span class="comment">// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +</span></div>
+<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span> <span class="comment">// 0x00004000 [14] PRIS (0) Prioritize Secure exceptions</span></div>
+<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> <span class="comment">// 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable</span></div>
+<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> <span class="comment">// 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field</span></div>
+<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> <span class="comment">// 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only</span></div>
+<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> <span class="comment">// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...</span></div>
+<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> <span class="comment">// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...</span></div>
+<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> io_rw_32 aircr;</div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span> </div>
-<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span><span class="preprocessor">#endif</span></div>
+<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span> _REG_(M33_SCR_OFFSET) <span class="comment">// M33_SCR</span></div>
+<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span> <span class="comment">// System Control Register</span></div>
+<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span> <span class="comment">// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +</span></div>
+<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> <span class="comment">// 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states +</span></div>
+<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> <span class="comment">// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...</span></div>
+<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> <span class="comment">// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...</span></div>
+<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span> io_rw_32 scr;</div>
+<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> </div>
+<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span> _REG_(M33_CCR_OFFSET) <span class="comment">// M33_CCR</span></div>
+<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span> <span class="comment">// Sets or returns configuration and control data</span></div>
+<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span> <span class="comment">// 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS</span></div>
+<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span> <span class="comment">// 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in...</span></div>
+<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span> <span class="comment">// 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS</span></div>
+<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> <span class="comment">// 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while...</span></div>
+<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> <span class="comment">// 0x00000200 [9] RES1 (1) Reserved, RES1</span></div>
+<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span> <span class="comment">// 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers...</span></div>
+<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span> <span class="comment">// 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when...</span></div>
+<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> <span class="comment">// 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses</span></div>
+<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> <span class="comment">// 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted...</span></div>
+<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span> <span class="comment">// 0x00000001 [0] RES1_1 (1) Reserved, RES1</span></div>
+<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span> io_rw_32 ccr;</div>
+<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> </div>
+<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> <span class="comment">// (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes)</span></div>
+<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span> _REG_(M33_SHPR1_OFFSET) <span class="comment">// M33_SHPR1</span></div>
+<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span> <span class="comment">// Sets or returns priority for system handlers 4 - 7</span></div>
+<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> <span class="comment">// 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault</span></div>
+<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> <span class="comment">// 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault</span></div>
+<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> <span class="comment">// 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault</span></div>
+<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> <span class="comment">// 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault</span></div>
+<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> io_rw_32 shpr[3];</div>
+<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> </div>
+<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> _REG_(M33_SHCSR_OFFSET) <span class="comment">// M33_SHCSR</span></div>
+<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> <span class="comment">// Provides access to the active and pending status of system exceptions</span></div>
+<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span> <span class="comment">// 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS</span></div>
+<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> <span class="comment">// 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception</span></div>
+<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span> <span class="comment">// 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled</span></div>
+<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span> <span class="comment">// 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS</span></div>
+<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span> <span class="comment">// 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled</span></div>
+<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> <span class="comment">// 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS</span></div>
+<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span> <span class="comment">// 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS</span></div>
+<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span> <span class="comment">// 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception</span></div>
+<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span> <span class="comment">// 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS</span></div>
+<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span> <span class="comment">// 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security...</span></div>
+<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span> <span class="comment">// 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS</span></div>
+<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span> <span class="comment">// 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS</span></div>
+<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span> <span class="comment">// 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception</span></div>
+<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span> <span class="comment">// 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS</span></div>
+<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span> <span class="comment">// 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception</span></div>
+<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span> <span class="comment">// 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception</span></div>
+<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span> <span class="comment">// 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS</span></div>
+<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span> <span class="comment">// 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active...</span></div>
+<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span> <span class="comment">// 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception</span></div>
+<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span> <span class="comment">// 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS</span></div>
+<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span> io_rw_32 shcsr;</div>
+<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span> </div>
+<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"> 124</span> _REG_(M33_CFSR_OFFSET) <span class="comment">// M33_CFSR</span></div>
+<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span> <span class="comment">// Contains the three Configurable Fault Status Registers</span></div>
+<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span> <span class="comment">// 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by...</span></div>
+<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"> 127</span> <span class="comment">// 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error...</span></div>
+<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"> 128</span> <span class="comment">// 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error...</span></div>
+<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"> 129</span> <span class="comment">// 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or...</span></div>
+<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"> 130</span> <span class="comment">// 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error...</span></div>
+<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"> 131</span> <span class="comment">// 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR</span></div>
+<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> <span class="comment">// 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction...</span></div>
+<div class="line"><a id="l00133" name="l00133"></a><span class="lineno"> 133</span> <span class="comment">// 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register</span></div>
+<div class="line"><a id="l00134" name="l00134"></a><span class="lineno"> 134</span> <span class="comment">// 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state...</span></div>
+<div class="line"><a id="l00135" name="l00135"></a><span class="lineno"> 135</span> <span class="comment">// 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during...</span></div>
+<div class="line"><a id="l00136" name="l00136"></a><span class="lineno"> 136</span> <span class="comment">// 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during...</span></div>
+<div class="line"><a id="l00137" name="l00137"></a><span class="lineno"> 137</span> <span class="comment">// 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred</span></div>
+<div class="line"><a id="l00138" name="l00138"></a><span class="lineno"> 138</span> <span class="comment">// 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred</span></div>
+<div class="line"><a id="l00139" name="l00139"></a><span class="lineno"> 139</span> <span class="comment">// 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch...</span></div>
+<div class="line"><a id="l00140" name="l00140"></a><span class="lineno"> 140</span> <span class="comment">// 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions</span></div>
+<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"> 141</span> io_rw_32 cfsr;</div>
+<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> </div>
+<div class="line"><a id="l00143" name="l00143"></a><span class="lineno"> 143</span> _REG_(M33_HFSR_OFFSET) <span class="comment">// M33_HFSR</span></div>
+<div class="line"><a id="l00144" name="l00144"></a><span class="lineno"> 144</span> <span class="comment">// Shows the cause of any HardFaults</span></div>
+<div class="line"><a id="l00145" name="l00145"></a><span class="lineno"> 145</span> <span class="comment">// 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred</span></div>
+<div class="line"><a id="l00146" name="l00146"></a><span class="lineno"> 146</span> <span class="comment">// 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has...</span></div>
+<div class="line"><a id="l00147" name="l00147"></a><span class="lineno"> 147</span> <span class="comment">// 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector...</span></div>
+<div class="line"><a id="l00148" name="l00148"></a><span class="lineno"> 148</span> io_rw_32 hfsr;</div>
+<div class="line"><a id="l00149" name="l00149"></a><span class="lineno"> 149</span> </div>
+<div class="line"><a id="l00150" name="l00150"></a><span class="lineno"> 150</span> _REG_(M33_DFSR_OFFSET) <span class="comment">// M33_DFSR</span></div>
+<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"> 151</span> <span class="comment">// Shows which debug event occurred</span></div>
+<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span> <span class="comment">// 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request...</span></div>
+<div class="line"><a id="l00153" name="l00153"></a><span class="lineno"> 153</span> <span class="comment">// 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug...</span></div>
+<div class="line"><a id="l00154" name="l00154"></a><span class="lineno"> 154</span> <span class="comment">// 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event...</span></div>
+<div class="line"><a id="l00155" name="l00155"></a><span class="lineno"> 155</span> <span class="comment">// 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event...</span></div>
+<div class="line"><a id="l00156" name="l00156"></a><span class="lineno"> 156</span> <span class="comment">// 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event...</span></div>
+<div class="line"><a id="l00157" name="l00157"></a><span class="lineno"> 157</span> io_rw_32 dfsr;</div>
+<div class="line"><a id="l00158" name="l00158"></a><span class="lineno"> 158</span> </div>
+<div class="line"><a id="l00159" name="l00159"></a><span class="lineno"> 159</span> _REG_(M33_MMFAR_OFFSET) <span class="comment">// M33_MMFAR</span></div>
+<div class="line"><a id="l00160" name="l00160"></a><span class="lineno"> 160</span> <span class="comment">// Shows the address of the memory location that caused an MPU fault</span></div>
+<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"> 161</span> <span class="comment">// 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location...</span></div>
+<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> io_rw_32 mmfar;</div>
+<div class="line"><a id="l00163" name="l00163"></a><span class="lineno"> 163</span> </div>
+<div class="line"><a id="l00164" name="l00164"></a><span class="lineno"> 164</span> _REG_(M33_BFAR_OFFSET) <span class="comment">// M33_BFAR</span></div>
+<div class="line"><a id="l00165" name="l00165"></a><span class="lineno"> 165</span> <span class="comment">// Shows the address associated with a precise data access BusFault</span></div>
+<div class="line"><a id="l00166" name="l00166"></a><span class="lineno"> 166</span> <span class="comment">// 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location...</span></div>
+<div class="line"><a id="l00167" name="l00167"></a><span class="lineno"> 167</span> io_rw_32 bfar;</div>
+<div class="line"><a id="l00168" name="l00168"></a><span class="lineno"> 168</span> </div>
+<div class="line"><a id="l00169" name="l00169"></a><span class="lineno"> 169</span> uint32_t _pad0;</div>
+<div class="line"><a id="l00170" name="l00170"></a><span class="lineno"> 170</span> </div>
+<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"> 171</span> <span class="comment">// (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes)</span></div>
+<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span> _REG_(M33_ID_PFR0_OFFSET) <span class="comment">// M33_ID_PFR0</span></div>
+<div class="line"><a id="l00173" name="l00173"></a><span class="lineno"> 173</span> <span class="comment">// Gives top-level information about the instruction set supported by the PE</span></div>
+<div class="line"><a id="l00174" name="l00174"></a><span class="lineno"> 174</span> <span class="comment">// 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support</span></div>
+<div class="line"><a id="l00175" name="l00175"></a><span class="lineno"> 175</span> <span class="comment">// 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support</span></div>
+<div class="line"><a id="l00176" name="l00176"></a><span class="lineno"> 176</span> io_ro_32 id_pfr[2];</div>
+<div class="line"><a id="l00177" name="l00177"></a><span class="lineno"> 177</span> </div>
+<div class="line"><a id="l00178" name="l00178"></a><span class="lineno"> 178</span> _REG_(M33_ID_DFR0_OFFSET) <span class="comment">// M33_ID_DFR0</span></div>
+<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"> 179</span> <span class="comment">// Provides top level information about the debug system</span></div>
+<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> <span class="comment">// 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture</span></div>
+<div class="line"><a id="l00181" name="l00181"></a><span class="lineno"> 181</span> io_ro_32 id_dfr0;</div>
+<div class="line"><a id="l00182" name="l00182"></a><span class="lineno"> 182</span> </div>
+<div class="line"><a id="l00183" name="l00183"></a><span class="lineno"> 183</span> _REG_(M33_ID_AFR0_OFFSET) <span class="comment">// M33_ID_AFR0</span></div>
+<div class="line"><a id="l00184" name="l00184"></a><span class="lineno"> 184</span> <span class="comment">// Provides information about the IMPLEMENTATION DEFINED features of the PE</span></div>
+<div class="line"><a id="l00185" name="l00185"></a><span class="lineno"> 185</span> <span class="comment">// 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning</span></div>
+<div class="line"><a id="l00186" name="l00186"></a><span class="lineno"> 186</span> <span class="comment">// 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning</span></div>
+<div class="line"><a id="l00187" name="l00187"></a><span class="lineno"> 187</span> <span class="comment">// 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning</span></div>
+<div class="line"><a id="l00188" name="l00188"></a><span class="lineno"> 188</span> <span class="comment">// 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning</span></div>
+<div class="line"><a id="l00189" name="l00189"></a><span class="lineno"> 189</span> io_ro_32 id_afr0;</div>
+<div class="line"><a id="l00190" name="l00190"></a><span class="lineno"> 190</span> </div>
+<div class="line"><a id="l00191" name="l00191"></a><span class="lineno"> 191</span> <span class="comment">// (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes)</span></div>
+<div class="line"><a id="l00192" name="l00192"></a><span class="lineno"> 192</span> _REG_(M33_ID_MMFR0_OFFSET) <span class="comment">// M33_ID_MMFR0</span></div>
+<div class="line"><a id="l00193" name="l00193"></a><span class="lineno"> 193</span> <span class="comment">// Provides information about the implemented memory model and memory management support</span></div>
+<div class="line"><a id="l00194" name="l00194"></a><span class="lineno"> 194</span> <span class="comment">// 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers</span></div>
+<div class="line"><a id="l00195" name="l00195"></a><span class="lineno"> 195</span> <span class="comment">// 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs)</span></div>
+<div class="line"><a id="l00196" name="l00196"></a><span class="lineno"> 196</span> <span class="comment">// 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented</span></div>
+<div class="line"><a id="l00197" name="l00197"></a><span class="lineno"> 197</span> <span class="comment">// 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented</span></div>
+<div class="line"><a id="l00198" name="l00198"></a><span class="lineno"> 198</span> <span class="comment">// 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system...</span></div>
+<div class="line"><a id="l00199" name="l00199"></a><span class="lineno"> 199</span> io_ro_32 id_mmfr[4];</div>
+<div class="line"><a id="l00200" name="l00200"></a><span class="lineno"> 200</span> </div>
+<div class="line"><a id="l00201" name="l00201"></a><span class="lineno"> 201</span> <span class="comment">// (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes)</span></div>
+<div class="line"><a id="l00202" name="l00202"></a><span class="lineno"> 202</span> _REG_(M33_ID_ISAR0_OFFSET) <span class="comment">// M33_ID_ISAR0</span></div>
+<div class="line"><a id="l00203" name="l00203"></a><span class="lineno"> 203</span> <span class="comment">// Provides information about the instruction set implemented by the PE</span></div>
+<div class="line"><a id="l00204" name="l00204"></a><span class="lineno"> 204</span> <span class="comment">// 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions</span></div>
+<div class="line"><a id="l00205" name="l00205"></a><span class="lineno"> 205</span> <span class="comment">// 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions</span></div>
+<div class="line"><a id="l00206" name="l00206"></a><span class="lineno"> 206</span> <span class="comment">// 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions</span></div>
+<div class="line"><a id="l00207" name="l00207"></a><span class="lineno"> 207</span> <span class="comment">// 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions</span></div>
+<div class="line"><a id="l00208" name="l00208"></a><span class="lineno"> 208</span> <span class="comment">// 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions</span></div>
+<div class="line"><a id="l00209" name="l00209"></a><span class="lineno"> 209</span> <span class="comment">// 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions</span></div>
+<div class="line"><a id="l00210" name="l00210"></a><span class="lineno"> 210</span> io_ro_32 id_isar[6];</div>
+<div class="line"><a id="l00211" name="l00211"></a><span class="lineno"> 211</span> </div>
+<div class="line"><a id="l00212" name="l00212"></a><span class="lineno"> 212</span> uint32_t _pad1;</div>
+<div class="line"><a id="l00213" name="l00213"></a><span class="lineno"> 213</span> </div>
+<div class="line"><a id="l00214" name="l00214"></a><span class="lineno"> 214</span> _REG_(M33_CTR_OFFSET) <span class="comment">// M33_CTR</span></div>
+<div class="line"><a id="l00215" name="l00215"></a><span class="lineno"> 215</span> <span class="comment">// Provides information about the architecture of the caches</span></div>
+<div class="line"><a id="l00216" name="l00216"></a><span class="lineno"> 216</span> <span class="comment">// 0x80000000 [31] RES1 (1) Reserved, RES1</span></div>
+<div class="line"><a id="l00217" name="l00217"></a><span class="lineno"> 217</span> <span class="comment">// 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of...</span></div>
+<div class="line"><a id="l00218" name="l00218"></a><span class="lineno"> 218</span> <span class="comment">// 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the...</span></div>
+<div class="line"><a id="l00219" name="l00219"></a><span class="lineno"> 219</span> <span class="comment">// 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line...</span></div>
+<div class="line"><a id="l00220" name="l00220"></a><span class="lineno"> 220</span> <span class="comment">// 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1</span></div>
+<div class="line"><a id="l00221" name="l00221"></a><span class="lineno"> 221</span> <span class="comment">// 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line...</span></div>
+<div class="line"><a id="l00222" name="l00222"></a><span class="lineno"> 222</span> io_ro_32 ctr;</div>
+<div class="line"><a id="l00223" name="l00223"></a><span class="lineno"> 223</span> </div>
+<div class="line"><a id="l00224" name="l00224"></a><span class="lineno"> 224</span> uint32_t _pad2[2];</div>
+<div class="line"><a id="l00225" name="l00225"></a><span class="lineno"> 225</span> </div>
+<div class="line"><a id="l00226" name="l00226"></a><span class="lineno"> 226</span> _REG_(M33_CPACR_OFFSET) <span class="comment">// M33_CPACR</span></div>
+<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"> 227</span> <span class="comment">// Specifies the access privileges for coprocessors and the FP Extension</span></div>
+<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> <span class="comment">// 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored</span></div>
+<div class="line"><a id="l00229" name="l00229"></a><span class="lineno"> 229</span> <span class="comment">// 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality</span></div>
+<div class="line"><a id="l00230" name="l00230"></a><span class="lineno"> 230</span> <span class="comment">// 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7</span></div>
+<div class="line"><a id="l00231" name="l00231"></a><span class="lineno"> 231</span> <span class="comment">// 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6</span></div>
+<div class="line"><a id="l00232" name="l00232"></a><span class="lineno"> 232</span> <span class="comment">// 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5</span></div>
+<div class="line"><a id="l00233" name="l00233"></a><span class="lineno"> 233</span> <span class="comment">// 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4</span></div>
+<div class="line"><a id="l00234" name="l00234"></a><span class="lineno"> 234</span> <span class="comment">// 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3</span></div>
+<div class="line"><a id="l00235" name="l00235"></a><span class="lineno"> 235</span> <span class="comment">// 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2</span></div>
+<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"> 236</span> <span class="comment">// 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1</span></div>
+<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span> <span class="comment">// 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0</span></div>
+<div class="line"><a id="l00238" name="l00238"></a><span class="lineno"> 238</span> io_rw_32 cpacr;</div>
+<div class="line"><a id="l00239" name="l00239"></a><span class="lineno"> 239</span> </div>
+<div class="line"><a id="l00240" name="l00240"></a><span class="lineno"> 240</span> _REG_(M33_NSACR_OFFSET) <span class="comment">// M33_NSACR</span></div>
+<div class="line"><a id="l00241" name="l00241"></a><span class="lineno"> 241</span> <span class="comment">// Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7</span></div>
+<div class="line"><a id="l00242" name="l00242"></a><span class="lineno"> 242</span> <span class="comment">// 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension</span></div>
+<div class="line"><a id="l00243" name="l00243"></a><span class="lineno"> 243</span> <span class="comment">// 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension</span></div>
+<div class="line"><a id="l00244" name="l00244"></a><span class="lineno"> 244</span> <span class="comment">// 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7</span></div>
+<div class="line"><a id="l00245" name="l00245"></a><span class="lineno"> 245</span> <span class="comment">// 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6</span></div>
+<div class="line"><a id="l00246" name="l00246"></a><span class="lineno"> 246</span> <span class="comment">// 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5</span></div>
+<div class="line"><a id="l00247" name="l00247"></a><span class="lineno"> 247</span> <span class="comment">// 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4</span></div>
+<div class="line"><a id="l00248" name="l00248"></a><span class="lineno"> 248</span> <span class="comment">// 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3</span></div>
+<div class="line"><a id="l00249" name="l00249"></a><span class="lineno"> 249</span> <span class="comment">// 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2</span></div>
+<div class="line"><a id="l00250" name="l00250"></a><span class="lineno"> 250</span> <span class="comment">// 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1</span></div>
+<div class="line"><a id="l00251" name="l00251"></a><span class="lineno"> 251</span> <span class="comment">// 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0</span></div>
+<div class="line"><a id="l00252" name="l00252"></a><span class="lineno"> 252</span> io_rw_32 nsacr;</div>
+<div class="line"><a id="l00253" name="l00253"></a><span class="lineno"> 253</span> </div>
+<div class="line"><a id="l00254" name="l00254"></a><span class="lineno"> 254</span>} <a class="code hl_struct" href="structarmv8m__scb__hw__t.html">armv8m_scb_hw_t</a>;</div>
+<div class="line"><a id="l00255" name="l00255"></a><span class="lineno"> 255</span> </div>
+<div class="line"><a id="l00256" name="l00256"></a><span class="lineno"> 256</span><span class="preprocessor">#define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET))</span></div>
+<div class="line"><a id="l00257" name="l00257"></a><span class="lineno"> 257</span><span class="preprocessor">#define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET))</span></div>
+<div class="line"><a id="l00258" name="l00258"></a><span class="lineno"> 258</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structarmv8m__scb__hw__t.html">armv8m_scb_hw_t</a>) == 0x0090, <span class="stringliteral">""</span>);</div>
+<div class="line"><a id="l00259" name="l00259"></a><span class="lineno"> 259</span> </div>
+<div class="line"><a id="l00260" name="l00260"></a><span class="lineno"> 260</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_SCB_H</span></div>
+<div class="line"><a id="l00261" name="l00261"></a><span class="lineno"> 261</span> </div>
<div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
-<div class="ttc" id="astructarmv6m__scb__t_html"><div class="ttname"><a href="structarmv6m__scb__t.html">armv6m_scb_t</a></div><div class="ttdef"><b>Definition:</b> scb.h:23</div></div>
+<div class="ttc" id="astructarmv8m__scb__hw__t_html"><div class="ttname"><a href="structarmv8m__scb__hw__t.html">armv8m_scb_hw_t</a></div><div class="ttdef"><b>Definition:</b> scb.h:26</div></div>
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