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<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
<div class="line"><a id="l00002" name="l00002"></a><span class="lineno"> 2</span> </div>
-<div class="line"><a id="l00003" name="l00003"></a><span class="lineno"> 3</span><span class="comment">/*</span></div>
-<div class="line"><a id="l00004" name="l00004"></a><span class="lineno"> 4</span><span class="comment"> * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.</span></div>
-<div class="line"><a id="l00005" name="l00005"></a><span class="lineno"> 5</span><span class="comment"> *</span></div>
-<div class="line"><a id="l00006" name="l00006"></a><span class="lineno"> 6</span><span class="comment"> * SPDX-License-Identifier: BSD-3-Clause</span></div>
-<div class="line"><a id="l00007" name="l00007"></a><span class="lineno"> 7</span><span class="comment"> */</span></div>
-<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span> </div>
-<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_MPU_H</span></div>
-<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span><span class="preprocessor">#define _HARDWARE_STRUCTS_MPU_H</span></div>
-<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span> </div>
-<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="preprocessor">#include "<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>"</span></div>
-<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span><span class="preprocessor">#include "hardware/regs/m0plus.h"</span></div>
-<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span> </div>
-<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus</span></div>
-<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">//</span></div>
-<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)</span></div>
-<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.</span></div>
-<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">//</span></div>
-<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
-<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span><span class="comment">// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION</span></div>
-<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span> </div>
-<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"><a class="line" href="structmpu__hw__t.html"> 23</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
-<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span> _REG_(M0PLUS_MPU_TYPE_OFFSET) <span class="comment">// M0PLUS_MPU_TYPE</span></div>
-<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span> <span class="comment">// Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports</span></div>
-<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> <span class="comment">// 0x00ff0000 [23:16] : IREGION (0): Instruction region</span></div>
-<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> <span class="comment">// 0x0000ff00 [15:8] : DREGION (0x8): Number of regions supported by the MPU</span></div>
-<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> <span class="comment">// 0x00000001 [0] : SEPARATE (0): Indicates support for separate instruction and data address maps</span></div>
-<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> io_ro_32 type;</div>
-<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span> </div>
-<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> _REG_(M0PLUS_MPU_CTRL_OFFSET) <span class="comment">// M0PLUS_MPU_CTRL</span></div>
-<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> <span class="comment">// Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled...</span></div>
-<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> <span class="comment">// 0x00000004 [2] : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for...</span></div>
-<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> <span class="comment">// 0x00000002 [1] : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs</span></div>
-<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> <span class="comment">// 0x00000001 [0] : ENABLE (0): Enables the MPU</span></div>
-<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> io_rw_32 ctrl;</div>
-<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> </div>
-<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> _REG_(M0PLUS_MPU_RNR_OFFSET) <span class="comment">// M0PLUS_MPU_RNR</span></div>
-<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> <span class="comment">// Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR</span></div>
-<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> <span class="comment">// 0x0000000f [3:0] : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers</span></div>
-<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> io_rw_32 rnr;</div>
-<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> </div>
-<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> _REG_(M0PLUS_MPU_RBAR_OFFSET) <span class="comment">// M0PLUS_MPU_RBAR</span></div>
-<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> <span class="comment">// Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR</span></div>
-<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span> <span class="comment">// 0xffffff00 [31:8] : ADDR (0): Base address of the region</span></div>
-<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> <span class="comment">// 0x00000010 [4] : VALID (0): On writes, indicates whether the write must update the base address of the region...</span></div>
-<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> <span class="comment">// 0x0000000f [3:0] : REGION (0): On writes, specifies the number of the region whose base address to update provided...</span></div>
-<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> io_rw_32 rbar;</div>
-<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span> </div>
-<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> _REG_(M0PLUS_MPU_RASR_OFFSET) <span class="comment">// M0PLUS_MPU_RASR</span></div>
-<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span> <span class="comment">// Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region...</span></div>
-<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> <span class="comment">// 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field</span></div>
-<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> <span class="comment">// 0x0000ff00 [15:8] : SRD (0): Subregion Disable</span></div>
-<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> <span class="comment">// 0x0000003e [5:1] : SIZE (0): Indicates the region size</span></div>
-<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> <span class="comment">// 0x00000001 [0] : ENABLE (0): Enables the region</span></div>
-<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> io_rw_32 rasr;</div>
-<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span>} <a class="code hl_struct" href="structmpu__hw__t.html">mpu_hw_t</a>;</div>
-<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> </div>
-<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span><span class="preprocessor">#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))</span></div>
-<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> </div>
-<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span><span class="preprocessor">#endif</span></div>
+<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_MPU_H</span></div>
+<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_MPU_H</span></div>
+<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span> </div>
+<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="preprocessor">#include "<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>"</span></div>
+<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="preprocessor">#include "hardware/regs/m33.h"</span></div>
+<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span> </div>
+<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33</span></div>
+<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"> 15</span><span class="comment">//</span></div>
+<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"> 16</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)</span></div>
+<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"> 17</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.</span></div>
+<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"> 18</span><span class="comment">//</span></div>
+<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"> 19</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
+<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"> 20</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
+<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div>
+<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"> 22</span><span class="preprocessor">#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV</span></div>
+<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span><span class="preprocessor">#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"</span></div>
+<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"> 24</span><span class="preprocessor">#endif</span></div>
+<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span> </div>
+<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structmpu__hw__t.html"> 26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
+<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"> 27</span> _REG_(M33_MPU_TYPE_OFFSET) <span class="comment">// M33_MPU_TYPE</span></div>
+<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"> 28</span> <span class="comment">// The MPU Type Register indicates how many regions the MPU `FTSSS supports</span></div>
+<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> <span class="comment">// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU</span></div>
+<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"> 30</span> <span class="comment">// 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data...</span></div>
+<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> io_ro_32 type;</div>
+<div class="line"><a id="l00032" name="l00032"></a><span class="lineno"> 32</span> </div>
+<div class="line"><a id="l00033" name="l00033"></a><span class="lineno"> 33</span> _REG_(M33_MPU_CTRL_OFFSET) <span class="comment">// M33_MPU_CTRL</span></div>
+<div class="line"><a id="l00034" name="l00034"></a><span class="lineno"> 34</span> <span class="comment">// Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled...</span></div>
+<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"> 35</span> <span class="comment">// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for...</span></div>
+<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span> <span class="comment">// 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less...</span></div>
+<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"> 37</span> <span class="comment">// 0x00000001 [0] ENABLE (0) Enables the MPU</span></div>
+<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"> 38</span> io_rw_32 ctrl;</div>
+<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"> 39</span> </div>
+<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"> 40</span> _REG_(M33_MPU_RNR_OFFSET) <span class="comment">// M33_MPU_RNR</span></div>
+<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span> <span class="comment">// Selects the region currently accessed by MPU_RBAR and MPU_RLAR</span></div>
+<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> <span class="comment">// 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR</span></div>
+<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span> io_rw_32 rnr;</div>
+<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"> 44</span> </div>
+<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"> 45</span> _REG_(M33_MPU_RBAR_OFFSET) <span class="comment">// M33_MPU_RBAR</span></div>
+<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"> 46</span> <span class="comment">// Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS</span></div>
+<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span> <span class="comment">// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
+<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> <span class="comment">// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
+<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"> 49</span> <span class="comment">// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region</span></div>
+<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"> 50</span> <span class="comment">// 0x00000001 [0] XN (0) Defines whether code can be executed from this region</span></div>
+<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"> 51</span> io_rw_32 rbar;</div>
+<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"> 52</span> </div>
+<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"> 53</span> _REG_(M33_MPU_RLAR_OFFSET) <span class="comment">// M33_MPU_RLAR</span></div>
+<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"> 54</span> <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS</span></div>
+<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"> 55</span> <span class="comment">// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
+<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"> 56</span> <span class="comment">// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
+<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> <span class="comment">// 0x00000001 [0] EN (0) Region enable</span></div>
+<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"> 58</span> io_rw_32 rlar;</div>
+<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"> 59</span> </div>
+<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"> 60</span> _REG_(M33_MPU_RBAR_A1_OFFSET) <span class="comment">// M33_MPU_RBAR_A1</span></div>
+<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"> 61</span> <span class="comment">// Provides indirect read and write access to the base address of the MPU region selected by...</span></div>
+<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"> 62</span> <span class="comment">// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
+<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"> 63</span> <span class="comment">// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
+<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"> 64</span> <span class="comment">// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region</span></div>
+<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> <span class="comment">// 0x00000001 [0] XN (0) Defines whether code can be executed from this region</span></div>
+<div class="line"><a id="l00066" name="l00066"></a><span class="lineno"> 66</span> io_rw_32 rbar_a1;</div>
+<div class="line"><a id="l00067" name="l00067"></a><span class="lineno"> 67</span> </div>
+<div class="line"><a id="l00068" name="l00068"></a><span class="lineno"> 68</span> _REG_(M33_MPU_RLAR_A1_OFFSET) <span class="comment">// M33_MPU_RLAR_A1</span></div>
+<div class="line"><a id="l00069" name="l00069"></a><span class="lineno"> 69</span> <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU...</span></div>
+<div class="line"><a id="l00070" name="l00070"></a><span class="lineno"> 70</span> <span class="comment">// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
+<div class="line"><a id="l00071" name="l00071"></a><span class="lineno"> 71</span> <span class="comment">// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
+<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"> 72</span> <span class="comment">// 0x00000001 [0] EN (0) Region enable</span></div>
+<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> io_rw_32 rlar_a1;</div>
+<div class="line"><a id="l00074" name="l00074"></a><span class="lineno"> 74</span> </div>
+<div class="line"><a id="l00075" name="l00075"></a><span class="lineno"> 75</span> _REG_(M33_MPU_RBAR_A2_OFFSET) <span class="comment">// M33_MPU_RBAR_A2</span></div>
+<div class="line"><a id="l00076" name="l00076"></a><span class="lineno"> 76</span> <span class="comment">// Provides indirect read and write access to the base address of the MPU region selected by...</span></div>
+<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"> 77</span> <span class="comment">// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
+<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"> 78</span> <span class="comment">// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
+<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"> 79</span> <span class="comment">// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region</span></div>
+<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span> <span class="comment">// 0x00000001 [0] XN (0) Defines whether code can be executed from this region</span></div>
+<div class="line"><a id="l00081" name="l00081"></a><span class="lineno"> 81</span> io_rw_32 rbar_a2;</div>
+<div class="line"><a id="l00082" name="l00082"></a><span class="lineno"> 82</span> </div>
+<div class="line"><a id="l00083" name="l00083"></a><span class="lineno"> 83</span> _REG_(M33_MPU_RLAR_A2_OFFSET) <span class="comment">// M33_MPU_RLAR_A2</span></div>
+<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"> 84</span> <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU...</span></div>
+<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"> 85</span> <span class="comment">// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
+<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"> 86</span> <span class="comment">// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
+<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"> 87</span> <span class="comment">// 0x00000001 [0] EN (0) Region enable</span></div>
+<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"> 88</span> io_rw_32 rlar_a2;</div>
+<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"> 89</span> </div>
+<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"> 90</span> _REG_(M33_MPU_RBAR_A3_OFFSET) <span class="comment">// M33_MPU_RBAR_A3</span></div>
+<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> <span class="comment">// Provides indirect read and write access to the base address of the MPU region selected by...</span></div>
+<div class="line"><a id="l00092" name="l00092"></a><span class="lineno"> 92</span> <span class="comment">// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
+<div class="line"><a id="l00093" name="l00093"></a><span class="lineno"> 93</span> <span class="comment">// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
+<div class="line"><a id="l00094" name="l00094"></a><span class="lineno"> 94</span> <span class="comment">// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region</span></div>
+<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"> 95</span> <span class="comment">// 0x00000001 [0] XN (0) Defines whether code can be executed from this region</span></div>
+<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"> 96</span> io_rw_32 rbar_a3;</div>
+<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"> 97</span> </div>
+<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"> 98</span> _REG_(M33_MPU_RLAR_A3_OFFSET) <span class="comment">// M33_MPU_RLAR_A3</span></div>
+<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU...</span></div>
+<div class="line"><a id="l00100" name="l00100"></a><span class="lineno"> 100</span> <span class="comment">// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
+<div class="line"><a id="l00101" name="l00101"></a><span class="lineno"> 101</span> <span class="comment">// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
+<div class="line"><a id="l00102" name="l00102"></a><span class="lineno"> 102</span> <span class="comment">// 0x00000001 [0] EN (0) Region enable</span></div>
+<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"> 103</span> io_rw_32 rlar_a3;</div>
+<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"> 104</span> </div>
+<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"> 105</span> uint32_t _pad0;</div>
+<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"> 106</span> </div>
+<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> <span class="comment">// (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes)</span></div>
+<div class="line"><a id="l00108" name="l00108"></a><span class="lineno"> 108</span> _REG_(M33_MPU_MAIR0_OFFSET) <span class="comment">// M33_MPU_MAIR0</span></div>
+<div class="line"><a id="l00109" name="l00109"></a><span class="lineno"> 109</span> <span class="comment">// Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values</span></div>
+<div class="line"><a id="l00110" name="l00110"></a><span class="lineno"> 110</span> <span class="comment">// 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3</span></div>
+<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"> 111</span> <span class="comment">// 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2</span></div>
+<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"> 112</span> <span class="comment">// 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1</span></div>
+<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"> 113</span> <span class="comment">// 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0</span></div>
+<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"> 114</span> io_rw_32 mair[2];</div>
+<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span> </div>
+<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"> 116</span>} <a class="code hl_struct" href="structmpu__hw__t.html">mpu_hw_t</a>;</div>
+<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"> 117</span> </div>
+<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"> 118</span><span class="preprocessor">#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))</span></div>
+<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"> 119</span><span class="preprocessor">#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET))</span></div>
+<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structmpu__hw__t.html">mpu_hw_t</a>) == 0x0038, <span class="stringliteral">""</span>);</div>
+<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"> 121</span> </div>
+<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"> 122</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_MPU_H</span></div>
+<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"> 123</span> </div>
<div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
-<div class="ttc" id="astructmpu__hw__t_html"><div class="ttname"><a href="structmpu__hw__t.html">mpu_hw_t</a></div><div class="ttdef"><b>Definition:</b> mpu.h:23</div></div>
+<div class="ttc" id="astructmpu__hw__t_html"><div class="ttname"><a href="structmpu__hw__t.html">mpu_hw_t</a></div><div class="ttdef"><b>Definition:</b> mpu.h:26</div></div>
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