|
| _REG_ (M0PLUS_SYST_CSR_OFFSET) io_rw_32 syst_csr |
|
| _REG_ (M0PLUS_SYST_RVR_OFFSET) io_rw_32 syst_rvr |
|
| _REG_ (M0PLUS_SYST_CVR_OFFSET) io_rw_32 syst_cvr |
|
| _REG_ (M0PLUS_SYST_CALIB_OFFSET) io_ro_32 syst_calib |
|
| _REG_ (M0PLUS_NVIC_ISER_OFFSET) io_rw_32 nvic_iser |
|
| _REG_ (M0PLUS_NVIC_ICER_OFFSET) io_rw_32 nvic_icer |
|
| _REG_ (M0PLUS_NVIC_ISPR_OFFSET) io_rw_32 nvic_ispr |
|
| _REG_ (M0PLUS_NVIC_ICPR_OFFSET) io_rw_32 nvic_icpr |
|
| _REG_ (M0PLUS_NVIC_IPR0_OFFSET) io_rw_32 nvic_ipr[8] |
|
| _REG_ (M0PLUS_CPUID_OFFSET) io_ro_32 cpuid |
|
| _REG_ (M0PLUS_ICSR_OFFSET) io_rw_32 icsr |
|
| _REG_ (M0PLUS_VTOR_OFFSET) io_rw_32 vtor |
|
| _REG_ (M0PLUS_AIRCR_OFFSET) io_rw_32 aircr |
|
| _REG_ (M0PLUS_SCR_OFFSET) io_rw_32 scr |
|
| _REG_ (M0PLUS_CCR_OFFSET) io_ro_32 ccr |
|
| _REG_ (M0PLUS_SHPR2_OFFSET) io_rw_32 shpr[2] |
|
| _REG_ (M0PLUS_SHCSR_OFFSET) io_rw_32 shcsr |
|
| _REG_ (M0PLUS_MPU_TYPE_OFFSET) io_ro_32 mpu_type |
|
| _REG_ (M0PLUS_MPU_CTRL_OFFSET) io_rw_32 mpu_ctrl |
|
| _REG_ (M0PLUS_MPU_RNR_OFFSET) io_rw_32 mpu_rnr |
|
| _REG_ (M0PLUS_MPU_RBAR_OFFSET) io_rw_32 mpu_rbar |
|
| _REG_ (M0PLUS_MPU_RASR_OFFSET) io_rw_32 mpu_rasr |
|
|
uint32_t | _pad0 [14340] |
|
uint32_t | _pad1 [56] |
|
uint32_t | _pad2 [31] |
|
uint32_t | _pad3 [31] |
|
uint32_t | _pad4 [31] |
|
uint32_t | _pad5 [95] |
|
uint32_t | _pad6 [568] |
|
uint32_t | _pad7 |
|
uint32_t | _pad8 [26] |
|
The documentation for this struct was generated from the following file: