platform.h

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/*
 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _PICO_PLATFORM_H
#define _PICO_PLATFORM_H
 
#ifndef _PICO_H
#error pico/platform.h should not be included directly; include pico.h instead
#endif
 
#include "pico/platform/compiler.h"
#include "pico/platform/sections.h"
#include "pico/platform/panic.h"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/sio.h"
#ifdef __riscv
#include "hardware/regs/rvcsr.h"
#endif
 
// PICO_CONFIG: PICO_RP2350A, Whether the current board has an RP2350 in an A (30 GPIO) package, type=bool, default=Usually provided via board header, group=pico_platform
 
// PICO_CONFIG: PICO_STACK_SIZE, Minimum amount of stack space reserved in the linker script for each core. See also PICO_CORE1_STACK_SIZE, min=0x100, default=0x800, advanced=true, group=pico_platform
#ifndef PICO_STACK_SIZE
#define PICO_STACK_SIZE _u(0x800)
#endif
 
// PICO_CONFIG: PICO_HEAP_SIZE, Minimum amount of heap space reserved by the linker script, min=0x100, default=0x800, advanced=true, group=pico_platform
#ifndef PICO_HEAP_SIZE
#define PICO_HEAP_SIZE _u(0x800)
#endif
 
// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform
#ifndef PICO_NO_RAM_VECTOR_TABLE
#define PICO_NO_RAM_VECTOR_TABLE 0
#endif
 
#ifndef PICO_RAM_VECTOR_TABLE_SIZE
#define PICO_RAM_VECTOR_TABLE_SIZE (VTABLE_FIRST_IRQ + NUM_IRQS)
#endif
 
// PICO_CONFIG: PICO_USE_STACK_GUARDS, Enable/disable stack guards, type=bool, default=0, advanced=true, group=pico_platform
#ifndef PICO_USE_STACK_GUARDS
#define PICO_USE_STACK_GUARDS 0
#endif
 
#ifndef __ASSEMBLER__
 
static __force_inline void tight_loop_contents(void) {}
 
static inline void busy_wait_at_least_cycles(uint32_t minimum_cycles) {
    pico_default_asm_volatile (
#ifdef __riscv
            // Note the range is halved on RISC-V due to signed comparison (no carry flag)
            ".option push\n"
            ".option norvc\n" // force 32 bit addi, so branch prediction guaranteed
            ".p2align 2\n"
            "1: \n"
            "addi %0, %0, -2 \n"
            "bgez %0, 1b\n"
            ".option pop"
#else
    "1: subs %0, #3\n"
    "bcs 1b\n"
#endif
    : "+r" (minimum_cycles) : : "cc", "memory"
    );
}
 
// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=platform dependent, advanced=true, group=pico_runtime
#ifndef PICO_NO_FPGA_CHECK
#if !PICO_RP2040
#define PICO_NO_FPGA_CHECK 1
#endif
#endif
 
// PICO_CONFIG: PICO_NO_SIM_CHECK, Remove the SIM platform check for small code size reduction, type=bool, default=1, advanced=true, group=pico_runtime
#ifndef PICO_NO_SIM_CHECK
#define PICO_NO_SIM_CHECK 1
#endif
 
#if PICO_NO_FPGA_CHECK
static inline bool running_on_fpga(void) {return false;}
#else
bool running_on_fpga(void);
#endif
#if PICO_NO_SIM_CHECK
static inline bool running_in_sim(void) {return false;}
#else
bool running_in_sim(void);
#endif
 
static __force_inline void __breakpoint(void) {
#ifdef __riscv
    __asm ("ebreak");
#else
    pico_default_asm_volatile ("bkpt #0" : : : "memory");
#endif
}
 
__force_inline static uint get_core_num(void) {
    return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
}
 
static __force_inline uint __get_current_exception(void) {
#ifdef __riscv
    uint32_t meicontext;
    pico_default_asm_volatile (
            "csrr %0, %1\n"
    : "=r" (meicontext) : "i" (RVCSR_MEICONTEXT_OFFSET)
    );
    if (meicontext & RVCSR_MEICONTEXT_NOIRQ_BITS) {
        return 0;
    } else {
        return VTABLE_FIRST_IRQ + (
                (meicontext & RVCSR_MEICONTEXT_IRQ_BITS) >> RVCSR_MEICONTEXT_IRQ_LSB
        );
    }
#else
    uint exception;
    pico_default_asm_volatile (
        "mrs %0, ipsr\n"
        "uxtb %0, %0\n"
        : "=l" (exception)
    );
    return exception;
#endif
}
 
__force_inline static bool pico_processor_state_is_nonsecure(void) {
#ifndef __riscv
    // todo add a define to disable NS checking at all?
    // IDAU-Exempt addresses return S=1 when tested in the Secure state,
    // whereas executing a tt in the NonSecure state will always return S=0.
    uint32_t tt;
    pico_default_asm_volatile (
        "movs %0, #0\n"
        "tt %0, %0\n"
        : "=r" (tt) : : "cc"
    );
    return !(tt & (1u << 22));
#else
    // NonSecure is an Arm concept, there is nothing meaningful to return
    // here. Note it's not possible in general to detect whether you are
    // executing in U-mode as, for example, M-mode is classically
    // virtualisable in U-mode.
    return false;
#endif
}
 
#define host_safe_hw_ptr(x) ((uintptr_t)(x))
#define native_safe_hw_ptr(x) host_safe_hw_ptr(x)
 
uint8_t rp2350_chip_version(void);
 
static inline uint8_t rp2040_chip_version(void) {
    return 2;
}
 
static inline uint8_t rp2040_rom_version(void) {
    GCC_Pragma("GCC diagnostic push")
    GCC_Pragma("GCC diagnostic ignored \"-Warray-bounds\"")
    return *(uint8_t*)0x13;
    GCC_Pragma("GCC diagnostic pop")
}
 
__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
#ifdef __riscv
    __asm ("mul %0, %0, %1" : "+l" (a) : "l" (b) : );
#else
    pico_default_asm ("muls %0, %1"     : "+l" (a) : "l" (b) : "cc");
#endif
    return a;
}
 
#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \
    (__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \
    (a)*(b))
 
#endif // __ASSEMBLER__
 
#endif