irq.h

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/*
 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _HARDWARE_IRQ_H
#define _HARDWARE_IRQ_H
 
// These two config items are also used by assembler, so keeping separate
// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
#ifndef PICO_MAX_SHARED_IRQ_HANDLERS
#define PICO_MAX_SHARED_IRQ_HANDLERS 4
#endif
 
// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
#endif
 
// PICO_CONFIG: PICO_VTABLE_PER_CORE, user is using separate vector tables per core, type=bool, default=0, group=hardware_irq
#ifndef PICO_VTABLE_PER_CORE
#define PICO_VTABLE_PER_CORE 0
#endif
 
#ifndef __ASSEMBLER__
 
#include "pico.h"
#include "hardware/address_mapped.h"
#include "hardware/regs/intctrl.h"
 
#include "pico/platform/cpu_regs.h"
 
// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq
#ifndef PICO_DEFAULT_IRQ_PRIORITY
#define PICO_DEFAULT_IRQ_PRIORITY 0x80
#endif
 
#define PICO_LOWEST_IRQ_PRIORITY 0xff
#define PICO_HIGHEST_IRQ_PRIORITY 0x00
 
// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80
#endif
 
#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00
 
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ
#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0
#endif
#endif
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef void (*irq_handler_t)(void);
 
static inline void check_irq_param(__unused uint num) {
    invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS);
}
 
void irq_set_priority(uint num, uint8_t hardware_priority);
 
uint irq_get_priority(uint num);
 
void irq_set_enabled(uint num, bool enabled);
 
bool irq_is_enabled(uint num);
 
void irq_set_mask_enabled(uint32_t mask, bool enabled);
 
void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled);
 
void irq_set_exclusive_handler(uint num, irq_handler_t handler);
 
irq_handler_t irq_get_exclusive_handler(uint num);
 
void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
 
void irq_remove_handler(uint num, irq_handler_t handler);
 
bool irq_has_shared_handler(uint num);
 
irq_handler_t irq_get_vtable_handler(uint num);
 
static inline void irq_clear(uint int_num) {
#if PICO_RP2040
    *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F)));
#elif defined(__riscv)
    // External IRQs are not latched, but we should clear the IRQ force bit here
    hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16));
#else
    nvic_hw->icpr[int_num/32] = 1 << (int_num % 32);
#endif
}
 
void irq_set_pending(uint num);
 
 
void runtime_init_per_core_irq_priorities(void);
 
static __force_inline void irq_init_priorities(void) {
    runtime_init_per_core_irq_priorities();
}
 
void user_irq_claim(uint irq_num);
 
void user_irq_unclaim(uint irq_num);
 
int user_irq_claim_unused(bool required);
 
/*
*! \brief Check if a user IRQ is in use on the calling core
 *  \ingroup hardware_irq
 *  
 * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending.
 *
 * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
 * dealing with Uer IRQs affect only the calling core
 *
 * \param irq_num the irq irq_num
 * \return true if the irq_num is claimed, false otherwise
 * \sa user_irq_claim
 * \sa user_irq_unclaim
 * \sa user_irq_claim_unused
 */
bool user_irq_is_claimed(uint irq_num);
 
void __unhandled_user_irq(void);
 
#ifdef __riscv
enum riscv_vector_num {
    RISCV_VEC_MACHINE_EXCEPTION = 0,
    RISCV_VEC_MACHINE_SOFTWARE_IRQ = 3,
    RISCV_VEC_MACHINE_TIMER_IRQ = 7,
    RISCV_VEC_MACHINE_EXTERNAL_IRQ = 11,
};
 
irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler);
#endif
 
#if PICO_SECURE
static inline void irq_assign_to_ns(uint irq_num, bool ns) {
    check_irq_param(irq_num);
    if (ns) nvic_hw->itns[irq_num >> 5] |= 1u << (irq_num & 0x1fu);
    else nvic_hw->itns[irq_num >> 5] &= ~(1u << (irq_num & 0x1fu));
}
#endif
#ifdef __cplusplus
}
#endif
 
#endif
#endif