8#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
9#define _HARDWARE_STRUCTS_IO_QSPI_H
12#include "hardware/regs/io_qspi.h"
27 GPIO_FUNC1_UART_AUX = 11,
28 GPIO_FUNC1_NULL = 0x1f,
32 _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET)
39 _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET)
50 _REG_(IO_QSPI_PROC0_INTE_OFFSET)
86 _REG_(IO_QSPI_PROC0_INTF_OFFSET)
122 _REG_(IO_QSPI_PROC0_INTS_OFFSET)
161 _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET)
166 io_ro_32 usbphy_dp_status;
168 _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET)
174 io_rw_32 usbphy_dp_ctrl;
176 _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET)
181 io_ro_32 usbphy_dm_status;
183 _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET)
189 io_rw_32 usbphy_dm_ctrl;
195 _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET)
204 io_ro_32 irqsummary_proc0_secure;
206 _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET)
215 io_ro_32 irqsummary_proc0_nonsecure;
217 _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET)
226 io_ro_32 irqsummary_proc1_secure;
228 _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET)
237 io_ro_32 irqsummary_proc1_nonsecure;
239 _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET)
248 io_ro_32 irqsummary_dormant_wake_secure;
250 _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET)
259 io_ro_32 irqsummary_dormant_wake_nonsecure;
261 _REG_(IO_QSPI_INTR_OFFSET)
308#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
Definition: io_qspi.h:160