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#define | TEST_PATTERN 0xFEEDBEADu |
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#define | SPI_BUS_CONTROL ((uint32_t)0x0000) |
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#define | SPI_RESPONSE_DELAY ((uint32_t)0x0001) |
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#define | SPI_STATUS_ENABLE ((uint32_t)0x0002) |
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#define | SPI_RESET_BP ((uint32_t)0x0003) |
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#define | SPI_INTERRUPT_REGISTER ((uint32_t)0x0004) |
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#define | SPI_INTERRUPT_ENABLE_REGISTER ((uint32_t)0x0006) |
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#define | SPI_STATUS_REGISTER ((uint32_t)0x0008) |
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#define | SPI_FUNCTION1_INFO ((uint32_t)0x000C) |
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#define | SPI_FUNCTION2_INFO ((uint32_t)0x000E) |
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#define | SPI_FUNCTION3_INFO ((uint32_t)0x0010) |
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#define | SPI_READ_TEST_REGISTER ((uint32_t)0x0014) |
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#define | SPI_RESP_DELAY_F0 ((uint32_t)0x001c) |
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#define | SPI_RESP_DELAY_F1 ((uint32_t)0x001d) |
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#define | SPI_RESP_DELAY_F2 ((uint32_t)0x001e) |
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#define | SPI_RESP_DELAY_F3 ((uint32_t)0x001f) |
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#define | SPI_FUNCTIONX_ENABLED (1 << 0) |
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#define | SPI_FUNCTIONX_READY (1 << 1) |
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#define | WORD_LENGTH_32 ((uint32_t)0x01) |
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#define | ENDIAN_BIG ((uint32_t)0x02) |
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#define | CLOCK_PHASE ((uint32_t)0x04) |
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#define | CLOCK_POLARITY ((uint32_t)0x08) |
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#define | HIGH_SPEED_MODE ((uint32_t)0x10) |
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#define | INTERRUPT_POLARITY_HIGH ((uint32_t)0x20) |
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#define | WAKE_UP ((uint32_t)0x80) |
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#define | STATUS_ENABLE ((uint32_t)0x01) |
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#define | INTR_WITH_STATUS ((uint32_t)0x02) |
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#define | RESP_DELAY_ALL ((uint32_t)0x04) |
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#define | DWORD_PKT_LEN_EN ((uint32_t)0x08) |
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#define | CMD_ERR_CHK_EN ((uint32_t)0x20) |
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#define | DATA_ERR_CHK_EN ((uint32_t)0x40) |
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#define | DATA_UNAVAILABLE ((uint32_t)0x0001) |
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#define | F2_F3_FIFO_RD_UNDERFLOW ((uint32_t)0x0002) |
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#define | F2_F3_FIFO_WR_OVERFLOW ((uint32_t)0x0004) |
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#define | COMMAND_ERROR ((uint32_t)0x0008) |
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#define | DATA_ERROR ((uint32_t)0x0010) |
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#define | F2_PACKET_AVAILABLE ((uint32_t)0x0020) |
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#define | F3_PACKET_AVAILABLE ((uint32_t)0x0040) |
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#define | F1_OVERFLOW ((uint32_t)0x0080) |
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#define | GSPI_PACKET_AVAILABLE ((uint32_t)0x0100) |
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#define | MISC_INTR1 ((uint32_t)0x0200) |
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#define | MISC_INTR2 ((uint32_t)0x0400) |
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#define | MISC_INTR3 ((uint32_t)0x0800) |
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#define | MISC_INTR4 ((uint32_t)0x1000) |
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#define | F1_INTR ((uint32_t)0x2000) |
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#define | F2_INTR ((uint32_t)0x4000) |
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#define | F3_INTR ((uint32_t)0x8000) |
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#define | BUS_OVERFLOW_UNDERFLOW (F1_OVERFLOW | F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW) |
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#define | STATUS_DATA_NOT_AVAILABLE ((uint32_t)0x00000001) |
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#define | STATUS_UNDERFLOW ((uint32_t)0x00000002) |
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#define | STATUS_OVERFLOW ((uint32_t)0x00000004) |
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#define | STATUS_F2_INTR ((uint32_t)0x00000008) |
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#define | STATUS_F3_INTR ((uint32_t)0x00000010) |
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#define | STATUS_F2_RX_READY ((uint32_t)0x00000020) |
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#define | STATUS_F3_RX_READY ((uint32_t)0x00000040) |
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#define | STATUS_HOST_CMD_DATA_ERR ((uint32_t)0x00000080) |
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#define | STATUS_F2_PKT_AVAILABLE ((uint32_t)0x00000100) |
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#define | STATUS_F2_PKT_LEN_MASK ((uint32_t)0x000FFE00) |
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#define | STATUS_F2_PKT_LEN_SHIFT ((uint32_t)9) |
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#define | STATUS_F3_PKT_AVAILABLE ((uint32_t)0x00100000) |
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#define | STATUS_F3_PKT_LEN_MASK ((uint32_t)0xFFE00000) |
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#define | STATUS_F3_PKT_LEN_SHIFT ((uint32_t)21) |
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#define | SPI_FRAME_CONTROL ((uint32_t)0x1000D) |
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