From 409e01f32787d7327fd732396d08c52051ab4746 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Wed, 18 Sep 2024 16:32:35 +0900 Subject: [PATCH] arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25 To avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name. Only the reset-pin is actually needed. Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20240918073236.648-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 1aa3b97e4fd5..98cfa3abb809 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -124,7 +124,7 @@ &pcie3x1 { num-lanes = <1>; pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1m0_pins>; + pinctrl-0 = <&pcie30x1_reset_h>; reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_minipcie>; status = "okay"; @@ -149,6 +149,10 @@ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; + pcie30x1_reset_h: pcie30x1-reset-h { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie30x2_reset_h: pcie30x2-reset-h { rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; -- 2.42.0