]> Git Repo - linux.git/commit
riscv: move sifive_l2_cache.c to drivers/soc
authorChristoph Hellwig <[email protected]>
Thu, 7 Nov 2019 09:20:39 +0000 (10:20 +0100)
committerPaul Walmsley <[email protected]>
Fri, 20 Dec 2019 11:40:24 +0000 (03:40 -0800)
commit9209fb51896fe0eef8dfac85afe1f357e9265c0d
treed169219e01f1c6d347937657ff7404a141531cca
parent01f52e16b868ce22069425c69f2c8e3ef4077b5c
riscv: move sifive_l2_cache.c to drivers/soc

The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <[email protected]>
Reviewed-by: Borislav Petkov <[email protected]>
[[email protected]: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley <[email protected]>
MAINTAINERS
arch/riscv/mm/Makefile
arch/riscv/mm/sifive_l2_cache.c [deleted file]
drivers/edac/Kconfig
drivers/soc/Kconfig
drivers/soc/Makefile
drivers/soc/sifive/Kconfig [new file with mode: 0644]
drivers/soc/sifive/Makefile [new file with mode: 0644]
drivers/soc/sifive/sifive_l2_cache.c [new file with mode: 0644]
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