]> Git Repo - linux.git/commit
Introduce cpu_dcache_is_aliasing() across all architectures
authorMathieu Desnoyers <[email protected]>
Thu, 15 Feb 2024 14:46:32 +0000 (09:46 -0500)
committerAndrew Morton <[email protected]>
Thu, 22 Feb 2024 23:27:19 +0000 (15:27 -0800)
commit8690bbcf3b7010b31fdbf3851e1add6ae19b8624
tree8b571309484074613ae93ac95b9d75d6b8144e4b
parent1df4ca0155acb37b9b1d03ab91323d70a309ff54
Introduce cpu_dcache_is_aliasing() across all architectures

Introduce a generic way to query whether the data cache is virtually
aliased on all architectures. Its purpose is to ensure that subsystems
which are incompatible with virtually aliased data caches (e.g. FS_DAX)
can reliably query this.

For data cache aliasing, there are three scenarios dependending on the
architecture. Here is a breakdown based on my understanding:

A) The data cache is always aliasing:

* arc
* csky
* m68k (note: shared memory mappings are incoherent ? SHMLBA is missing there.)
* sh
* parisc

B) The data cache aliasing is statically known or depends on querying CPU
   state at runtime:

* arm (cache_is_vivt() || cache_is_vipt_aliasing())
* mips (cpu_has_dc_aliases)
* nios2 (NIOS2_DCACHE_SIZE > PAGE_SIZE)
* sparc32 (vac_cache_size > PAGE_SIZE)
* sparc64 (L1DCACHE_SIZE > PAGE_SIZE)
* xtensa (DCACHE_WAY_SIZE > PAGE_SIZE)

C) The data cache is never aliasing:

* alpha
* arm64 (aarch64)
* hexagon
* loongarch (but with incoherent write buffers, which are disabled since
             commit d23b7795 ("LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE"))
* microblaze
* openrisc
* powerpc
* riscv
* s390
* um
* x86

Require architectures in A) and B) to select ARCH_HAS_CPU_CACHE_ALIASING and
implement "cpu_dcache_is_aliasing()".

Architectures in C) don't select ARCH_HAS_CPU_CACHE_ALIASING, and thus
cpu_dcache_is_aliasing() simply evaluates to "false".

Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future
work. This would be useful to gate features like XIP on architectures
which have aliasing CPU dcache-icache but not CPU dcache-dcache.

Use "cpu_dcache" and "cpu_cache" rather than just "dcache" and "cache"
to clarify that we really mean "CPU data cache" and "CPU cache" to
eliminate any possible confusion with VFS "dentry cache" and "page
cache".

Link: https://lore.kernel.org/lkml/[email protected]/
Link: https://lkml.kernel.org/r/[email protected]
Fixes: d92576f1167c ("dax: does not work correctly with virtual aliasing caches")
Signed-off-by: Mathieu Desnoyers <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Vishal Verma <[email protected]>
Cc: Dave Jiang <[email protected]>
Cc: Matthew Wilcox <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Russell King <[email protected]>
Cc: Alasdair Kergon <[email protected]>
Cc: Christoph Hellwig <[email protected]>
Cc: Dave Chinner <[email protected]>
Cc: Heiko Carstens <[email protected]>
Cc: kernel test robot <[email protected]>
Cc: Michael Sclafani <[email protected]>
Cc: Mike Snitzer <[email protected]>
Cc: Mikulas Patocka <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
22 files changed:
arch/arc/Kconfig
arch/arc/include/asm/cachetype.h [new file with mode: 0644]
arch/arm/Kconfig
arch/arm/include/asm/cachetype.h
arch/csky/Kconfig
arch/csky/include/asm/cachetype.h [new file with mode: 0644]
arch/m68k/Kconfig
arch/m68k/include/asm/cachetype.h [new file with mode: 0644]
arch/mips/Kconfig
arch/mips/include/asm/cachetype.h [new file with mode: 0644]
arch/nios2/Kconfig
arch/nios2/include/asm/cachetype.h [new file with mode: 0644]
arch/parisc/Kconfig
arch/parisc/include/asm/cachetype.h [new file with mode: 0644]
arch/sh/Kconfig
arch/sh/include/asm/cachetype.h [new file with mode: 0644]
arch/sparc/Kconfig
arch/sparc/include/asm/cachetype.h [new file with mode: 0644]
arch/xtensa/Kconfig
arch/xtensa/include/asm/cachetype.h [new file with mode: 0644]
include/linux/cacheinfo.h
mm/Kconfig
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