ARM: dts: vexpress: Support GICC_DIR operations

ARM: dts: vexpress: Support GICC_DIR operations

The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT.  Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt
deactivation.

Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
[[email protected]: included same fix for tc1 platform too]
Signed-off-by: Sudeep Holla <[email protected]>