drm/amd/display: flicking observed while installing driver on Navi10 CF

[WHY] value of dchub_ref_clock is decided by dchubbub global timer
settings which is programmed by vbios command table disp_init.
for multi-GPU case, vbios is posted only for primary GPU. without
vbios posted for the secondary GPU, value of dchub_ref_clock is not
set properly. this value will affect dcn bandwidth calcuation and
cause underflow. user will see screen flicking during driver
installation for dual GPU case.

[HOW] dc init_hw always call vbios command table disp_init to
make sure dchubbub global timer is configured and enable.

Signed-off-by: hersen wu <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL

[Why]
The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
embedded display. Currently we do not actually read this register's values,
so during power down we think that this display is already off, so we skip
calling into VBIOS to actually turn it off.

[How]
 - add relevant fields to shift / mask initialization

Signed-off-by: Joshua Aberback <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: revert wait in pipelock

[why]
Previous workaround to prevent a vsync flip to be converted
to immediate flip is no longer needed, and is risky because
there are cases where it can result in infinite loop.

[how]
Remove wait loop (which is potentially infinite) before locking
pipe

Signed-off-by: Jun Lei <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Use res_cap to acquire i2c instead of pipe count

[Why]
We should be using the ddc_num from res_caps. As the
pipe count != number of i2c resources.

[How]
Use ddc_num from res_cap instead of pipe count.

Signed-off-by: Derek Lai <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags

[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.

[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONTROL.

Signed-off-by: Bayan Zabihiyan <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix DML not calculating delivery time

[why]
Calculating DCFCLK DS time requires calculating
delivery time for luma/chroma, but this value is
not calculated in DMLv2, it was inadvertently
removed when porting DMLv2

[how]
Add the calculation back

Signed-off-by: Jun Lei <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: MST topology debugfs

DRM provides drm_dp_mst_dump_topology, which prints
useful information about MST devices

Hook this up to a debugfs file named amdgpu_mst_topology

Signed-off-by: David Francis <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: set av_mute in hw_init for HDMI

[Description]
OS will reserve HW state in UEFI mode.
Driver init_hw reset to RGB which caused HDMI green in YCbCr mode.
read HW blank_color based on acc_mode.

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Add Logging for Gamma Related information

[Why]
A recent bug showed that logging would be useful in debugging
various gamma issues.

[How]
Add logging in dc.
Fix formatting for easier graphing.

Signed-off-by: Wyatt Wood <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Enable HW rotation

[Why] HW rotation is not enabled. Calculations for cursor rotation
are wrong for the values passed to set_cursor_position.

[How] Swap Src rect and height and vertically mirror surface for
the correct surface rotation direction. Cursor position is rotated
according to angle. Offset calculations are tweaked for non-rotated
cursor hotspot and width/height.

Signed-off-by: Jaehyun Chung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: add Cursor Degamma logic for DCN2

[Why]
We need to have the ability to to tell us set degamma on the cursor.

[How]
Pass a flag down to register programming that tells us if the
current surface format needs cursor degamma.

Signed-off-by: Bayan Zabihiyan <[email protected]>
Reviewed-by: Krunoslav Kovac <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix odm validation

Update bw validation to use prev and next odm pipe pointers
for populating dml inputs.

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix odm stream release

Need to memset all odm pipes when calling dc_remove_stream_from_ctx

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix dcn20 odm dpp programming

dcn20 requires special casing for odm.
This change treats odm as alternative to mpc tree on dcn20.

This is planned to be fixed in a future refactor

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Fix number of slices not being checked for dsc

[why]
num_slices_h was not being checked

[How]
Fix the typo and check num_slices_h

Signed-off-by: Nikola Cornij <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix odm pipe copy

ODM next and prev pipe were missing from dc_copy_state

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Nikola Cornij <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix trigger not generated for freesync

[Why]
In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this
front porch is fixed and in these hardware freesync does not work.

[How]
Change the programming to generate a pulse so that the event will be
triggered, front porch will be cut short and freesync will work.

Signed-off-by: Yogesh Mohan Marimuthu <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix stuck test pattern on right half of display

[why]
With visual confirm enabled, displays where ODM combine is enabled
has a test pattern stuck on the right half of the display even
though the display is unblanked.

[how]
Add a condition to not show the colour ramp test pattern when the
display is unblanked.

Signed-off-by: Zi Yu Liao <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: support spdif

[Description]
port spdif fix to staging:
 spdif hardwired to afmt inst 1.
 spdif func pointer
 spdif resource allocation (reserve last audio endpoint for spdif only)

Signed-off-by: Charlene Liu <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Refactoring VTEM

[Why]
Video Timing Extended Metadata packet (VTEM) is not
specific to freesync. So move it out of freesync module

[How]
- Moved VTEM from freesync module to info_packet module
- Created new structure for VTEM parameters that can be used for VRR
and FVA

Signed-off-by: Ahmad Othman <[email protected]>
Reviewed-by: Chris Park <[email protected]>
Acked-by: Ahmad Othman <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: 3.2.47

Signed-off-by: Anthony Koo <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: remove unused function

[Why]
This function is not being used, it was left in
when introducing DCN2

[How]
Remove the function

Signed-off-by: Qingqing Zhuo <[email protected]>
Reviewed-by: Eric Bernstein <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: cleaned up coding error in init_hw

[why]
during a refactor a redundant code that has unknown behaviour was added.

[how]
removed old bad code

Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
Signed-off-by: Martin Leung <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Add VM page fault handle implementation

[How] Allocate memory for default page and program memory block addr
into default page addr register.

Signed-off-by: Jaehyun Chung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: refactor Device ID for external chips

IEEE OUI will now be used while referring to certain vendors.
instead of normal index

Signed-off-by: Qingqing Zhuo <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Zero-out dsc init regs

[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.

[how]
Zero-out PPS data structure at initialization time before it's
populated

Fixes: 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end")
Signed-off-by: Nikola Cornij <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Implement voltage limitation stub

add new function to get the voltage at the end of
dcn_validate_bandwidth, to check against the
highest voltage we allow.

Created a stub to allow for optimizations

Signed-off-by: Joseph Gravenor <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Acked-by: Sun peng Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: add null checks before logging

Adding NULL checks to various parameters in log_tf, to avoid
nullptr errors

Signed-off-by: Wyatt Wood <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Acked-by: Nikola Cornij <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: set Hratio and VRatio in dml

Set the writeback Hratio and Vratio in dml.

Signed-off-by: Ilya Bakoulin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix dp stream enable

A previous odm change broke stream enable by always setting
n_multiply as if odm was on.

This fixes the check for odm by making sure opp count is >1
rather than not 0.

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: load iram for abm 2.3

[Why]
ABM 2.3 firmware expects information in iRAM that differs from previous
versions of ABM, so a mechanism is required to provide it with that
information.

[How]
Extend the existing iRAM definition to include parameters added by
ABM 2.3, and load it if DMCU is running ABM 2.3.

Signed-off-by: Josip Pavic <[email protected]>
Reviewed-by: Anthony Koo <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix MPO HUBP underflow with Scatter Gather

[why]
With Scatter Gather enabled, HUBP underflows during MPO enabled video
playback. hubp_init has a register write that fixes this problem, but
the register is cleared when HUBP gets power gated.

[how]
Make a call to hubp_init during enable_plane, so that the fix can
be applied after HUBP powers back on again.

Signed-off-by: Zi Yu Liao <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix audio endpoint not getting disabled issue

[Why]
Disable_audio_stream gets enum option as a paramenter which will decide
if we free acquired resources or not. However checks for the option is
guarded by the other condition which check if audio stream is getting
diabled more than once. With both conditions combined, if we attempt to
disable audio stream twice in a row, first with keep and second with
free as an option, we will never free any resources, which will make
system think there is audio endpoint connected even after we plug out
the device

[How]
Get rid of option as parameter to disable_audio_stream and move the part
of the code that free acquired resources to outside where to keep or to
free resources is actually determined

Signed-off-by: Su Sung Chung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Delete dead code in command_table_helper

[Why]
dig_encoder_sel_to_atom will always return zero on any ASIC version
past DCE80 since programming of the FE selection is handled by
driver, but the translation code was left in the function, making
it look like a coding error.

[How]
Remove code that has no effect, and replace with a comment describing
why it returns zero.

Signed-off-by: Julian Parkin <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: re structure odm to allow 4 to 1 support

Currently odm is handled using top_bottom pipe by special casing
the differing opps to differentiate from mpc combine.

Since top/bottom pipe list was made to track mpc muxing this creates
difficulties in adding a 4 pipe odm case support.

Rather than continue using mpc combine list, this change reworks odm
to use it's own linked list to keep track of odm combine pipes. This
also opens up options for using mpo with odm, if a practical use case
is ever found.

Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: set adev->num_vmhubs for gmc6,7,8

So that we properly handle them on older asics.

Fixes: 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm hub")
Tested-by: Tom St Denis <[email protected]>
Reviewed-by: Xiaojie Yuan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/display: add flag for multi-display mclk switching

Add a dcfeaturemask flag for mclk switching.  Disable by default;
enable once the feature has seen more testing.

Set amdgpu.dcfeaturemask=2 on the kernel command line in grub
to enable this.

Acked-by: Evan Quan <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: update bw_calcs to take pipe sync into account (v3)

Properly set all_displays_in_sync so that when the data is
propagated to powerplay, it's set properly and we can enable
mclk switching when all monitors are in sync.

v2: fix logic, clean up
v3: check for blending chains, simplify logic

Acked-by: Evan Quan <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay/vega10: enable mclk switching if monitors are synced

If DC has synced the displays, we can enable mclk switching to
save power.

Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay/smu7: enable mclk switching if monitors are synced

If DC has synced the displays, we can enable mclk switching to
save power.

Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/powerplay: Fix Vega20 power reading again

For the 40.46 SMU release, they changed CurrSocketPower to
AverageSocketPower, but this was changed back in 40.47 so just check if
it's 40.46 and make the appropriate change

Tested with 40.45, 40.46 and 40.47 successfully

Signed-off-by: Kent Russell <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amd/amdkfd: add Arcturus vf DID support

Add the virtual function PCI device id.

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Frank.Min <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerpaly: fix navi series custom peak level value error

fix other navi asic set peak performance level error.
because the navi10_ppt.c will handle navi12 14 asic,
it will use navi10 peak value to set other asic, it is not correct.

after patch:
only navi10 use custom peak value, other asic will used default value.

Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: correct ras error count type

Use unsigned long type for the same ras count variable.
This will avoid overflow on 64 bit system.

Signed-off-by: Guchun Chen <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix calc_pll_max_vco_construct

This was broken by a previous change switching to cached fw_info.
Fixed by inverting a valid bool check.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111432
Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create")
Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable VCN DPG for Renoir

This will enable indirect SRAM loading for VCN DPG mode initialization.

Signed-off-by: Thong Thai <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Reviewed-by: Prike Liang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"

This reverts commit 444a0fea5107e9ad7e3cbbafed78678489e31713.

We are ready to enable it now.

Signed-off-by: Thong Thai <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: update gc/sdma goldensetting for rn

This patch updates gc/sdma goldensetting for renoir

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: Disable renoir smu feature retrieve for the moment

To avoid the dpm frequence range get failed when DPM enabled and it
will be enabled later once handle well the feature bit map struct.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: enable renoir dpm feature

enable the dpm feature for the renoir.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Aaron Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable SDMA power gating for rn

Enable SDMA PG flag during device ip early init.

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Prike Liang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/sdma4: set sdma clock gating for rn

Add support for SDMA clockgating on RN.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/mmhub1: set mmhub clock gating for rn

setup mmhub clockgating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable DF clock gating for rn

Enable DF clock gating during DF IP early init.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable athub clock gating for rn

Enable athub MG and LS clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable IH clock gating for rn

Enable IH clock gating during IH block initialized.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable vcn clock gating for rn

Enable VCN middle grain clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable rom clock gating for rn

Enable rom light sleep clock gating.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Prike Liang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable HDP clock gating for rn

Enable HDP light sleep clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable BIF clock gating for rn

Enable BIF light sleep clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable sdma clock gating for rn

Enable sdma middle grain and light sleep clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable mmhub clock gating for rn

Enable mmhub midle grain and light sleep clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable gfx clock gating for rn

Enable gfx cg/mg/cp etc clock gating.

Signed-off-by: Prike Liang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: add DPMCLOCKS table implementation

This patch adds add DPMCLOCKS table implementation
Rename smu_populate_smc_pptable to smu_populate_smc_tables

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: init smu tables for rn

Initialize smu tables for renoir:
WATERMARKS/DPMCLOCKS/SMU_METRICS

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: add smu tables for rn

add and map smu tables for renoir

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: using valid mapping check for rn

Check whether the message mapping is valid

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: fix checking gfxoff status for rn

For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check
gfxoff status. For the first time to enter gfxoff status,
it maybe takes about one second more. So just set the max
timeout to 5s.

GFXOFF_STATUS(bits 2:1)'s description is below:
0=GFXOFF(default).
1=Transition out of GFX State.
2=Not in GFXOFF.
3=Transition into GFXOFF.

Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Aaron Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: add and enable gfxoff feature

This patch updates gfxoff feature.

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: add set_gfx_cgpg implement (v2)

add set_gfx_cgpg implement

v2: check if using sw_smu (Alex)

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2)

This interface support SMU_MSG_GetDriverIfVersion
and SMU_MSG_GetSmuVersion checking.

v2: squash in driver_if changes (Alex)

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: powerup sdma/vcn for all apu series

All apu series need powerup sdma and vcn via smu messages.

Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: add Renoir VCN power management

Thus VCN can be powered up for normal operations

Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: skip dpm init for renoir

Renoir DPM is not functional so far, we skip it for the comment.
Will revert this patch once SMU 12 is functional.

Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir

1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir
2.adjust smu ip block ahead of gfx&sdma ip block

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: add smu ip block for renoir (v2)

add swSMU [smu_v12_0] for renoir

v2: whitespace fixes (Alex)

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir

add smu_v12_0.c & smu_v12_0.h for renoir

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3)

Add renoir_ppt and map ppsmc to amdgpu_smu.h

v2: squash in ppsmc updates (Alex)
v3: squash in driver_if updates (Alex)

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: add smu12_driver_if.h (v3)

This patch adds smu12_driver_if.h

v2: squash in updates (Alex)
v3: more updates (Alex)

Signed-off-by: Aaron Liu <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2)

This is the SMU v12 driver message interface.

v2: squash in updates

Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix a potential null pointer dereference

Currently the pointer init_data is dereferenced on the assignment
of fw_info before init_data is sanity checked to see if it is null.
Fix te potential null pointer dereference on init_data by only
performing dereference after it is null checked.

Addresses-Coverity: ("Dereference before null check")
Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create")
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: remove redundant assignment to variable baco_state

Variable baco_state is initialized to a value that is never read and it is
re-assigned later. The initialization is redundant and can be removed.

Addresses-Coverity: ("Unused Value")
Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: Make deallocate_hiq_sdma_mqd static

Fix sparse warning:

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:1846:6:
 warning: symbol 'deallocate_hiq_sdma_mqd' was not declared. Should it be static?

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x

v2: set num_types based on num_instances

navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:

(enable irq for sdma0) * 1 time
(enable irq for sdma1) * 1 time
(disable irq for sdma1) * 6 times

as a result, after gpu reset, interrupt for sdma1 is lost.

Signed-off-by: Xiaojie Yuan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Enable SST DSC in DM

In create_stream_for_sink, check for SST DP connectors

Parse DSC caps to DC format, then, if DSC is supported,
compute the config

DSC hardware will be programmed by dc_commit_state

Tested-by: Mikita Lipski <[email protected]>
Signed-off-by: David Francis <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amd/display: Fix underscan not using proper scaling"

This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.

This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timing

Signed-off-by: David Francis <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amd/display: add global master update lock for DCN2"

This reverts commit 6c5be4ac630805d3a3b20157a0c6421ef815fe78.

This commit was accidentally promoted twice

Signed-off-by: David Francis <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amd/display: navi10 bring up skip dsc encoder config"

This reverts commit ec8763486dd3d2fb585c2e6747520406e7dcef98.

Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works

Signed-off-by: David Francis <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amd/display: skip dsc config for navi10 bring up"

This reverts commit 9e14d4f17e23ce46d346a6a22a295b4a65b9d918.

optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled

The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are not associated
with dsc, and power gating on dsc still has an issue on
non-dsc monitors where the dsc hardware block is never init
and so cannot respond to power gating requests. Therefore,
those are left as is

Signed-off-by: David Francis <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: fix dma_fence_wait without reference

We need to grab a reference to the fence we wait for.

Signed-off-by: Christian König <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/powerplay: Fix Vega20 Average Power value v4

The SMU changed reading from CurrSocketPower to AverageSocketPower, so
reflect this accordingly. This fixes the issue where Average Power
Consumption was being reported as 0 from SMU 40.46-onward

v2: Fixed headline prefix
v3: Add check for SMU version for proper compatibility
v4: Style fix

Signed-off-by: Kent Russell <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amd/amdgpu: add Arcturus vf DID support

Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Frank.Min <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: unity mc base address for arcturus

arcturus for sriov would use the unified mc base address

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Frank.Min <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: disable agp for sriov

Since agp is not used for sriov, just disable it

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Frank.Min <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: silence a warning in smu_v11_0_setup_pptable

I think gcc is confused as I don't see how size could be used
uninitialized, but go ahead and silence the warning.

Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: remove set but not used variable 'pdd'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c: In function restore_process_worker:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:949:29: warning:
 variable pdd set but not used [-Wunused-but-set-variable]

It is not used since
commit 5b87245faf57 ("drm/amdkfd: Simplify kfd2kgd interface")

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: remove duplicated include from dc_link.c

Remove duplicated include.

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: remove duplicated include from gfx_v9_0.c

Remove duplicated include.

Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: remove set but not used variable 'psp_enabled'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init':
drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning:
 variable 'psp_enabled' set but not used [-Wunused-but-set-variable]

It's not used since inroduction in
commit c6b6a42175f5 ("drm/amdgpu: add navi10 common ip block (v3)")

Signed-off-by: YueHaibing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Fix 32-bit divide error in wait_for_alt_mode

When building arm32 allyesconfig:

ld.lld: error: undefined symbol: __aeabi_uldivmod
>>> referenced by dc_link.c
>>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a
>>> referenced by dc_link.c
>>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a

time_taken_in_ns is of type unsigned long long so we need to use div_u64
to avoid this error.

Fixes: b5b1f4554904 ("drm/amd/display: Enable type C hotplug")
Reported-by: Randy Dunlap <[email protected]>
Acked-by: Randy Dunlap <[email protected]> # build-tested
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Nathan Chancellor <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>