Ville Syrjälä [Thu, 23 May 2024 18:28:18 +0000 (21:28 +0300)]
drm/i915: Bury c8_planes_changed() in intel_color_check()
The c8_planes_changed() check in the high level atomic code is
a bit of an eyesore. Push it inside intel_color_check() so the
high level code doesn't have to care about this stuff.
Ville Syrjälä [Thu, 23 May 2024 18:28:17 +0000 (21:28 +0300)]
drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check()
Move the intel_crtc_needs_color_update() into intel_color_check()
so that the caller doesn't have to care about this. This will
also enable us to hide the c8_planes_changed() thing better.
Ville Syrjälä [Thu, 23 May 2024 18:28:16 +0000 (21:28 +0300)]
drm/i915: Plumb the entire atomic state into intel_color_check()
Bunch of stuff in intel_color_check() needs to look at both the
old and new crtc states. Currently we do that by digging the
full atomic state via the crtc_state->state pointer. That thing
is a total footgun if I ever saw one, as it's only valid during
specific parts of the atomic flow. A lot of people have been
bitten by this thing in the past when trying to use it after
it's no longer valid.
Take a small step towards elimination of the footgun by not
using it in the inte_color_check(). Instead we plumb in the
entire atomic state all the way from the top.
Ville Syrjälä [Fri, 24 May 2024 15:50:00 +0000 (18:50 +0300)]
drm/i915: Fix SEL_FETCH_{SIZE,OFFSET} registers
Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic
copy-paste fail on my part.
I even had a small test to confirm that the old and new register
offsets match, but somehow I must have screwed things up when
running it, and likely just ended up comparing the old defines
against themselves :/
Imre Deak [Tue, 21 May 2024 14:30:22 +0000 (17:30 +0300)]
drm/i915: Fix audio component initialization
After registering the audio component in i915_audio_component_init()
the audio driver may call i915_audio_component_get_power() via the
component ops. This could program AUD_FREQ_CNTRL with an uninitialized
value if the latter function is called before display.audio.freq_cntrl
gets initialized. The get_power() function also does a modeset which in
the above case happens too early before the initialization step and
triggers the
"Reject display access from task"
error message added by the Fixes: commit below.
Fix the above issue by registering the audio component only after the
initialization step.
Ville Syrjälä [Thu, 16 May 2024 13:56:15 +0000 (16:56 +0300)]
drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
for the SEL_FETCH_PLANE registers. A bit more tedious to have
to define 8 raw register offsets for everything, but perhaps
a bit easier to understand since we use a standard mechanism
now instead of hand rolling the arithmetic.
Also bloat-o-meter says:
add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326)
Function old new delta
icl_plane_update_arm 510 446 -64
icl_plane_disable_sel_fetch_arm.isra 158 54 -104
icl_plane_update_noarm 1898 1740 -158
Total: Before=2574502, After=2574176, chg -0.01%
v2: s/mtl+/tgl+/ comments to reflect actual reality
Ville Syrjälä [Thu, 16 May 2024 13:56:13 +0000 (16:56 +0300)]
drm/i915: Simplify PIPESRC_ERLY_TPT definition
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().
Ville Syrjälä [Mon, 20 May 2024 17:14:59 +0000 (20:14 +0300)]
drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
s/mtl+/tgl+/ as that's where this was introduced
Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
actually match the normal CUR_CTL register
Ville Syrjälä [Fri, 17 May 2024 17:12:08 +0000 (20:12 +0300)]
drm/i915: Add skl+ plane name aliases to enum plane_id
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
Vidya Srinivas [Mon, 20 May 2024 16:56:34 +0000 (22:26 +0530)]
drm/i915/dpt: Make DPT object unshrinkable
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Jani Nikula [Wed, 15 May 2024 16:56:50 +0000 (19:56 +0300)]
drm/i915/pciids: switch to xe driver style PCI ID macros
The PCI ID macros in xe_pciids.h allow passing in the macro to operate
on each PCI ID, making it more flexible. Convert i915_pciids.h to the
same pattern.
INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
unconditionally uses INTEL_QUANTA_VGA_DEVICE().
Jouni Högander [Fri, 17 May 2024 07:30:03 +0000 (10:30 +0300)]
drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits +
5 lines added by the HW. Take this into account in calculation and when
writing the IO Wake lines.
v2: maximum line count is 68 (6 bits + 5 lines added by HW)
Nirmoy Das [Thu, 16 May 2024 15:14:03 +0000 (17:14 +0200)]
drm/i915/selftests: Set always_coherent to false when reading from CPU
Commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
was not complete as for non LLC sharing platforms cpu read can happen
from LLC which probably doesn't have the latest changes made by GPU.
Jani Nikula [Fri, 10 May 2024 11:22:18 +0000 (14:22 +0300)]
drm/i915/pciids: don't include WHL/CML PCI IDs in CFL
It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI
IDs. Even if we treat them the same in a lot of places, CML is a
platform of its own, and the lists of PCI IDs should not conflate them.
Largely go by the idea that if a platform has a name, group its PCI IDs
together.
That said, AML is special, having both KBL and CFL variants. Leave that
alone.
Ville Syrjälä [Fri, 10 May 2024 15:23:29 +0000 (18:23 +0300)]
drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.
The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.
Ville Syrjälä [Fri, 10 May 2024 15:23:27 +0000 (18:23 +0300)]
drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
Extract helpers to calculate the final wm/ddb register
values for skl+. Will allow me to more cleanly remove the
register write wrappers for these registers.
Currently every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro
Ville Syrjälä [Mon, 13 May 2024 16:59:09 +0000 (19:59 +0300)]
drm/i915: Shuffle the skl+ plane register definitions
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
v2: Define register contents after all offsets (Jani)
Jouni Högander [Fri, 10 May 2024 09:38:22 +0000 (12:38 +0300)]
drm/i915/psr: Split intel_psr2_config_valid for panel replay
Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.
v3:
- move early transport check to psr2 specific check
- check intel_psr2_config_valid only for non-Panel Replay case
v2:
- use psr2_global_enabled for panel replay as well
- goto unsupported instead of return when global enabled check fails
Jouni Högander [Fri, 10 May 2024 09:38:19 +0000 (12:38 +0300)]
drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.
Bspec: 53370, 68920
v4:
- use PSR2_STATUS for eDP Panel Replay
- handle intel_psr_wait_exit_locked as well
v3:
- do not use PSR2_STATUS for PSR1
v2:
- use intel_dp_is_edp to differentiate
- modify debugfs status as well
Jouni Högander [Fri, 10 May 2024 09:38:18 +0000 (12:38 +0300)]
drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
Currently intel_dp_get_su_granularity doesn't support panel replay.
This fix modifies it to support panel replay as well.
v4:
- use drm_dp_dpcd_readb instead of drm_dp_dpcd_read
- ensure return value is 0 if drm_dp_dpcd_readb fails
v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
v2: rely on PSR definitions on common bits
Jouni Högander [Fri, 10 May 2024 09:38:17 +0000 (12:38 +0300)]
drm/i915/psr: Detect panel replay selective update support
Add new boolean to store panel replay selective update support of sink into
intel_psr struct. Detect panel replay selective update support and store
it into this new boolean.
v3: Clear sink_panel_replay_su_support in intel_dp_detect
v2: Merge adding new boolean into this patch
Jouni Högander [Fri, 10 May 2024 09:38:14 +0000 (12:38 +0300)]
drm/i915/dp: Use always vsc revision 0x6 for Panel Replay
We are about to enable Panel Replay Selective update mode. Vsc revision 0x6
for Panel Replay no matter if it is selective update or full frame update
mode. Take this into account when preparing VSC SDP package.
Jouni Högander [Fri, 10 May 2024 09:38:13 +0000 (12:38 +0300)]
drm/i915/display: Do not print "psr: enabled" for on Panel Replay
After setting has_psr for panel replay as well crtc state dump is
improperly printing "psr: enabled" for Panel Replay as well. Fix this by
checking also has_panel_replay.
Luca Coelho [Fri, 10 May 2024 09:05:02 +0000 (12:05 +0300)]
Documentation/i915: remove kernel-doc for DMC wakelocks
The function descriptions are optional and have not yet been added to
the DMC wakelock code, so we shouldn't try to use it. Since this is a
regression, remove the kernel-doc entry for DMC wakelocks for now.
The proper documentation will be added in a future patch.
Jani Nikula [Fri, 10 May 2024 09:43:13 +0000 (12:43 +0300)]
drm/xe/display: remove unused xe->sb_lock
Nothing in xe needs xe->sb_lock. None of the i915 display code using
->sb_lock gets built with xe, and in any case that would be wrong as xe
uses gt->pcode.lock for this.
Ville Syrjälä [Fri, 10 May 2024 10:22:57 +0000 (13:22 +0300)]
drm/i915: Cleanup fbdev fb setup
We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function.
Both should be pointing at the same thing. Make things less
confusing by just getting existing fb from 'ifbdev->fb' at the
start and then sticking with the local 'fb' (renamed from the
'intel_fb') until the very end.
Ville Syrjälä [Fri, 10 May 2024 10:22:33 +0000 (13:22 +0300)]
drm/i915: Change intel_fbdev_fb_alloc() return type
Change intel_fbdev_fb_alloc() to return struct intel_fb instead
of struct drm_framebuffer. Let's us eliminate some annoying
aliasing variables in the fbdev setup code.
v2: Assing the results to the correct variable (Jani)
Fix xe's copy
Ville Syrjälä [Mon, 6 May 2024 12:57:15 +0000 (15:57 +0300)]
drm/i915: Constify 'fb' in during pinning
Make the 'fb' pointers const in the pinning code. We never
want to mutate these. Also nuke a few aliasing fb vs. intel_fb
cases by just using the more specific type everywhere in the
same function.
Uma Shankar [Thu, 9 May 2024 05:35:08 +0000 (11:05 +0530)]
drm/i915: Implement Audio WA_14020863754
WA_14020863754: Corner case with Min Hblank Fix can cause
audio hang
Issue: Previously a fix was made to avoid issues with extremely
small hblanks, called the "Min Hblank Fix". However, this can
potentially cause an audio hang.
Workaround :
During "Audio Programming Sequence" Audio Enabling -
When DP mode is enabled Set mmio offset 0x65F1C bit 18 = 1b,
before step #1 "Enable audio Presence Detect"
During "Audio Programming Sequence" Audio Disabling -
When DP mode is enabled Clear mmio offset 0x65F1C bit 18 = 0b,
after step #6 "Disable Audio PD (Presence Detect)"
If not clearing PD bit, must also not clear 0x65F1C bit 18 (leave = 1b)
v2: Update the platform checks (Jani Nikula)
v3: Limited the WA to LNL and BMG, added a helper (Matt Roper)
v4: Updated the bit naming, fixed redundant if statement
projects / linux.git / log