drm/dp_mst: Add branch bandwidth validation to MST atomic check

[why]
Adding PBN attribute to drm_dp_vcpi_allocation structure to
keep track of how much bandwidth each Port requires.
Adding drm_dp_mst_atomic_check_bw_limit to verify that
state's bandwidth needs doesn't exceed available bandwidth.
The funtion is called in drm_dp_mst_atomic_check after
drm_dp_mst_atomic_check_topology_state to fully verify that
the proposed topology is supported.

v2: Fixing some typos and indenting
v3: Return correct error enums if no bw space available

Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Add DSC enablement helpers to DRM

Adding a helper function to be called by
drivers outside of DRM to enable DSC on
the MST ports.

Function is called to recalculate VCPI allocation
if DSC is enabled and raise the DSC flag to enable.
In case of disabling DSC the flag is set to false
and recalculation of VCPI slots is expected to be done
in encoder's atomic_check.

v2: squash separate functions into one and call it per
port
v3: Fix comment typos

Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Manually overwrite PBN divider for calculating timeslots

[why]
For DSC case we cannot use topology manager's PBN divider
variable. The default divider does not take FEC into account.
Therefore the driver has to calculate its own divider based
on the link rate and lane count its handling, as it is hw specific.

[how]
Pass pbn_div as an argument, which is used if its more than
zero, otherwise default topology manager's pbn_div will be used.

Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Write DSC enable to MST DPCD

Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.

Use the cached dsc_aux field.

Reviewed-by: Wenjing Liu <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Validate DSC caps on MST endpoints

During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.

Use drm_dp_mst_dsc_aux_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.

Reviewed-by: Wenjing Liu <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Initialize DSC PPS variables to 0

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Add new quirk for Synaptics MST hubs

Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
support virtual DPCD registers, but do support DSC.
The DSC caps can be read from the physical aux,
like in SST DSC. These hubs have many different
DEVICE_IDs.  Add a new quirk to detect this case.

v2: Fix error when checking return of drm_dp_read_desc

Reviewed-by: Wenjing Liu <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux

Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
register might have to be written on the leaf port's DPCD,
its parent's DPCD, or the MST manager's DPCD. This function
finds the correct aux for the job.

As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual DPCD
is a DP feature new in DP v1.4, which exposes certain DPCD
registers on virtual ports.

v2: Remember to unlock mutex on all paths
v3: Refactor to match coding style and increase brevity
v4: - Check DSC capable MST sink connected directly to the device.
    - Check branch's port_parent to be set

Cc: Lyude Paul <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Fill branch->num_ports

This field on drm_dp_mst_branch was never filled

It is initialized to zero when the port is kzallocced.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.

v2: remember to decrement on port removal
v3: don't explicitly init to 0
v4: move decrement of num_ports to unlink_port function

Reviewed-by: Lyude Paul <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Add MST support to DP DPCD R/W functions

Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.

This means that DRM drivers can make MST DPCD read/writes.

v2: Fix spacing
v3: Dump dpcd access on MST read/writes
v4: Fix calling wrong function on DPCD write
v5: delete deprecated include of drmP.h

Reviewed-by: Lyude Paul <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Parse FEC capability on MST ports

As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.

The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)

That value is needed for FEC and DSC support

Store it on drm_dp_mst_port

Reviewed-by: Lyude Paul <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/dp_mst: Add PBN calculation for DSC modes

With DSC, bpp can be fractional in multiples of 1/16.

Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel

v2: Don't add separate function for this
v3: In the equation divide bpp by 16 as it is expected
not to leave any remainder
v4: Added DSC test parameters for selftest

Reviewed-by: Manasi Navare <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: David Francis <[email protected]>
Signed-off-by: Mikita Lipski <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: Improve kfd_process lookup in kfd_ioctl

Use filep->private_data to store a pointer to the kfd_process data
structure. Take an extra reference for that, which gets released in
the kfd_release callback. Check that the process calling kfd_ioctl
is the same that opened the file descriptor. Return -EBADF if it's
not, so that this error can be distinguished in user mode.

Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Philip Yang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded

For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
"interesting" modes would be disabled, leaving only low-res or low
framerate modes.

This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
clock is exceeded. Verified that 8K30 and 4K120 are now available and
working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700.

Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Thomas Anderson <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: add event type check before restart the authentication

[Why]
Some combined docks will always trigger CP_IRQ but there's nothing the driver
needs to take care of, but the CP_IRQ breaks the original hdcp state and
triggers the driver to restart the authentication.

[How]
Add the event type check before restart the authentication or resend the stream
management

Signed-off-by: Xiaodong Yan <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Add delay after h' watchdog timeout event

[WHY]
Some monitors trigger HDCP2.x timeout after reinitializing (e.g. toggling HDR)
by taking longer than expected to return h' (h prime)
Previously the 200ms watchdog timer retry count would hit
MAX_NUM_OF_ATTEMPTS (4), causing fallback to HDCP1.x

[HOW]
Adding a 1s delay after an h' watchdog timeout provides enough time
for affected monitors to return h' in time without hitting MAX_NUM_OF_ATTEMPTS

Signed-off-by: Michael Strauss <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: rx_validation failed resume from sleep

[why]
Most DP/HDMI monitors need more time to response rx_validation
request.

[how]
Add generic 1000ms delay.

Signed-off-by: Jing Zhou <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Return correct Error code for validate h_prime

[Why]
We are returning incorrect error code for validate h prime

[How]
Return the right Error code

Signed-off-by: Bhawanpreet Lakha <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: Fix hdcp1 create session

[Why]
PSP needs session ID to destroy a session, In the case where we fail
create session we don't have a session ID

[How]
Set the session ID before returning

Signed-off-by: Bhawanpreet Lakha <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix psp return condition for hdcp module

We are returning SUCCESS when hdcp_status != Success. Fix it.

Signed-off-by: Bhawanpreet Lakha <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd: use list_for_each_entry for list iteration.

list_for_each() can be replaced by the more concise
list_for_each_entry() here for iteration over the lists.
This change was reported by coccinelle.

Signed-off-by: Wambui Karuga <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: remove unnecessary braces around conditionals.

As single statement conditionals do not need to be wrapped around
braces, the unnecessary braces can be removed.

Signed-off-by: Wambui Karuga <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: remove boolean checks in if statements.

Remove unnecessary variable comparisions to true/false in if statements
and check the value of the variable directly.

Signed-off-by: Wambui Karuga <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amdgpu: Set no-retry as default."

This reverts commit 51bfac71cade386966791a8db87a5912781d249f.

This causes stability issues on some raven boards.  Revert
for now until a proper fix is completed.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/934
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206017
Reviewed-by: Felix Kuehling <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/gfx: simplify old firmware warning

Put it on one line to avoid whitespace issues when
printing in the log.

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/gmc10: use common invalidation engine helper

Rather than open coding it.  This also changes the free masks
to better reflect the usage by other components.

Acked-by: Felix Kuehling <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/gmc: move invaliation bitmap setup to common code

So it can be shared with newer GMC versions.

Reviewed-by: Felix Kuehling <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: updated UMC error address record with correct channel index

defined macros for repetitive for loops

Reviewed-by: Guchun Chen <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: resolved bug in UMC RAS CE query

switch CE counter register access' to use SMN

disable UMC indexing mode

Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: cleanup the interfaces for powergate setting through SMU

Provided an unified entry point. And fixed the confusing that the API
usage is conflict with what the naming implies.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: issue proper hdp flush for table transferring

Guard the content consistence between the view of GPU and CPU
during the table transferring.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: refine code to support no-dpm case

With "dpm=0", there will be no DPM enabled. The code
needs to be refined to support this.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: unified VRAM address for driver table interaction with SMU V2

By this, we can avoid to pass in the VRAM address on every table
transferring. That puts extra unnecessary traffics on SMU on
some cases(e.g. polling the amdgpu_pm_info sysfs interface).

V2: document what the driver table is for and how it works

Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: cache the watermark settings on system memory

So that we do not need to allocate a piece of VRAM for it. This
is a preparation for coming change which unifies the VRAM address
for all driver tables interaction with SMU.

Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/smu: custom pstate profiling clock frequence for navi series asics

add navi10 & navi14 pstate profiling clock value support.

Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: L1 Policy(5/5) - removed IH_CHICKEN from VF

Signed-off-by: Zhigang Luo <[email protected]>
Signed-off-by: Jane Jian <[email protected]>
Reviewed-by: Emily Deng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: L1 Policy(3/5) - removed ECC interrupt from VF

Signed-off-by: Zhigang Luo <[email protected]>
Signed-off-by: Jane Jian <[email protected]>
Reviewed-by: Emily Deng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhub

Signed-off-by: Zhigang Luo <[email protected]>
Signed-off-by: Jane Jian <[email protected]>
Reviewed-by: Emily Deng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/amdgpu: L1 Policy(1/5) - removed VM settings for mmhub and gfxhub from VF

Signed-off-by: Zhigang Luo <[email protected]>
Signed-off-by: Jane Jian <[email protected]>
Reviewed-by: Emily Deng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: removed GFX RAS support check in UMC ECC callback

enable GPU recovery in event of uncorrectable UMC error

Signed-off-by: John Clements <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: added function to wait for PSP BL availability

reduced duplicate code

increased wait time for PSP BL readiness

Signed-off-by: John Clements <[email protected]>
Reviewed-by: Guchun Chen <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use linux size macro to simplify ONE_Kib & One_Mib

replace internal size macro with linux size macro

Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Tianci Yin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: resolve bug in UMC 6 error counter query

iterate over all error counter registers in SMN space

removed support error counter access via MMIO

Reviewed-by: Guchun Chen <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: add smu11_driver_if_arcturus.h new OOB members

This is to fit the latest SMC firmware and it's backward compatible.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amd/amdgpu/sriov tdr enablement with pp_onevf_mode

Under sriov and pp_onevf mode,
1.take resume instead of hw_init for smc recover to avoid
potential memory leak.

2.add return condition inside smc resume function for
sriov_pp_onevf_mode and pm_enabled param.

Signed-off-by: Jack Zhang <[email protected]>
Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

amd/amdgpu/sriov enable onevf mode for ARCTURUS VF

Before, initialization of smu ip block would be skipped
for sriov ASICs. But if there's only one VF being used,
guest driver should be able to dump some HW info such as
clks, temperature,etc.

To solve this, now after onevf mode is enabled, host
driver will notify guest. If it's onevf mode, guest will
do smu hw_init and skip some steps in normal smu hw_init
flow because host driver has already done it for smu.

With this fix, guest app can talk with smu and dump hw
information from smu.

v2: refine the logic for pm_enabled.Skip hw_init by not
changing pm_enabled.
v3: refine is_support_sw_smu and fix some indentation
issue.

Signed-off-by: Jack Zhang <[email protected]>
Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: retrieve the enabled feature mask from cache

This is why those feature mask members designed for. And this
can reduce the SMU workload.

Signed-off-by: Evan Quan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: avoid deadlock on Vega20 swSMU routine

The lock required was already hold by its parent API.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: update UMC 6.1 RAS error counter register access path

use proper method for SMN register access

Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/smu: add helper function smu_get_dpm_level_range() for smu driver

this function can help smu driver to query dpm level clock range from
smu firmware.

Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: remove three set but not used variable

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/radeon_atombios.c: In function
‘radeon_get_atom_connector_info_from_object_table’:
drivers/gpu/drm/radeon/radeon_atombios.c:651:26: warning: variable
‘grph_obj_num’ set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/radeon_atombios.c:651:13: warning: variable
‘grph_obj_id’ set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/radeon_atombios.c:573:37: warning: variable
‘con_obj_type’ set but not used [-Wunused-but-set-variable]

They are never used, and so can be removed.

Signed-off-by: yu kuai <[email protected]>
Acked-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/powerplay: fix NULL pointer issue when SMU disabled

Fix smu related NULL pointer issue which occurs when SMU is disabled.

Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/smu: use unified variable smu->is_apu to check apu asic platform

use unified variable smu->is_apu to check apu asic in smu driver.

related patch:
drm/amd/powerplay: bypass dpm_context null pointer check guard for some
smu series

Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: amalgamated PSP TA invoke functions

reduce duplicate code

Reviewed-by: Guchun Chen <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: amalgamate PSP TA load/unload functions

reduce duplicate code

Reviewed-by: Guchun Chen <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: by default output PSP ret status in event of cmd failure

update log level from DRM_DEBUG_DRIVER to DRM_WARN

Reviewed-by: Guchun Chen <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: correct RLC firmwares loading sequence

Per confirmation with RLC firmware team, the RLC should
be unhalted after all RLC related firmwares uploaded.
However, in fact the RLC is unhalted immediately after
RLCG firmware uploaded. And that may causes unexpected
PSP hang on loading the succeeding RLC save restore
list related firmwares.
So, we correct the firmware loading sequence to load
RLC save restore list related firmwares before RLCG
ucode. That will help to get around this issue.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: add check for baco support on Arcturus

This is used to determine whether runtime pm can be
supported or not.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in display_rq_dlg_calc_21.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:85:6-13: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:88:2-9: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:225:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:226:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:251:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:252:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:256:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:257:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:267:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:269:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:682:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1013:1-9: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in display_rq_dlg_calc_20v2.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:110:6-13: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:113:2-9: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:243:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:244:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:267:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:268:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:272:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:273:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:283:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:285:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:673:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c:962:1-9: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in display_rq_dlg_calc_20.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:110:6-13: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:113:2-9: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:243:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:244:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:267:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:268:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:272:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:273:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:283:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:285:3-11: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:673:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c:961:1-9: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in dce_calcs.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:157:46-64: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:159:2-20: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:161:46-64: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:163:2-20: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:289:1-12: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:290:1-12: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:341:3-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:343:4-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in display_mode_vba_21.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c:4124:3-28: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c:4128:5-30: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c:5207:3-37: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in dcn20_hwseq.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:186:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c:189:2-10: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in dcn10_hw_sequencer.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:482:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:485:2-10: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: use true, false for bool variable in dc_link_ddc.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:593:6-9: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: use true, false for bool variable in vega20_hwmgr.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c:875:1-31: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/smu: make the set_performance_level logic easier to follow

Have every asic provide a callback for this rather than a mix
of generic and asic specific code.

Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

Revert "drm/amdgpu: simplify ATPX detection"

This reverts commit f5fda6d89afe6e9cedaa1c3303903c905262f6e8.

You can't use BASE_CLASS in pci_get_class.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/995
Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: simplify function return logic

Former return logic is redundant.

Signed-off-by: Guchun Chen <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/powerplay: support custom power profile setting

Support custom power profile mode settings on Arcturus.

Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amd/display: fix kernel_fpu_begin/_end() warnings

kernel_fpu_begin/_end() are already called inside dcn20_resource_construct,
and calling kernel_fpu_begin/_end() recursively triggers WARN_ON() when
CONFIG_X86_DEBUG_FPU is enabled.

[  107.060434] WARNING: CPU: 6 PID: 1370 at arch/x86/kernel/fpu/core.c:90 kernel_fpu_begin+0xbd/0xe0
<snip>
[  107.268197] Call Trace:
[  107.270751]  dcn20_patch_bounding_box+0x17/0x100 [amdgpu]
[  107.276204]  init_soc_bounding_box+0x1b3/0x5f0 [amdgpu]
[  107.281536]  ? _cond_resched+0x19/0x30
[  107.285307]  dcn20_resource_construct+0x3a9/0xa90 [amdgpu]
[  107.290957]  ? dcn20_resource_construct+0x3a9/0xa90 [amdgpu]
[  107.296621]  ? __alloc_pages_nodemask+0x16a/0x330
[  107.301476]  ? _cond_resched+0x19/0x30
[  107.305284]  ? kmem_cache_alloc_trace+0x197/0x230
[  107.310063]  ? _cond_resched+0x19/0x30
[  107.313783]  ? kmem_cache_alloc_trace+0x197/0x230
[  107.318691]  dcn20_create_resource_pool+0x42/0x70 [amdgpu]
[  107.324315]  dc_create_resource_pool+0x12d/0x170 [amdgpu]
[  107.329851]  dc_create+0x1b8/0x6a0 [amdgpu]
[  107.334013]  ? kmem_cache_alloc_trace+0x1e2/0x230
[  107.338832]  amdgpu_dm_init+0x13e/0x1c0 [amdgpu]
<snip>

Signed-off-by: Xiaojie Yuan <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: Avoid hanging hardware in stop_cpsch

Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.

Signed-off-by: Felix Kuehling <[email protected]>
Tested-by: Emily Deng <[email protected]>
Reviewed-by: shaoyunl <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: Improve HWS hang detection and handling

Move HWS hang detection into unmap_queues_cpsch to catch hangs in all
cases. If this happens during a reset, don't schedule another reset
because the reset already in progress is expected to take care of it.

Signed-off-by: Felix Kuehling <[email protected]>
Tested-by: Emily Deng <[email protected]>
Reviewed-by: shaoyunl <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: Remove unused variable

dqm->pipeline_mem wasn't used anywhere.

Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: shaoyunl <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdkfd: Fix permissions of hang_hws

Reading from /sys/kernel/debug/kfd/hang_hws would cause a kernel
oops because we didn't implement a read callback. Set the permission
to write-only to prevent that.

Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: shaoyunl <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu

Can expose it now that the khronos has exposed the
vlk extension.

Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Flora Cui <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use true, false for bool variable in amdgpu_psp.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:674:2-26: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:794:1-25: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:897:2-36: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1016:1-35: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1087:2-34: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1177:1-33: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use true, false for bool variable in amdgpu_debugfs.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:132:2-10: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:140:2-10: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:142:13-21: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use true, false for bool variable in amdgpu_device.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3961:1-19: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3981:1-19: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use true, false for bool variable in mxgpu_nv.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:255:2-20: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:267:2-20: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: use true, false for bool variable in mxgpu_ai.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:253:2-20: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:265:2-20: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true,false for bool variable in ni.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/ni.c:2020:2-15: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/radeon/ni.c:2088:2-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true,false for bool variable in cik.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/cik.c:8140:2-15: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/radeon/cik.c:8212:2-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true,false for bool variable in rv770.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/rv770.c:1706:2-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true, false for bool variable in evergreen.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/evergreen.c:4948:2-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true,false for bool variable in r600.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/r600.c:3056:2-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true,false for bool variable in si.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/si.c:6475:2-15: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/radeon/si.c:6542:2-15: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/radeon: use true,false for bool variable in r100.c

Fixes coccicheck warning:

drivers/gpu/drm/radeon/r100.c:1826:3-31: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/radeon/r100.c:1828:3-31: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/radeon/r100.c:2390:2-22: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/radeon/r100.c:2395:2-22: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: zhengbin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/smu: add peak profile support for navi12

Add defined peak sclk for navi12 peak profile mode.

Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/smu/navi: Adjust default behavior for peak sclk profile

Fetch the sclk from the pptable if there is no specified sclk for
the board.

Reviewed-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: add missed return value set for error case

Return value should be set when going to error handle tag
for error case, this can avoid potential invalid array
access by upper caller.

Signed-off-by: Guchun Chen <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: remove FB location config for sriov

FB location is already programmed by HV driver
for arcutus so remove this part

Signed-off-by: Frank.Min <[email protected]>
Reviewed-by: Emily Deng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: enable xgmi init for sriov use case

1. enable xgmi ta initialization for sriov
2. enable xgmi initialization for sriov

Signed-off-by: Frank.Min <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: remove memory training p2c buffer reservation(V2)

IP discovery TMR(occupied the top VRAM with size DISCOVERY_TMR_SIZE)
has been reserved, and the p2c buffer is in the range of this TMR, so
the p2c buffer reservation is unnecessary.

Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Reviewed-by: Xiaojie Yuan <[email protected]>
Signed-off-by: Tianci.Yin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: update the method to get fb_loc of memory training(V4)

The method of getting fb_loc changed from parsing VBIOS to
taking certain offset from top of VRAM

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Tianci.Yin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Ma Feng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: Remove unneeded variable 'ret' in amdgpu_device.c

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1036:5-8: Unneeded variable: "ret". Return "0" on line 1079

Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Ma Feng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/gfx: Add mmSDMA2-7_EDC_COUNTER to support Arcturus

Add mmSDMA2-7_EDC_COUNTER to support Arcturus

Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Yong Zhao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu/gfx: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus

Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus

Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Yong Zhao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>