Merge branches 'clk-leak', 'clk-rockchip', 'clk-renesas' and 'clk-at91' into clk-next

 - Clock power management for new SAMA7G5 SoC
 - Updates to the master clock driver and sam9x60-pll to be able to use
   cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while
   changing the frequency via DVFS
 - Power management refinement with the use of save_context()/restore_context()
   on each clock driver to specify their use in case of Backup mode only

* clk-leak:
  clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths

* clk-rockchip:
  clk: rockchip: use module_platform_driver_probe
  clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}
  clk: rockchip: rk3399: make CPU clocks critical

* clk-renesas:
  clk: renesas: r8a779[56]x: Add MLP clocks
  clk: renesas: r9a07g044: Add SDHI clock and reset entries
  clk: renesas: rzg2l: Add SDHI clk mux support
  clk: renesas: r8a779a0: Add RPC support
  clk: renesas: cpg-lib: Move RPC clock registration to the library
  clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller
  clk: renesas: r8a779a0: Add Z0 and Z1 clock support
  clk: renesas: r9a07g044: Add GbEthernet clock/reset
  clk: renesas: rzg2l: Add support to handle coupled clocks
  clk: renesas: r9a07g044: Add ethernet clock sources
  clk: renesas: rzg2l: Add support to handle MUX clocks
  clk: renesas: r8a779a0: Add TPU clock
  clk: renesas: rzg2l: Fix clk status function
  clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical

* clk-at91:
  clk: at91: sama7g5: set low limit for mck0 at 32KHz
  clk: at91: sama7g5: remove prescaler part of master clock
  clk: at91: clk-master: add notifier for divider
  clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
  clk: at91: clk-master: fix prescaler logic
  clk: at91: clk-master: mask mckr against layout->mask
  clk: at91: clk-master: check if div or pres is zero
  clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
  clk: at91: pmc: add sama7g5 to the list of available pmcs
  clk: at91: clk-master: improve readability by using local variables
  clk: at91: clk-master: add register definition for sama7g5's master clock
  clk: at91: sama7g5: add securam's peripheral clock
  clk: at91: pmc: execute suspend/resume only for backup mode
  clk: at91: re-factor clocks suspend/resume
  clk: at91: check pmc node status before registering syscore ops

Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-next

 - Use ARRAY_SIZE in qcom clk drivers
 - Remove some impractical fallback parent names in qcom clk drivers
 - GCC and RPMcc support for Qualcomm QCM2290 SoCs
 - GCC support for Qualcomm MSM8994/MSM8992 SoCs
 - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
 - Support for Mediatek MT8195 SoCs
 - Make Mediatek clk drivers tristate

* clk-qcom: (44 commits)
  clk: qcom: gdsc: enable optional power domain support
  clk: qcom: videocc-sm8250: use runtime PM for the clock controller
  clk: qcom: dispcc-sm8250: use runtime PM for the clock controller
  dt-bindings: clock: qcom,videocc: add mmcx power domain
  dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain
  clk: qcom: gcc-sc7280: Drop unused array
  clk: qcom: camcc: Add camera clock controller driver for SC7280
  dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280
  clk: qcom: Add lpass clock controller driver for SC7280
  dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280
  clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180
  clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc
  clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc
  clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents
  clk: qcom: gcc-msm8994: Add proper msm8992 support
  clk: qcom: gcc-msm8994: Add modem reset
  clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE
  clk: qcom: gcc-msm8994: Add missing clocks
  clk: qcom: gcc-msm8994: Add missing NoC clocks
  clk: qcom: gcc-msm8994: Fix up SPI QUP clocks
  ...

* clk-mtk: (28 commits)
  clk: mediatek: Export clk_ops structures to modules
  clk: mediatek: support COMMON_CLK_MT6779 module build
  clk: mediatek: support COMMON_CLK_MEDIATEK module build
  clk: composite: export clk_register_composite
  clk: mediatek: Add MT8195 apusys clock support
  clk: mediatek: Add MT8195 imp i2c wrapper clock support
  clk: mediatek: Add MT8195 wpesys clock support
  clk: mediatek: Add MT8195 vppsys1 clock support
  clk: mediatek: Add MT8195 vppsys0 clock support
  clk: mediatek: Add MT8195 vencsys clock support
  clk: mediatek: Add MT8195 vdosys1 clock support
  clk: mediatek: Add MT8195 vdosys0 clock support
  clk: mediatek: Add MT8195 vdecsys clock support
  clk: mediatek: Add MT8195 scp adsp clock support
  clk: mediatek: Add MT8195 mfgcfg clock support
  clk: mediatek: Add MT8195 ipesys clock support
  clk: mediatek: Add MT8195 imgsys clock support
  clk: mediatek: Add MT8195 ccusys clock support
  clk: mediatek: Add MT8195 camsys clock support
  clk: mediatek: Add MT8195 infrastructure clock support
  ...

* clk-versatile:
  clk: versatile: hide clock drivers from non-ARM users
  clk: versatile: Rename ICST to CLK_ICST
  clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address
  dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address

* clk-doc:
  dt-bindings: clk: fixed-mmio-clock: Convert to YAML

clk: at91: sama7g5: set low limit for mck0 at 32KHz

MCK0 could go as low as 32KHz. Set this limit.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: sama7g5: remove prescaler part of master clock

On SAMA7G5 the prescaler part of master clock has been implemented as a
changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
been discovered that in some conditions the PMC_SR.MCKRDY is not rising
but the rate it provides it's stable. The workaround is to add a timeout
when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
will be removed from Linux clock tree as all the frequencies for CPU could
be obtained from PLL and also there will be less overhead when changing
frequency via DVFS.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-master: add notifier for divider

SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
parent with cpuck as seen in the following clock tree:

                       +----------> cpuck
                       |
FRAC PLL ---> DIV PLL -+-> DIV ---> mck0

mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
while changing FRAC PLL or DIV PLL the commit implements a notifier for
mck0 which applies a safe divider to register (maximum value of the divider
which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
events.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-sam9x60-pll: add notifier for div part of PLL

SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
one fractional part and one divider. On SAMA7G5 the CPU PLL could be
changed at run-time to implement DVFS. The hardware clock tree on
SAMA7G5 for CPU PLL is as follows:

                       +---- div1 ----------------> cpuck
                       |
FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0

The div1 block is not implemented in Linux; on prescaler block it has
been discovered a bug on some scenarios and will be removed from Linux
in next commits. Thus, the final clock tree that will be used in Linux
will be as follows:

                       +-----------> cpuck
                       |
FRAC PLL ---> DIV PLL -+-> div0 ---> mck0

It has been proposed in [1] to not introduce a new CPUFreq driver but
to overload the proper clock drivers with proper operation such that
cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
clock notifiers which applies safe dividers before FRAC PLL is changed.
The current commit treats only the DIV PLL by adding a notifier that
sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
provided by initialization clock code (sama7g5.c). The div0 is treated
in next commits (to keep the changes as clean as possible).

[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-master: fix prescaler logic

When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.

Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-master: mask mckr against layout->mask

Mask values read/written from/to MCKR against layout->mask as this
mask may be different b/w PMC versions.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-master: check if div or pres is zero

Check if div or pres is zero before using it as argument for ffs().
In case div is zero ffs() will return 0 and thus substracting from
zero will lead to invalid values to be setup in registers.

Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5")
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL

Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
computed in sam9x60_frac_pll_recalc_rate() and the one computed in
sam9x60_frac_pll_compute_mul_frac().

Fixes: 43b1bb4a9b3e1 ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: pmc: add sama7g5 to the list of available pmcs

Add SAMA7G5 to the list of available PMCs such that the suspend/resume
code for clocks to be used on backup mode.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-master: improve readability by using local variables

Improve readability in clk_sama7g5_master_set() by using local
variables.

Suggested-by: Nicolas Ferre <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: clk-master: add register definition for sama7g5's master clock

SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
register at offset 0x30 (relative to PMC). In the last/first phase of
suspend/resume procedure (which is architecture specific) the parent
of master clocks are changed (via assembly code) for more power saving
(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
and at91_mckx_ps_restore). Thus the macros corresponding to register
at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
master clock") introduced the proper macros but didn't adapted the
clk-master.c as well. Thus, this commit adapt the clk-master.c to use
the macros introduced in commit ec03f18cc222 ("clk: at91: add register
definition for sama7g5's master clock").

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: sama7g5: add securam's peripheral clock

Add SECURAM's peripheral clock.

Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: pmc: execute suspend/resume only for backup mode

Before going to backup mode architecture specific PM code sets the first
word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()).
Thus take this into account when suspending/resuming clocks. This will
avoid executing unnecessary instructions when suspending to non backup
modes.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: at91: re-factor clocks suspend/resume

SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
most of the SoC's components are powered off (including PMC). Resuming
from this mode is done with the help of bootloader. Peripherals are not
aware of the power saving mode thus most of them are disabling clocks in
proper suspend API and re-enable them in resume API without taking into
account the previously setup rate. Moreover some of the peripherals are
acting as wakeup sources and are not disabling the clocks in this
scenario, when suspending. Since backup mode cuts the power for
peripherals, in resume part these clocks needs to be re-configured.

The initial PMC suspend/resume code was designed only for SAMA5D2's PMC
(as it was the only one supporting backup mode). SAMA7G supports also
backup mode and its PMC is different (few new functionalities, different
registers offsets, different offsets in registers for each
functionalities). To address both SAMA5D2 and SAMA7G5 PMC add
.save_context()/.resume_context() support to each clocks driver and call
this from PMC driver.

Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

Merge tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L
 - Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U
 - Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N

* tag 'renesas-clk-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779[56]x: Add MLP clocks
  clk: renesas: r9a07g044: Add SDHI clock and reset entries
  clk: renesas: rzg2l: Add SDHI clk mux support
  clk: renesas: r8a779a0: Add RPC support
  clk: renesas: cpg-lib: Move RPC clock registration to the library
  clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller

clk: renesas: r8a779[56]x: Add MLP clocks

Add clocks for MLP modules on Renesas R-Car H3 and M3-W/N SoCs.

Signed-off-by: Andrey Gusakov <[email protected]>
Signed-off-by: Nikita Yushchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: versatile: hide clock drivers from non-ARM users

Commit 419b3ab6987f ("clk: versatile: remove dependency on ARCH_*")
made the whole menu of ARM reference clock drivers visible on all
architectures. I can't see how this is an improvement for non-ARM
users. Unless build-testing, there is no point on presenting
ARM-only clock drivers on other architectures.

Signed-off-by: Jean Delvare <[email protected]>
Cc: Peter Collingbourne <[email protected]>
Cc: Lee Jones <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/20210901180953.5bd2a994@endymion
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: versatile: Rename ICST to CLK_ICST

For consistency, prefix the ICST config option with CLK as all other
clock source drivers have.

Signed-off-by: Jean Delvare <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Link: https://lore.kernel.org/r/20210901180833.4558932d@endymion
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gdsc: enable optional power domain support

On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Currently we use a regulator to enable this domain on demand,
however this has some consequences, as genpd code is not reentrant.

Make gdsc code also use pm_runtime calls to ensure that registers are
accessible during the gdsc_enable/gdsc_disable operations.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: videocc-sm8250: use runtime PM for the clock controller

On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Use runtime PM calls to make sure that required power domain is
powered on while we access clock controller's registers.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: dispcc-sm8250: use runtime PM for the clock controller

On sm8250 dispcc and videocc registers are powered up by the MMCX power
domain. Use runtime PM calls to make sure that required power domain is
powered on while we access clock controller's registers.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clock: qcom,videocc: add mmcx power domain

On sm8250 videocc requires MMCX power domain to be powered up before
clock controller's registers become available. For now sm8250 was using
external regulator driven by the power domain to describe this
relationship. Switch into specifying power-domain and required opp-state
directly.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain

On sm8250 dispcc requires MMCX power domain to be powered up before
clock controller's registers become available. For now sm8250 was using
external regulator driven by the power domain to describe this
relationship. Switch into specifying power-domain and required opp-state
directly.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-sc7280: Drop unused array

After commit 3165d1e3c737 ("clk: qcom: gcc: Remove CPUSS clocks control
for SC7280") this array is unused. Remove it.

Reported-by: kernel test robot <[email protected]>
Cc: Taniya Das <[email protected]>
Fixes: 3165d1e3c737 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: camcc: Add camera clock controller driver for SC7280

Add support for the camera clock controller found on SC7280 based
devices.
This would allow camera drivers to probe and control their clocks.

Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Make some VCOs unsigned long]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280

The camera clock controller clock provider have a bunch of generic
properties that are needed in a device tree. Add the CAMCC clock IDs for
camera client to request for the clocks.

Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Add lpass clock controller driver for SC7280

Add support for the lpass clock controller found on SC7280 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.

Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280

The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Add the LPASS clock IDs for
LPASS PIL client to request for the clocks.

Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180

Fix the order of the Kconfig symbol for SC_LPASS_CORECC_7180.

Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc

As shown downstream[1], this GDSC supports HW trigger mode and
we're supposed to enable it in order to ensure correct operation.

[1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm630.dtsi#L2181

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc

As also shown on downstream dts[1], for a correct operation of the
Venus block, we have to retain MEM/PERIPH when halting the video_core,
video_axi and video_subcore0 branches: add these CXCs to the main
Venus GDSC.

[1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi#L80

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents

Don't rely on the programmer to enter the name of array elements, since the
computer can compute it with much less chance of making a mistake.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Add proper msm8992 support

MSM8992 is a cut-down version of MSM8994, featuring
largely the same hardware.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Add modem reset

This will be required to support the modem.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE

This GDSC is not present on msm8994.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Add missing clocks

This should be the last "add missing clocks" commit, as to
my knowledge there are no more clocks registered within gcc.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Add missing NoC clocks

Add necessary NoC clocks to provide frequency sources for
relevant branch clocks.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Fix up SPI QUP clocks

Fix up SPI QUP freq tables to account for the fact
that not every QUP can run at the same set of frequencies.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: gcc-msm8994: Modernize the driver

Switch to the newer-style parent_data and remove the hardcoded
xo clock.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver

Add documentation for the MSM8994 GCC driver. While at it, retire its
compatible from the old, everyone-get-in-here file.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: smd-rpm: Add QCM2290 RPM clock support

Add support for RPM-managed clocks on the QCM2290 platform.

Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clk: qcom,rpmcc: Document QCM2290 compatible

Add compatible for the RPM Clock Controller on the QCM2290 SoC.

Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: smd-rpm: Add .recalc_rate hook for clk_smd_rpm_branch_ops

As there is a `rate` field in clk_smd_rpm, clk_smd_rpm_recalc_rate() can
be used by branch clocks to report rate as well, rather than assuming
the rate is always same as parent clock.  This assumption doesn't hold
on platforms like QCM2290, where xo_board is 38.4MHz while bi_tcxo is
19.2MHz.

To get this work, XO buffered clocks need the following updates.

- Assign a correct rate rather than the fake one which is being used to
  generate binary value for clk_smd_rpm_req interface.

- Explicitly handle the clk_smd_rpm_req interface value for XO buffered
  clocks (.rpm_res_type being QCOM_SMD_RPM_CLK_BUF_A).

Suggested-by: Bjorn Andersson <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Bjorn Andersson <[email protected]>
[[email protected]: Do cpu_to_le32() again to keep sparse happy]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Add Global Clock Controller driver for QCM2290

Add Global Clock Controller (GCC) driver for QCM2290.  This is a porting
of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top.

Because the alpha_pll on the platform has a different register
layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the
driver.

Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rob Herring <[email protected]>
[[email protected]: Drop duplicate includes, clk.h include, module alias]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clk: qcom: Add QCM2290 Global Clock Controller bindings

It adds device tree bindings for QCM2290 Global Clock Controller.

Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: renesas: r9a07g044: Add SDHI clock and reset entries

Add SDHI{0,1} mux, clock and reset entries to CPG driver.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: rzg2l: Add SDHI clk mux support

Add SDHI clk mux support to select SDHI clock from different clock
sources.

As per HW manual, direct clock switching from 533MHz to 400MHz and
vice versa is not recommended. So added support for handling this
in mux.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: r8a779a0: Add RPC support

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: cpg-lib: Move RPC clock registration to the library

We want to reuse this code for V3U soon. Because its RPCCKCR register is
at a different offset, the moved functions do not use the base register
as an argument anymore but the RPCCKCR register itself. Verified that an
Eagle board with R-Car V3M still works.

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller

Add clock and reset entries for SPI Multi I/O Bus Controller.

Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: at91: check pmc node status before registering syscore ops

Currently, at91 pmc driver always register the syscore_ops whatever
the status of the pmc node that has been found. When set as secure
and disabled, the pmc should not be accessed or this will generate
abort exceptions.
To avoid this, add a check on node availability before registering
the syscore operations.

Signed-off-by: Clément Léger <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Fixes: b3b02eac33ed ("clk: at91: Add sama5d2 suspend/resume")
Signed-off-by: Stephen Boyd <[email protected]>

Merge tag 'renesas-clk-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
 - Add Ethernet clocks on Renesas RZ/G2L

* tag 'renesas-clk-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779a0: Add Z0 and Z1 clock support
  clk: renesas: r9a07g044: Add GbEthernet clock/reset
  clk: renesas: rzg2l: Add support to handle coupled clocks
  clk: renesas: r9a07g044: Add ethernet clock sources
  clk: renesas: rzg2l: Add support to handle MUX clocks
  clk: renesas: r8a779a0: Add TPU clock
  clk: renesas: rzg2l: Fix clk status function
  clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical

clk: qcom: gcc: Remove CPUSS clocks control for SC7280

The CPUSS clocks are kept always ON and at a fixed frequency of 100MHZ
from the bootloader and no longer required to be controlled from HLOS.

Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: qcom: Remove redundant .owner

Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Signed-off-by: Kai Song <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

Merge tag 'v5.16-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - Move to use module_platform_probe
 - Enable usage of Coresight-related clocks on rk3399

* tag 'v5.16-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: use module_platform_driver_probe
  clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}
  clk: rockchip: rk3399: make CPU clocks critical

clk: renesas: r8a779a0: Add Z0 and Z1 clock support

Add support for the Z0 and Z1 (Cortex-A76 Sub-system 0 and 1) clocks,
based on the existing support for Z clocks on R-Car Gen3.

As the offsets of the CPG_FRQCRB and CPG_FRQCRC registers on R-Car V3U
differ from the offsets on other R-Car Gen3 SoCs, we cannot use the
existing R-Car Gen3 support as-is.  For now, just make a copy, and
change the register offsets.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/2112e3bc870580c623bdecfeff8c74739699c610.1625219713.git.geert+renesas@glider.be

clk: renesas: r9a07g044: Add GbEthernet clock/reset

Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: rzg2l: Add support to handle coupled clocks

The AXI and CHI clocks use the same register bit for controlling clock
output. Add a new clock type for coupled clocks, which sets the
CPG_CLKON_ETH.CLK[01]_ON bit when at least one clock is enabled, and
clears the bit only when both clocks are disabled.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: r9a07g044: Add ethernet clock sources

Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match
with the register description as mentioned in RZ/G2L HW manual (Rev.1.00).

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: rzg2l: Add support to handle MUX clocks

Add support to handle mux clocks in order to select a clock source
from multiple sources.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: r8a779a0: Add TPU clock

Signed-off-by: Wolfram Sang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: rzg2l: Fix clk status function

As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
0 means clock is not supplied and 1 means clock is supplied.
This patch fixes the issue by removing the inverted logic.

Fixing the above, triggered following 2 issues

1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
   Fixed this issue by adding these clocks as critical clocks.

2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
   So will provide a fix in the DMA driver to turn on DMA_PCLK.

Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical

Add IA55_CLK and DMAC_ACLK as critical clocks.

Previously it worked ok, because of a bug in clock status function
and the following patch in this series fixes the original bug.

Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions")
Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets")
Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

clk: rockchip: use module_platform_driver_probe

Replace builtin_platform_driver_probe with module_platform_driver_probe
because that rk3399 and rk3568 can be built as kernel modules.

Fixes: 70d839e2761d ("clk: rockchip: rk3399: Support module build")
Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568")
Cc: Heiko Stuebner <[email protected]>
Cc: Stephen Boyd <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Miles Chen <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}

We have DT IDs for PCLK_COREDBG_L and PCLK_COREDBG_B, but we don't
actually expose them.

Note that this requires the previous patch (making "armclkl" and
"armclkb" into "critical" clocks) to prevent these clocks from taking
down the CPU.

Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Brian Norris <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Link: https://lore.kernel.org/r/20210908111337.v2.2.If29cd838efbcee4450a62b8d84a99b23c86e0a3f@changeid
Signed-off-by: Heiko Stuebner <[email protected]>

clk: rockchip: rk3399: make CPU clocks critical

The CPU clocks don't currently have any owner (e.g., cpufreq-dt doesn't
enable() them -- and even if it did, it's not early enough compared to
other consumers -- nor does arch/arm64/kernel/smp.c), and instead are
simply assumed to be "on" all the time.

They are also parents of a few other clocks which haven't been
previously exposed for other devices to consume. If we want to expose
those clocks, then the common clock framework may eventually choose to
disable their parents (including the CPU PLLs) -- which is no fun for
anyone.

Thus, mark the CPU clocks as critical, to prevent them from being
disabled implicitly.

Signed-off-by: Brian Norris <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Link: https://lore.kernel.org/r/20210908111337.v2.1.I006bb36063555079b1a88f01d20e38d7e4705ae0@changeid
Signed-off-by: Heiko Stuebner <[email protected]>

clk: mediatek: Export clk_ops structures to modules

modpost complains once these drivers become modules.

 ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined!

Let's just export them.

Cc: Hanks Chen <[email protected]>
Cc: Wendell Lin <[email protected]>
Cc: Lee Jones <[email protected]>
Cc: Miles Chen <[email protected]>
Fixes: 32b028fb1d09 ("clk: mediatek: support COMMON_CLK_MEDIATEK module build")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling paths

If we exit the for_each_of_cpu_node loop early, the reference on the
current node must be decremented, otherwise there is a leak.

Fixes: f756e362d938 ("clk: mvebu: add CPU clock driver for Armada 7K/8K")
Signed-off-by: Christophe JAILLET <[email protected]>
Link: https://lore.kernel.org/r/545df946044fc1fc05a4217cdf0054be7a79e49e.1619161112.git.christophe.jaillet@wanadoo.fr
Reviewed-by: Dan Carpenter <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: support COMMON_CLK_MT6779 module build

To support COMMON_CLK_MT6779* module build,
add MODULE_LICENSE and export necessary symbols.

Cc: Stephen Boyd <[email protected]>
Cc: Hanks Chen <[email protected]>
Cc: Wendell Lin <[email protected]>
Cc: Lee Jones <[email protected]>
Signed-off-by: Miles Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: support COMMON_CLK_MEDIATEK module build

To support COMMON_CLK_MEDIATEK module build,
add MODULE_LICENSE and export necessary symbols.

Cc: Stephen Boyd <[email protected]>
Cc: Hanks Chen <[email protected]>
Cc: Wendell Lin <[email protected]>
Cc: Lee Jones <[email protected]>
Signed-off-by: Miles Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: composite: export clk_register_composite

To support module build of mediatek clk drivers,
it is necessary to export clk_register_composite.

Cc: Stephen Boyd <[email protected]>
Cc: Hanks Chen <[email protected]>
Cc: Wendell Lin <[email protected]>
Cc: Lee Jones <[email protected]>
Signed-off-by: Miles Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clk: fixed-mmio-clock: Convert to YAML

Convert the binding documentatoin for fixed-mmio-clock to YAML.

Signed-off-by: Marek Behún <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address

The ICST binding now also supports 'reg' in addition to 'vco-offset' for
the VCO register address. Add support to the driver to get the VCO
address from 'reg'.

Cc: Linus Walleij <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address

'reg' is the standard property for defining register banks/addresses. Add
it to use for the VCO register address and deprecate 'vco-offset'. This
will also allow for using standard node names with unit-addresses.

Cc: Linus Walleij <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Michael Turquette <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 apusys clock support

Add MT8195 apusys clock controller which provides PLLs
in AI processor Unit.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 imp i2c wrapper clock support

Add MT8195 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 wpesys clock support

Add MT8195 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 vppsys1 clock support

Add MT8195 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 vppsys0 clock support

Add MT8195 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 vencsys clock support

Add MT8195 vencsys clock controllers which provide clock gate
control for video encoder.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 vdosys1 clock support

Add MT8195 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 vdosys0 clock support

Add MT8195 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 vdecsys clock support

Add MT8195 vdec clock controllers which provide clock gate
control for video decoder.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 scp adsp clock support

Add MT8195 scp adsp clock controller which provides clock gate
control for Audio DSP.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 mfgcfg clock support

Add MT8195 mfg clock controller which provides clock gate
control for GPU.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 ipesys clock support

Add MT8195 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 imgsys clock support

Add MT8195 imgsys clock controllers which provide clock gate
control for image IP blocks.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 ccusys clock support

Add MT8195 ccusys clock controller which provides clock gate
control in Camera Computing Unit.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 camsys clock support

Add MT8195 camsys clock controllers which provide clock gate
control for camera IP blocks.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 infrastructure clock support

Add MT8195 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 peripheral clock support

Add MT8195 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 topckgen clock support

Add MT8195 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.

Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add MT8195 apmixedsys clock support

Add MT8195 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Fix resource leak in mtk_clk_simple_probe

Release clock data when clock driver probe fail to fix
possible resource leak.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add API for clock resource recycle

In order to avoid resource leak when fail clock registration appears,
so adds the common interface to handle it.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Fix corner case of tuner_en_reg

On MT8195, tuner_en_reg is moved to register offest 0x0.
If we only judge by tuner_en_reg, it may lead to wrong address.
Add tuner_en_bit to the check condition. And it has been confirmed,
on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
clock square control.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

clk: mediatek: Add dt-bindings of MT8195 clocks

Add MT8195 clock dt-bindings, includes topckgen, apmixedsys,
infracfg_ao, pericfg_ao and subsystem clocks.

Signed-off-by: Chun-Jie Chen <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock

This patch adds the new binding documentation for system clock
and functional clock on Mediatek MT8195.

Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>