Ville Syrjälä [Wed, 4 May 2022 15:04:34 +0000 (18:04 +0300)]
drm/i915/bios: Get access to the tail end of the LFP data block
We need to start parsing stuff from the tail end of the LFP data block.
This is made awkward by the fact that the fp_timing table has variable
size. So we must use a bit more finesse to get the tail end, and to
make sure we allocate enough memory for it to make sure our struct
representation fits.
v2: Rebase due to the preallocation of BDB blocks
v3: Rebase due to min_size WARN relocation
v4: Document BDB_LVDS_LFP_DATA vs. BDB_LVDS_LFP_DATA_PTRS order (Jani)
Ville Syrjälä [Wed, 4 May 2022 15:04:33 +0000 (18:04 +0300)]
drm/i915/bios: Generate LFP data table pointers if the VBT lacks them
Modern VBTs no longer contain the LFP data table pointers
block (41). We are expecting to have one in order to be able
to parse the LFP data block (42), so let's make one up.
Since the fp_timing table has variable size we must somehow
determine its size. Rather than just hardcode it we look for
the terminator bytes (0xffff) to figure out where each table
entry starts. dvo_timing, panel_pnp_id, and panel_name are
expected to have fixed size.
This has been observed on various machines, eg. TGL with BDB
version 240, CML with BDB version 231, etc. The most recent
VBT I've observed that still had block 41 had BDB version
228. So presumably the cutoff (if an exact cutoff even exists)
is somewhere around BDB version 229-231.
v2: kfree the thing we allocated, not the thing+3 bytes
v3: Do the debugprint only if we found the LFP data block
v4: Fix t0 null check (Jani)
Ville Syrjälä [Fri, 18 Feb 2022 10:03:59 +0000 (12:03 +0200)]
drm/i915: Use drm_mode_init() for on-stack modes
Initialize on-stack modes with drm_mode_init() to guarantee
no stack garbage in the list head, or that we aren't copying
over another mode's list head.
Based on the following cocci script, with manual fixups:
@decl@
identifier M;
expression E;
@@
- struct drm_display_mode M = E;
+ struct drm_display_mode M;
@@
identifier decl.M;
expression decl.E;
statement S, S1;
@@
struct drm_display_mode M;
... when != S
+ drm_mode_init(&M, &E);
+
S1
Jani Nikula [Fri, 29 Apr 2022 14:21:40 +0000 (17:21 +0300)]
drm/i915: move tons of power well initializers to rodata
Using compound literals for initialization can be tricky. Lacking a
const qualifier, they won't end up in rodata, which is probably not
expected or intended. Add const to move a whopping 136 initializers to
rodata.
Jani Nikula [Fri, 29 Apr 2022 09:58:40 +0000 (12:58 +0300)]
Merge tag 'gvt-next-2022-04-29' of https://github.com/intel/gvt-linux into drm-intel-next
gvt-next-2022-04-29
Introduce fixes from previous pull.
- Fix a compiling warning of non-static funtion only having one caller.
- Fix a potential NULL pointer reference in the code re-factor.
- Fix a compiling error when CONFIG_DRM_I915_DEBUG_RUNTIME_PM=n
Matt Roper [Mon, 25 Apr 2022 21:12:50 +0000 (14:12 -0700)]
drm/i915: Add first set of DG2 PCI IDs
The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now (although they'll continue to require force_probe until the
usual requirements are met).
The remaining DG2 IDs for add-in cards will come in a future patch once
some additional required functionality has fully landed.
Imre Deak [Fri, 8 Apr 2022 22:46:29 +0000 (01:46 +0300)]
drm/i915/dp: Add workaround for spurious AUX timeouts/hotplugs on LTTPR links
To avoid AUX timeouts and subsequent spurious hotplug interrupts, make
sure that the first DPCD access during detection is a read from an LTTPR
register.
Some ADLP DP link configuration at least with multiple LTTPRs expects
the first DPCD access during the LTTPR/DPCD detection after hotplug to
be a read from the LTTPR range starting with
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV. The side effect of
this read is to put each LTTPR into the LTTPR transparent or LTTPR
non-transparent mode.
The lack of the above read may leave some of the LTTPRs in non-LTTPR
mode, while other LTTPRs in LTTPR transparent or LTTPR non-transparent
mode (for instance LTTPRs after system suspend/resume that kept their
mode from before suspend). Due to the different AUX timeouts the
different modes imply, the DPCD access from a non-LTTPR range will
timeout and lead to an LTTPR generated hotplug towards the source (which
the LTTPR firmware uses to account for buggy TypeC adapters with a long
wake-up delay).
SYSCROS: 72939
v2: Keep DPCD read-out working on non-LTTPR platforms.
v3: Summarize what and why the patch does at the beginning of the commit
log. (Jani)
Ville Syrjälä [Fri, 25 Mar 2022 12:32:01 +0000 (14:32 +0200)]
drm/i915: Add crtc .crtc_get_shared_dpll()
Start splitting the .compute_crtc_clock() into two parts; one
part does the computation, the second part does the shared dpll
assignment. I want to move the actual computation part much earlier
into the compute_config() phase.
Ville Syrjälä [Fri, 25 Mar 2022 12:31:58 +0000 (14:31 +0200)]
drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
All .crtc_compute_clock() implementations do the same memset() to
clear the dpll_hw_state (since we preserve it across
intel_crtc_prepare_cleared_state()). Move the memset() to the common
wrapper.
Ville Syrjälä [Fri, 25 Mar 2022 12:31:57 +0000 (14:31 +0200)]
drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
Move some checks into intel_dpll_crtc_compute_clock() from the
caller. Avoids the caller from having to worry about all this
crap.
We'll also reorder the hw.enable vs. shared_dpll checks since
it makes sense to sanity check that we've cleared out the
old shared_dpll even if the pipe is getting disabled.
Ville Syrjälä [Wed, 13 Apr 2022 15:28:52 +0000 (18:28 +0300)]
drm/i915/fbc: s/false/0/
intel_fbc_check_plane() is supposed to an int, not a boolean.
So replace the bogus 'return false's with the correct 'return 0's.
These were accidental copy-paste mistakes when the code got moved
into intel_fbc_check_plane() from somewhere else tht did return
a boolean.
Ville Syrjälä [Wed, 13 Apr 2022 15:28:51 +0000 (18:28 +0300)]
drm/i915/fbc: Consult hw.crtc instead of uapi.crtc
plane_state->uapi.crtc is not what we want to be looking at.
If bigjoiner is used hw.crtc is what tells us what crtc the plane
is supposedly using.
Not an actual problem on current hardware as the only FBC capable
pipe (A) can't be a bigjoiner slave and thus uapi.crtc==hw.crtc
always here. But when we get more FBC instances this will become
actually important.
Dave Airlie [Thu, 21 Apr 2022 20:43:52 +0000 (06:43 +1000)]
Merge tag 'drm-misc-next-2022-04-21' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.19-rc1
UAPI Changes:
Cross-subsystem Changes:
- of: Create a platform_device for offb
Core Changes:
- edid: block read refactoring
- ttm: Add common debugfs code for resource managers
Driver Changes:
- bridges:
- adv7611: Enable DRM_BRIDGE_OP_HPD if there's an interrupt
- anx7625: Fill ELD if no monitor is connected
- dw_hdmi: Add General Parallel Audio support
- icn6211: Add data-lanes DT property
- new driver: Lontium LT9211
- nouveau: make some structures static
- tidss: Reset DISPC on startup
- solomon: SPI Support and DT bindings improvements
drm/i915: Check EDID for HDR static metadata when choosing blc
We have now seen panel (XMG Core 15 e21 laptop) advertizing support
for Intel proprietary eDP backlight control via DPCD registers, but
actually working only with legacy pwm control.
This patch adds panel EDID check for possible HDR static metadata and
Intel proprietary eDP backlight control is used only if that exists.
Missing HDR static metadata is ignored if user specifically asks for
Intel proprietary eDP backlight control via enable_dpcd_backlight
parameter.
v2 :
- Ignore missing HDR static metadata if Intel proprietary eDP
backlight control is forced via i915.enable_dpcd_backlight
- Printout info message if panel is missing HDR static metadata and
support for Intel proprietary eDP backlight control is detected
Jason Gunthorpe [Mon, 11 Apr 2022 14:14:02 +0000 (16:14 +0200)]
vfio/mdev: Use the driver core to create the 'remove' file
The device creator is supposed to use the dev.groups value to add sysfs
files before device_add is called, not call sysfs_create_files() after
device_add() returns. This creates a race with uevent delivery where the
extra attribute will not be visible.
This was being done because the groups had been co-opted by the mdev
driver, now that prior patches have moved the driver's groups to the
struct device_driver the dev.group is properly free for use here.
Jason Gunthorpe [Mon, 11 Apr 2022 14:14:00 +0000 (16:14 +0200)]
vfio/mdev: Remove mdev_parent_ops dev_attr_groups
This is only used by one sample to print a fixed string that is pointless.
In general, having a device driver attach sysfs attributes to the parent
is horrific. This should never happen, and always leads to some kind of
liftime bug as it become very difficult for the sysfs attribute to go back
to any data owned by the device driver.
Remove the general mechanism to create this abuse.
Jason Gunthorpe [Mon, 11 Apr 2022 14:13:59 +0000 (16:13 +0200)]
vfio/mdev: Remove vfio_mdev.c
Now that all mdev drivers directly create their own mdev_device driver and
directly register with the vfio core's vfio_device_ops this is all dead
code.
Delete vfio_mdev.c and the mdev_parent_ops members that are connected to
it.
drm/i915/gvt: convert to use vfio_register_emulated_iommu_dev
This is straightforward conversion, the intel_vgpu already has a pointer
to the vfio_dev, which can be replaced with the embedded structure and
we can replace all the mdev_get_drvdata() with a simple container_of().
Instead of having an option to build the gvt code into the main i915
module, just move it into the kvmgt.ko module. This only requires
a new struct with three entries that the KVMGT modules needs to register
with the main i915 module, and a proper list of GVT-enabled devices
instead of global device pointer.
Zhi Wang [Thu, 7 Apr 2022 07:19:44 +0000 (03:19 -0400)]
i915/gvt: Save the initial HW state snapshot in i915
Save the initial HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.
v6:
- Remove the reference of intel_gvt_device_info.(Christoph)
- Refine the save_mmio() function. (Christoph)
Zhi Wang [Thu, 7 Apr 2022 07:19:43 +0000 (03:19 -0400)]
i915/gvt: Separate the MMIO tracking table from GVT-g
To support the new mdev interfaces and the re-factor patches from
Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
MMIO tracking table needs to be separated from GVT-g.
v9:
- Fix a problem might cause kernel panic.
- Remove the redaundant definitation of intel_get_device_type(). (Jani)
- Sort the list of header reference in intel_gvt_mmio.c (Jani)
- Include minimum header insted in intel_gvt_mmio.c (Jani)
v8:
- Use SPDX header in the intel_gvt_mmio_table.c
- Reference the gvt.h with path. (Jani)
- Add a missing fix on mmio emulation path during the debug.
- Fix a building problem on refreshed gvt-staging branch. (Christoph)
v7:
- Keep the marcos of device generation in GVT-g. (Christoph, Jani)
v6:
- Move the mmio_table.c into i915. (Christoph)
- Keep init_device_info and related structures in GVT-g. (Christoph)
- Refine the callbacks of the iterator. (Christoph)
- Move the flags of MMIO register defination to GVT-g. (Chrsitoph)
- Move the mmio block handling to GVT-g.
v5:
- Re-design the mmio table framework. (Christoph)
v4:
- Fix the errors of patch checking scripts.
v3:
- Fix the errors when CONFIG_DRM_I915_WERROR is turned on. (Jani)
v2:
- Implement a mmio table instead of generating it by marco in i915. (Jani)
drm/radeon: Use TTM builtin resource manager debugfs code
Switch to using the TTM resource manager debugfs helpers. The
functionality is largely the same.
The TTM resource managers need to stay valid for as long as the
drm debugfs_root is valid.
drm/qxl: Use TTM builtin resource manager debugfs code
Switch to using the TTM resource manager debugfs helpers. The
functionality is largely the same.
The TTM resource managers need to stay valid for as long as the
drm debugfs_root is valid.
drm/vmwgfx: Add debugfs entries for various ttm resource managers
Use the newly added TTM's ability to automatically create debugfs entries
for specified placements. This creates debugfs files that can be read to
get information about various TTM resource managers which are used by
vmwgfx.
drm/ttm: Add common debugfs code for resource managers
Drivers duplicate the code required to add debugfs entries for various
ttm resource managers. To fix it add common TTM resource manager debugfs
code that each driver can reuse.
Specific resource managers can overwrite
ttm_resource_manager_func::debug to get more information from those
debugfs entries.
Imre Deak [Thu, 14 Apr 2022 21:06:57 +0000 (00:06 +0300)]
drm/i915: Remove the XELPD specific AUX and DDI power domains
The spec calls the XELPD_D/E ports just D/E, the platform prefix in the
domain names was only needed by the port->domain mapping relying on
matching enum values for the whole port/domain range (and the
corresponding aliasing between the platform specific domain enums).
Since a previous patch we can define the port->domain mapping explicitly
so do this by reusing the already existing D/E power domain names.
Imre Deak [Thu, 14 Apr 2022 21:06:56 +0000 (00:06 +0300)]
drm/i915: Remove duplicate DDI/AUX power domain mappings
The DDI and AUX domain -> power well mappings are identical for a few
platforms/power well instances, reuse the mappings of earlier platforms
for these removing the duplicate mapping of new platforms.
Imre Deak [Thu, 14 Apr 2022 21:06:54 +0000 (00:06 +0300)]
drm/i915: Remove the aliasing of power domain enum values
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1. Make this clearer by removing the aliasing which is
possible after a previous patch converting the mask to a bitmap.
Imre Deak [Thu, 14 Apr 2022 21:06:53 +0000 (00:06 +0300)]
drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the corresponding port is TC1. To make it clear what
port/domain the code refers to add a mapping between them which matches
the bspec terms on different display versions.
This also allows for removing the aliasing in enum values in a follow-up
patch.
v2: Add the functions to intel_display_power.c, use
intel_display_power_ prefix.
Imre Deak [Thu, 14 Apr 2022 21:06:52 +0000 (00:06 +0300)]
drm/i915: Sanitize the ADL-S power well definition
Instead of the skip_mask special casing of the ADL-S power well
descriptors, add a power well descriptor list for ADL-S as well reusing
the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have
TypeC PHYs, so a better way would be having ADL-S specific AUX
descriptors, but I left changing this for a follow-up.
This changes the ordering of the AUX and TC-cold vs. PW_4/5 power wells
on TGL and ADL-S, but this shouldn't make a difference (PW_4/5 don't
depend on the AUX/TC-cold power wells).
Imre Deak [Thu, 14 Apr 2022 21:06:51 +0000 (00:06 +0300)]
drm/i915: Simplify the DG1 power well descriptors
Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.
This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).
Imre Deak [Thu, 14 Apr 2022 21:06:50 +0000 (00:06 +0300)]
drm/i915: Allow platforms to share power well descriptors
Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.
This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove the ADL-S skip_mask special casing.
Imre Deak [Thu, 14 Apr 2022 21:06:49 +0000 (00:06 +0300)]
drm/i915: Simplify power well definitions by adding power well instances
All the port specific AUX/DDI_IO power wells share the same power well
ops struct and flags, so we can save some space and simplify the
definition of these by listing for all such power wells only the params
specific to them (name, domains, power well register index, id). Move
these params to a new i915_power_well_instance struct and convert the
per-platform power well definitions accordingly.
For all power well instance the name and power domain list params must
be specified, while the register index and id are optional, add the
I915_PW() macro that both simplifies the definitions and ensures that
the required params are set.
Imre Deak [Thu, 14 Apr 2022 21:06:48 +0000 (00:06 +0300)]
drm/i915: Convert the u64 power well domains mask to a bitmap
To remove the aliasing of the power domain enum values in a follow-up
patch in this patchset (requiring a bigger mask) and allow for defining
additional power domains in the future (at least some upcoming TypeC
changes requires this) convert the u64 i915_power_well_desc::domains
mask to a bitmap.
For simplicity I changed the for_each_power_domain_well() macros to
accept one domain only instead of a mask, as there isn't any current
user passing multiple domains.
v2: Don't add a typedef for the bitmap struct. (Jani)
Imre Deak [Thu, 14 Apr 2022 21:06:47 +0000 (00:06 +0300)]
drm/i915: Convert the power well descriptor domain mask to an array of domains
The next patch converts the i915_power_well_desc::domain mask from a u64
mask to a bitmap. I didn't find a reasonably simple way to initialize
bitmaps statically, so prepare for the next patch here by converting the
masks to an array of domain enums and initing the masks from these
arrays during module loading.
v2: Clarify list vs. array in the commit message. (Jani)
Imre Deak [Thu, 14 Apr 2022 21:06:43 +0000 (00:06 +0300)]
drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.
This change also lets simplifying the definiton of power wells sharing
the same flags in an upcoming patch.
Imre Deak [Thu, 14 Apr 2022 21:06:42 +0000 (00:06 +0300)]
drm/i915: Move the power domain->well mappings to intel_display_power_map.c
Move the list of platform specific power domain -> power well
definitions to intel_display_power_map.c. While at it group the
platforms' power domain macros with the corresponding power well lists
and keep all the power domain lists in the same order (matching the enum
order).
Imre Deak [Thu, 14 Apr 2022 21:06:40 +0000 (00:06 +0300)]
drm/i915: Move per-platform power well hooks to intel_display_power_well.c
Move the implementation of platform specific power well hooks to
intel_display_power_well.c, to reduce the clutter in
intel_display_power.c.
The locking of all the power domain/power well state is handled in the
power domain functions in intel_display_power.c using
i915_power_domains::lock. This patch also moves the
chy_phy_powergate_ch/lanes() functions to intel_display_power_well.c
which borrow the same lock to protect the DISPLAY_PHY_CONTROL register
state, which the HW uses both for toggling power wells and power gating
PHY lanes.
No functional change.
v2:
- Clarify in the commit log why CHV functions using the
i915_power_domains::lock were moved, while others locking the power
domain/well state were kept in intel_display_power.c . (Jouni)
- Move forward declaration of chv_phy_powergate_ch/lanes() to
intel_display_power_well.h .
drm/solomon: Add SSD130x OLED displays SPI support
The ssd130x driver only provides the core support for these devices but it
does not have any bus transport logic. Add a driver to interface over SPI.
There is a difference in the communication protocol when using 4-wire SPI
instead of I2C. For the latter, a control byte that contains a D/C# field
has to be sent. This field tells the controller whether the data has to be
written to the command register or to the graphics display data memory.
But for 4-wire SPI that control byte is not used, instead a real D/C# line
must be pulled HIGH for commands data and LOW for graphics display data.
For this reason the standard SPI regmap can't be used and a custom .write
bus handler is needed.
drm/solomon: Move device info from ssd130x-i2c to the core driver
These are declared in the ssd130x-i2c transport driver but the information
is not I2C specific, and could be used by other SSD130x transport drivers.
Move them to the ssd130x core driver and just set the OF device entries to
an ID that could be used to lookup the correct device info from an array.
While being there, also move the SSD130X_DATA and SSD130X_COMMAND control
bytes. Since even though they are used by the I2C interface, they could
also be useful for other transport protocols such as SPI.
drm/solomon: Add ssd130x new compatible strings and deprecate old ones.
The current compatible strings for SSD130x I2C controllers contain an "fb"
and "-i2c" suffixes. These have been deprecated and more correct ones were
added, that don't encode a subsystem or bus used to interface the devices.
The current compatible strings for SSD130x I2C controllers contain both an
"fb" and "-i2c" suffixes. It seems to indicate that are for a fbdev driver
and also that are for devices that can be accessed over an I2C bus.
But a DT is supposed to describe the hardware and not Linux implementation
details. So let's deprecate those compatible strings and add new ones that
only contain the vendor and device name, without any of these suffixes.
These will just describe the device and can be matched by both I2C and SPI
DRM drivers. The required properties should still be enforced for old ones.
While being there, just drop the "sinowealth,sh1106-i2c" compatible string
since that was never present in a released Linux version.
Ville Syrjälä [Mon, 21 Mar 2022 19:50:04 +0000 (21:50 +0200)]
drm/i915: Program i830 DPLL FP register later
Follow the new i9xx DPLL FP register programming sequence
introduced in commit 62d66b218386 ("drm/i915: Fold
i9xx_set_pll_dividers() into i9xx_enable_pll()") in the
i830 "power well" code as well. Just for consistency.
drm/i915: program wm blocks to at least blocks required per line
In configurations with single DRAM channel, for usecases like
4K 60 Hz, FIFO underruns are observed quite frequently. Looks
like the wm0 watermark values need to bumped up because the wm0
memory latency calculations are probably not taking the DRAM
channel's impact into account.
As per the Bspec 49325, if the ddb allocation can hold at least
one plane_blocks_per_line we should have selected method2.
Assuming that modern HW versions have enough dbuf to hold
at least one line, set the wm blocks to equivalent to blocks
per line.
v2: styling and comments changes (Ville)
v3: Updated the reviewed-by tag
v4: max_t to max and patch styling (Ville)
projects / linux.git / log