accel/habanalabs: minimize encapsulation signal mutex lock time
Sync Stream Encapsulated Signal Handlers can be managed from different
contexts, and as such they are protected via a spin_lock.
However, spin_lock was unnecessarily protecting a larger code section
than really needed, covering a sleepable code section as well.
Since spin_lock disables preemption, it could lead to sleeping in
atomic context.
Jani Nikula [Fri, 26 May 2023 16:38:08 +0000 (19:38 +0300)]
drm/i915: re-enable -Wunused-but-set-variable
W=1 enables -Wunused-but-set-variable. We disabled it locally in i915
Makefile as we were hitting a bunch of warnings. See commit 6a05d2900464
("drm/i915: Disable unused-but-set compiler warning").
With the issues fixed or annotated with __maybe_unused, re-enable the
warning not only in W=1 but also locally as part of i915 build.
Zhi Wang [Wed, 31 May 2023 02:04:11 +0000 (02:04 +0000)]
drm/i915/gvt: remove unused variable gma_bottom in command parser
Remove unused variable gma_bottom in scan_workload() and scan_wa_ctx().
commit be1da7070aea ("drm/i915/gvt: vGPU command scanner") introduces
gma_bottom in several functions to calculate the size of the command
buffer. However, some of them are set but actually unused.
When compiling the code with ccflags -Wunused-but-set-variable, gcc
throws warnings.
Remove unused variables to avoid the gcc warnings. Tested via compiling
the code with ccflags -Wunused-but-set-variable.
On DG2, capturing OA reports while running heavy render workloads
sometimes results in invalid OA reports where 64-byte chunks inside
reports have stale values. Under memory pressure, high OA sampling rates
(13.3 us) and heavy render workload, occasionally, the OA HW TAIL
pointer does not progress as fast as the sampling rate. When these
glitches occur, the TAIL pointer takes approx. 200us to progress. While
this is expected behavior from the HW perspective, invalid reports are
not expected.
In oa_buffer_check_unlocked(), when we execute the if condition, we are
updating the oa_buffer.tail to the aging tail and then setting pollin
based on this tail value, however, we do not have a chance to rewind and
validate the reports prior to setting pollin. The validation happens
in a subsequent call to oa_buffer_check_unlocked(). If a read occurs
before this validation, then we end up reading reports up until this
oa_buffer.tail value which includes invalid reports. Though found on
DG2, this affects all platforms.
The aging tail logic is no longer necessary since we are explicitly
checking for landed reports.
Start by dropping the aging tail logic.
v2:
- Drop extra blank line
- Add reason to drop aging logic (Ashutosh)
- Add bug links (Ashutosh)
- rename aged_tail to read_tail
- Squash patches 3 and 1
v3: (Ashutosh)
- Remove extra spaces
- Remove gtt_offset from the pollin calculation
- s/Bug:/Link/ in commit message (checkpatch)
Mika Kahola [Tue, 6 Jun 2023 20:10:32 +0000 (23:10 +0300)]
drm/i915/mtl: Add support for PM DEMAND
MTL introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
Wa_14016740474 is added which applies to Xe_LPD+ display
v2: checkpatch warning fixes, simplify program pmdemand part
v3: update to dbufs and pipes values to pmdemand register(stan)
Removed the macro usage in update_pmdemand_values()
v4: move the pmdemand_pre_plane_update before cdclk update
pmdemand_needs_update included cdclk params comparisons
pmdemand_state NULL check (Gustavo)
pmdemand.o in sorted order in the makefile (Jani)
update pmdemand misc irq handler loop (Gustavo)
active phys bitmask and programming correction (Gustavo)
v5: simplify pmdemand_state structure
simplify methods to find active phys and max port clock
Timeout in case of previou pmdemand task pending (Gustavo)
v6: rebasing
updates to max_ddiclk calculations (Gustavo)
updates to active_phys count method (Gustavo)
v7: use two separate loop to iterate throug old and new
crtc states to calculate the active phys (Gustavo)
v8: use uniform function names (Gustavo)
v9: For phys change iterate through connectors (Imre)
Look for change in phys for pmdemand update (Gustavo, Imre)
Some more stlying changes (Imre)
Update pmdemand state during HW readout/sanitize (Imre)
v10: Fix CI checkpatch warnings
v11: use correct pmdemand object pointer during hw readout,
simplify the check for phys need update (Gustavo)
v12: Handle possible non serialize cases (Imre)
Initialise also pmdemand params HW readout (Imre)
Update active phys mask during sanitize calls (Imre)
Check TC/encoder changes to limit connector update (Imre)
v13: Check display version before accessing pmdemand functions
v14: Move is_serialized to intel_global_state.c
simplify update params and other stlying issues (Imre)
drm/i915/mtl: find the best QGV point for the SAGV configuration
From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
v1: Fix for warning from kernel test robot
v2: No need to serialize for the peakbw change as pmdemand code
will do that (Imre)
drm/i915: modify max_bw to return index to intel_bw_info
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned by max_bw_index functions
v3: return UINT_MAX in icl_max_bw_index in case no match found
drm/i915: update the QGV point frequency calculations
From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
v2: use DIV_ROUND_* macro for the calculations (Ville)
v3: Use only DIV_ROUN_CLOSEST and remove divisor / 2 again
Fei Yang [Tue, 6 Jun 2023 10:00:42 +0000 (12:00 +0200)]
drm/i915: Allow user to set cache at BO creation
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.
However, since PAT index was not clearly defined for platforms prior to
GEN12 (TGL), so we are limiting this externsion to GEN12+ platforms
only. See ext_set_pat() in for the implementation details.
The documentation related to the PAT/MOCS tables is currently available
for Tiger Lake here:
https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html
The documentation for other platforms is currently being updated.
BSpec: 45101
Mesa support has been submitted in this merge request:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
The media driver supprt has bin submitted in this merge request:
https://github.com/intel/media-driver/pull/1680
The IGT test related to this change is
igt@gem_create@create-ext-set-pat
Jani Nikula [Fri, 26 May 2023 16:38:06 +0000 (19:38 +0300)]
drm/i915: annotate maybe unused but set intel_crtc_state variables
Prepare for re-enabling -Wunused-but-set-variable.
for_each_new_intel_crtc_in_state() requires passing in a struct
intel_crtc_state pointer, which it uses, but in a few places this leads
to warning about unused but set variables. Annotate them with
__maybe_unused.
Jani Nikula [Fri, 26 May 2023 16:38:05 +0000 (19:38 +0300)]
drm/i915: annotate maybe unused but set intel_plane_state variables
Prepare for re-enabling -Wunused-but-set-variable.
for_each_new_intel_plane_in_state() requires passing in a struct
intel_plane_state pointer, which it uses, but in many places this leads
to warning about unused but set variables. Annotate them with
__maybe_unused.
Jani Nikula [Fri, 26 May 2023 16:38:04 +0000 (19:38 +0300)]
drm/i915/selftest: annotate maybe unused but set variable unused
Prepare for re-enabling -Wunused-but-set-variable.
The variable is indeed 'unused' as the name suggests, but we can't just
drop it because i915_vma_unbind_unlocked() is annotated
__must_check. Apparently the selftest does not really need to check the
value.
Tvrtko Ursulin [Mon, 5 Jun 2023 13:11:35 +0000 (14:11 +0100)]
drm/i915/selftests: Add some missing error propagation
Add some missing error propagation in live_parallel_switch.
To avoid needlessly burdening the various backport processes, note I am
not marking it as a fix against any patches and not copying stable since
it is debug/selftests only code.
Matt Roper [Thu, 1 Jun 2023 17:38:04 +0000 (10:38 -0700)]
drm/i915: Fix error handling if driver creation fails during probe
If i915_driver_create() fails to create a valid 'i915' object, we
should just disable the PCI device and return immediately without trying
to call i915_probe_error() that relies on a valid i915 pointer.
Matt Roper [Fri, 2 Jun 2023 18:14:50 +0000 (11:14 -0700)]
drm/i915/display: Extract display init from intel_device_info_runtime_init
Moving display-specific runtime info initialization into display/ makes
the display code more self-contained and also makes it easier to call
from the Xe driver.
v2:
- Drop unnecessary display/ prefix from #includes. (Jani)
- Clear runtime info if fusing leaves no pipes remaining, the same as
we do when fusing indicates the entire display controller is
unavailable. (Jani)
- Move adjustment of DRIVER_MODESET / DRIVER_ATOMIC after call to
intel_display_device_info_runtime_init(); HAS_DISPLAY may have
changed to false during the runtime init. (Jani)
drm/i915/mtl/huc: Use the media gt for the HuC getparam
On MTL, for obvious reasons, HuC is only available on the media tile.
We already disable SW support for HuC on the root gt due to the
absence of VCS engines, but we also need to update the getparam to point
to the HuC struct in the media GT.
The full authentication via the GSC requires an heci packet submission
to the GSC FW via the GSC CS. The GSC has new PXP command for this
(literally called NEW_HUC_AUTH).
The intel_huc_auth function is also updated to handle both authentication
types.
v2: check that the GuC auth for clear media has completed before
proceding with the full auth
drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with
GSC-enabled binaries being considered fully authenticated only after
the GSC auth step.
To report the difference between the 2 auth steps, a new case is added
to the HuC getparam. This way, the clear media driver can start
submitting before full auth, as partial auth is enough for those
workloads.
v2: fix authentication status check for DG2
v3: add a better comment at the top of the HuC file to explain the
different approaches to load and auth (John)
v4: update call to intel_huc_is_authenticated in the pxp code to check
for GSC authentication
v5: drop references to meu and esclamation mark in huc_auth print (John)
drm/i915/huc: Load GSC-enabled HuC via DMA xfer if the fuse says so
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case has been renamed to "has GSC headers"
for clarity, while the latter is now based on the fuse instead of the
binary format. This way, all the legacy load paths are automatically
taken (including the auth by GuC) without having to implement further
code changes.
The new binaries that support the 2-step authentication contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the
manifest of the GSC-enabled HuC binary. The manifest consist of a
partition header followed by entries, one of which contains the offset
we're looking for.
Note that the DG2 GSC binary contains entries with the same names, but
it doesn't contain a full legacy binary, so we need to skip assigning
the dma offset in that case (which we can do by checking the ccs).
Also, since we're now parsing the entries, we can extract the HuC
version that way instead of using hardcoded offsets.
Note that the GSC binary uses the same structures in its binary header,
so they've been added in their own header file.
v2: fix structure names to match meu defines (s/CPT/CPD/), update commit
message, check ccs validity, drop old version location defines.
v3: drop references to the MEU tool to reduce confusion, fix log (John)
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW to be
pinned in GGTT after the xfer is completed.
Since the vma is now valid for a long time and not just for the quick
pin-load-unpin dance, the name "dummy" is no longer appropriare and has
been replaced with vma_res. All the functions have also been updated to
operate on vma_res for consistency.
Given that we pin the vma behind the allocator's back (which is ok
because we do the pinning in an area that was previously reserved for
thus purpose), we do need to explicitly re-pin on resume because the
automated helper won't cover us.
v2: better comments and commit message, s/dummy/vma_res/
Masahiro Yamada [Mon, 5 Jun 2023 12:00:20 +0000 (21:00 +0900)]
drm/bridge: imx: fix mixed module-builtin object
With CONFIG_DRM_IMX8QM_LDB=m and CONFIG_DRM_IMX8QXP_LDB=y (or vice
versa), imx-ldb-helper.o is linked to a module and also to vmlinux
even though the expected CFLAGS are different between builtins and
modules.
This is the same situation as fixed by commit 637a642f5ca5 ("zstd:
Fixing mixed module-builtin objects").
Dafna Hirschfeld [Thu, 16 Mar 2023 08:20:44 +0000 (10:20 +0200)]
accel/habanalabs: extract and save the FW's SW major/minor/sub-minor
It is not always possible to know the FW's SW version from the inner FW
version. Therefore we should extract the general SW version in addition
to the FW version and use it in functions like
'hl_is_fw_ver_below_1_9' etc.
accel/habanalabs: rename fw_{major/minor}_version to fw_inner_{major/minor}_ver
We later want to add fields for Firmware SW version. The current
extracted FW version is the inner FW versioning so the new name
is better and also better differentiate from the FW's SW version.
accel/habanalabs: allow user to modify EDMA RL register
EDMA transpose workload requires to signal for every activation.
User FW sends all the dummy signals to RD_LBW_RATE_LIM_CFG, to save
lbw bandwidth. We need the user to be able to access that register to
configure it.
Tal Cohen [Thu, 30 Mar 2023 10:38:19 +0000 (13:38 +0300)]
accel/habanalabs: ignore false positive razwi
In Gaudi2 asic, PSOC RAZWI may cause in HBW or LBW. The address that
caused the error is read from HW register and printed by the Driver.
There are cases where the Driver receives an indication on PSOC
RAZWI error but the address value is zero. In that case, the indication
is a false positive.
The Driver should not "count" a PSOC RAZWI event error when the
caused the address is zeroed.
Tom Rix [Tue, 11 Apr 2023 14:08:50 +0000 (10:08 -0400)]
accel/habanalabs: remove variable gaudi_irq_name
gcc with W=1 reports
drivers/accel/habanalabs/gaudi/gaudi.c:117:19: error:
‘gaudi_irq_name’ defined but not used [-Werror=unused-const-variable=]
117 | static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {
| ^~~~~~~~~~~~~~
Mika Kahola [Thu, 1 Jun 2023 10:13:14 +0000 (13:13 +0300)]
drm/i915/mtl: Reset only one lane in case of MFD
In case when only two or less transmit lanes are owned such as MFD
(DP-alt with x2 lanes) we need to reset only one data lane (lane0).
With only x2 lanes we don't need to poll for the phy current
status on both data lanes since only the owned data lane will respond.
v2: Find better naming for lanes and revise the commit message (Luca)
Jouni Högander [Tue, 30 May 2023 10:16:49 +0000 (13:16 +0300)]
drm/i915: Use 18 fast wake AUX sync len
HW default for wake sync pulses is 18. 10 precharge and 8 preamble. There
is no reason to change this especially as it is causing problems with
certain eDP panels.
drm/virtio: Wait for each dma-fence of in-fence array individually
Use dma-fence-unwrap API for waiting each dma-fence of the in-fence array
individually. Sync file's in-fence array always has a non-matching fence
context ID, which doesn't allow to skip waiting of fences with a matching
context ID in a case of a merged sync file fence.
drm/virtio: Refactor and optimize job submission code path
Move virtio_gpu_execbuffer_ioctl() into separate virtgpu_submit.c file,
refactoring and optimizing the code along the way to ease addition of new
features to the ioctl.
The optimization is done by using optimal ordering of the job's submission
steps, reducing code path from the start of the ioctl to the point of
pushing job to virtio queue. Job's initialization is now performed before
in-fence is awaited and out-fence setup is made after sending out job to
virtio.
Jeffrey Hugo [Tue, 23 May 2023 16:14:21 +0000 (10:14 -0600)]
MAINTAINERS: Add Carl/Pranjal as QAIC reviewers
Carl and Pranjal have been reviewing the QAIC patches. List them as
reviewers so that they are copied on all developments which will make
it easier for them to continue reviewing QAIC patches.
drm/i915: Flush power delayed put when connector init failed
When intel_dp_init_connector fails, some power wells used in dp aux
communication may not be completely disabled yet. This may result in a
null pointer dereference when icl_aux_pw_to_phy() is called from
icl_combo_phy_aux_power_well_disable() after the encoder and connector
are already freed.
enum i915_drm_suspend_mode suspend_mode is only used in
intel_display_power, while we only care about whether we perform a
s2idle. Remove it and use a simple bool.
drm/i915/pxp: Fix size_t format specifier in gsccs_send_message()
When building ARCH=i386 allmodconfig, the following warning occurs:
In file included from include/linux/device.h:15,
from include/linux/node.h:18,
from include/linux/cpu.h:17,
from include/linux/static_call.h:135,
from arch/x86/include/asm/perf_event.h:5,
from include/linux/perf_event.h:25,
from drivers/gpu/drm/i915/i915_pmu.h:11,
from drivers/gpu/drm/i915/gt/intel_engine_types.h:21,
from drivers/gpu/drm/i915/gt/intel_context_types.h:18,
from drivers/gpu/drm/i915/gem/i915_gem_context_types.h:20,
from drivers/gpu/drm/i915/i915_request.h:34,
from drivers/gpu/drm/i915/i915_active.h:13,
from drivers/gpu/drm/i915/gt/intel_context.h:13,
from drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:8:
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c: In function 'gsccs_send_message':
include/drm/drm_print.h:456:39: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
456 | dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
| ^~~~~~~~
include/linux/dev_printk.h:110:30: note: in definition of macro 'dev_printk_index_wrap'
110 | _p_func(dev, fmt, ##__VA_ARGS__); \
| ^~~
include/linux/dev_printk.h:146:61: note: in expansion of macro 'dev_fmt'
146 | dev_printk_index_wrap(_dev_warn, KERN_WARNING, dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
include/drm/drm_print.h:456:9: note: in expansion of macro 'dev_warn'
456 | dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
| ^~~~
include/drm/drm_print.h:466:9: note: in expansion of macro '__drm_printk'
466 | __drm_printk((drm), warn,, fmt, ##__VA_ARGS__)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c:146:17: note: in expansion of macro 'drm_warn'
146 | drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n",
| ^~~~~~~~
cc1: all warnings being treated as errors
Use the '%zu' format specifier, as the variable is a 'size_t'.
Arnd Bergmann [Fri, 2 Jun 2023 12:45:24 +0000 (14:45 +0200)]
drm/meson: venc: include linux/bitfield.h
Without this header, the use of FIELD_PREP() can cause a build failure:
drivers/gpu/drm/meson/meson_venc.c: In function 'meson_encl_set_gamma_table':
drivers/gpu/drm/meson/meson_venc.c:1595:24: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
Jani Nikula [Tue, 30 May 2023 09:08:25 +0000 (12:08 +0300)]
drm/i915/display: switch the rest of the connectors to struct drm_edid
Convert the remaining uses of struct edid based drm_get_edid(),
drm_connector_update_edid_property() and drm_add_edid_modes() calls to
the struct drm_edid based drm_edid_read_ddc(),
drm_edid_connector_update() and drm_edid_connector_add_modes().
Jani Nikula [Tue, 30 May 2023 09:08:24 +0000 (12:08 +0300)]
drm/display/dp_mst: convert to struct drm_edid
Convert the topology manager to use struct drm_edid, add
drm_dp_mst_edid_read() that returns drm_edid, and rewrite the old
drm_dp_mst_get_edid() to use it.
Note that the old drm_get_edid() ended up calling
drm_connector_update_edid_property(). This responsibility is now
deferred to drivers, which all do it anyway after calling
drm_dp_mst_edid_read() or drm_dp_mst_get_edid().
Jani Nikula [Tue, 30 May 2023 09:08:14 +0000 (12:08 +0300)]
drm/display/dp_mst: drop has_audio from struct drm_dp_mst_port
Caching the has_audio in struct drm_dp_mst_port seems odd, and oddly
placed. Defer audio handling to drivers, and use the info from the
connector display info. i915 was the only one using it anyway.
Jani Nikula [Tue, 30 May 2023 09:08:13 +0000 (12:08 +0300)]
drm/edid: parse display info has_audio similar to is_hdmi
Since we already iterate everything that's needed for determining audio,
reduce the need to call drm_detect_monitor_audio() by storing has_audio
to connector info.
The warning is pointing out that while 'enum i915_cache_level' and
'unsigned int' are ABI compatible, these indirect calls will fail
clang's kernel Control Flow Integrity (kCFI) checks, as the callback's
signature does not exactly match the prototype's signature.
To fix this, replace the cache_level parameter with pat_index, as was
done in other places within i915 where there is no difference between
cache_level and pat_index on certain generations.
drm/i915/gt: Fix second parameter type of pre-gen8 pte_encode callbacks
When booting a kernel compiled with CONFIG_CFI_CLANG (kCFI), there is a
CFI failure in ggtt_probe_common() when trying to call hsw_pte_encode()
via an indirect call:
With kCFI, indirect calls are validated against their expected type
versus actual type and failures occur when the two types do not match.
clang's -Wincompatible-function-pointer-types-strict can catch this at
compile time but it is not enabled for the kernel yet:
drivers/gpu/drm/i915/gt/intel_ggtt.c:1155:23: error: incompatible function pointer types assigning to 'u64 (*)(dma_addr_t, unsigned int, u32)' (aka 'unsigned long long (*)(unsigned int, unsigned int, unsigned int)') from 'u64 (dma_addr_t,
enum i915_cache_level, u32)' (aka 'unsigned long long (unsigned int, enum i915_cache_level, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict]
ggtt->vm.pte_encode = iris_pte_encode;
^ ~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gt/intel_ggtt.c:1157:23: error: incompatible function pointer types assigning to 'u64 (*)(dma_addr_t, unsigned int, u32)' (aka 'unsigned long long (*)(unsigned int, unsigned int, unsigned int)') from 'u64 (dma_addr_t,
enum i915_cache_level, u32)' (aka 'unsigned long long (unsigned int, enum i915_cache_level, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict]
ggtt->vm.pte_encode = hsw_pte_encode;
^ ~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gt/intel_ggtt.c:1159:23: error: incompatible function pointer types assigning to 'u64 (*)(dma_addr_t, unsigned int, u32)' (aka 'unsigned long long (*)(unsigned int, unsigned int, unsigned int)') from 'u64 (dma_addr_t,
enum i915_cache_level, u32)' (aka 'unsigned long long (unsigned int, enum i915_cache_level, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict]
ggtt->vm.pte_encode = byt_pte_encode;
^ ~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gt/intel_ggtt.c:1161:23: error: incompatible function pointer types assigning to 'u64 (*)(dma_addr_t, unsigned int, u32)' (aka 'unsigned long long (*)(unsigned int, unsigned int, unsigned int)') from 'u64 (dma_addr_t,
enum i915_cache_level, u32)' (aka 'unsigned long long (unsigned int, enum i915_cache_level, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict]
ggtt->vm.pte_encode = ivb_pte_encode;
^ ~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gt/intel_ggtt.c:1163:23: error: incompatible function pointer types assigning to 'u64 (*)(dma_addr_t, unsigned int, u32)' (aka 'unsigned long long (*)(unsigned int, unsigned int, unsigned int)') from 'u64 (dma_addr_t,
enum i915_cache_level, u32)' (aka 'unsigned long long (unsigned int, enum i915_cache_level, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict]
ggtt->vm.pte_encode = snb_pte_encode;
^ ~~~~~~~~~~~~~~
5 errors generated.
In this case, the pre-gen8 pte_encode functions have a second parameter
type of 'enum i915_cache_level' whereas the function pointer prototype
in 'struct i915_address_space' expects a second parameter type of
'unsigned int'.
Update the second parameter of the callbacks and the comment above them
noting that these statements are still valid, which matches other
functions and files, to clear up the kCFI failures at run time.
Cong Yang [Thu, 25 May 2023 09:31:51 +0000 (17:31 +0800)]
drm/panel: Support for Starry-ili9882t TDDI MIPI-DSI panel
The Starry-ili9882 is a 10.51" WUXGA TFT panel. which fits in nicely with
the existing panel-boe-tv101wum-nl6 driver. From the datasheet,MIPI need
to keep the LP11 state before the lcm_reset pin is pulled high. So add
lp11_before_reset flag.
Cong Yang [Thu, 25 May 2023 09:31:50 +0000 (17:31 +0800)]
dt-bindings: display: panel: Add compatible for Starry ili9882t
The STARRY ili9882t is a 10.51" WUXGA TFT LCD panel,
which fits in nicely with the existing panel-boe-tv101wum-nl6
driver. Hence, we add a new compatible with panel specific config.
Cong Yang [Thu, 25 May 2023 09:31:49 +0000 (17:31 +0800)]
drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel
The Starry-himax83102-j02 is a 10.51" WUXGA TFT panel. which fits in nicely
with the existing panel-boe-tv101wum-nl6 driver. From the datasheet[1], MIPI
needs to keep the LP11 state before the lcm_reset pin is pulled high, so
increase lp11_before_reset flag.
Cong Yang [Thu, 25 May 2023 09:31:48 +0000 (17:31 +0800)]
dt-bindings: display: panel: Add compatible for Starry himax83102-j02
The STARRY himax83102-j02 is a 10.51" WUXGA TFT LCD panel,
which fits in nicely with the existing panel-boe-tv101wum-nl6
driver. Hence, we add a new compatible with panel specific config.
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