Arnd Bergmann [Mon, 20 Dec 2021 14:55:51 +0000 (15:55 +0100)]
Merge tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt
Devicetree changes for TI K3 platforms for v5.17 merge window:
* New Platforms:
- J721s2 SoC, SoM and Common Processor Board support
* New features:
- CAN support on AM64 EVM and SK
- TimeSync Router on AM64
* Fixes:
- Correct d-cache-sets info on J7200
- Fix L2 cache-sets value for J721e/J7200/AM64
- Fixes for dtbs_check warnings wrt serdes_ln_ctrl node on J721e/J7200
- Disable McASP on IoT2050 board to fix dtbs_check warnings
* tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arch: arm64: ti: Add support J721S2 Common Processor Board
arm64: dts: ti: Add initial support for J721S2 System on Module
arm64: dts: ti: Add initial support for J721S2 SoC
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
dt-bindings: arm: ti: Add bindings for J721s2 SoC
arm64: dts: ti: iot2050: Disable mcasp nodes at dtsi level
arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK
arm64: dts: ti: k3-am64-main: Add support for MCAN
arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes
arm64: dts: ti: k3-j721e: Add support for MCAN nodes
arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes
arm64: dts: ti: k3-am65-mcu: Add Support for MCAN
arm64: dts: ti: k3-am64-main: add timesync router node
arm64: dts: ti: k3-j7200: Correct the d-cache-sets info
arm64: dts: ti: k3-j721e: Fix the L2 cache sets
arm64: dts: ti: k3-j7200: Fix the L2 cache sets
arm64: dts: ti: k3-am642: Fix the L2 cache sets
arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node
arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node
arm64: dts: ti: k3-j721e: correct cache-sets info
Arnd Bergmann [Mon, 20 Dec 2021 14:49:16 +0000 (15:49 +0100)]
Merge tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.17-rc1
The vast majority of this contains various updates and cleanups to the
Tegra device trees that will eventually help validate all of them using
the dt-schema infrastructure.
Another notable chunk of this contains additional Tegra234 support as
well as support for the new Jetson AGX Orin Developer Kit.
* tag 'tegra-for-5.17-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (47 commits)
arm64: tegra: Add host1x hotflush reset on Tegra210
arm64: tegra: Hook up MMC and BPMP to memory controller
arm64: tegra: Add memory controller on Tegra234
arm64: tegra: Add EMC general interrupt on Tegra194
arm64: tegra: Update SDMMC4 speeds for Tegra194
arm64: tegra: Add dma-coherent for Tegra194 VIC
arm64: tegra: Rename Ethernet PHY nodes
arm64: tegra: Remove unused only-1-8-v properties
arm64: tegra: Sort Tegra210 XUSB clocks correctly
arm64: tegra: Add missing TSEC properties on Tegra210
arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
arm64: tegra: Rename GPIO hog nodes to match schema
arm64: tegra: Remove unsupported regulator properties
arm64: tegra: Rename TCU node to "serial"
arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
arm64: tegra: Drop unused properties for Tegra194 PCIe
arm64: tegra: Fix Tegra194 HSP compatible string
arm64: tegra: Drop unsupported nvidia,lpdr property
...
CN9130 has a built-in CP115 which has 2 GPIO controllers, but unlike in
Armada 7k and 8k both are left disabled by the SoC DTSI.
This first of all makes no sense as they are always present due to being
SoC built-in and its an issue as boards like CN9130-CRB use the CPO GPIO2
pins for regulators and SD card support without enabling them first.
So, enable both of them like Armada 7k and 8k do.
Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
Robert Marko [Fri, 12 Nov 2021 13:44:02 +0000 (14:44 +0100)]
arm64: dts: marvell: cn9130: add GPIO and SPI aliases
CN9130 has one CP115 built in, which like the CP110 has 2 GPIO and 2 SPI
controllers built-in.
However, unlike the Armada 7k and 8k the SoC DTSI doesn't add the required
aliases as both the Orion SPI driver and MVEBU GPIO drivers require the
aliases to be present.
So add the required aliases for GPIO and SPI controllers.
Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
Pali Rohár [Wed, 8 Dec 2021 02:40:35 +0000 (03:40 +0100)]
arm64: dts: marvell: armada-37xx: Add xtal clock to comphy node
Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the
reference xtal clock. So add missing xtal clock source into comphy device
tree node. If the property is not present, the driver defaults to 25 MHz
xtal rate (which, as far as we know, is used by all the existing boards).
Arnd Bergmann [Fri, 17 Dec 2021 14:53:29 +0000 (15:53 +0100)]
Merge tag 'renesas-arm-dt-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.17 (take two)
- Initial support for the R-Car S4-8 SoC on the Spider CPU and
BreakOut boards,
- MIPI DSI display support for the R-Car V3u SoC and the Falcon board
stack,
- Thermal and GPU support for the RZ/G2L SoC and the RZ/G2L SMARC EVK
development board,
- Miscellaneous fixes and improvements.
Arnd Bergmann [Fri, 17 Dec 2021 14:52:07 +0000 (15:52 +0100)]
Merge tag 'sunxi-dt-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual round of DT patches for the 5.17 merge window, with:
- Introduction of the chassis-type property
- I2C, SPDIF support for the Tanix TX6
- Memory frequency scaling for the A64 and H5
- Hantro G2 support for the H6
- New Board: Tanix TX6 Mini
Dmitry Osipenko [Tue, 30 Nov 2021 23:23:11 +0000 (02:23 +0300)]
dt-bindings: clock: tegra-car: Document new clock sub-nodes
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to them, clock controller is in charge of managing power for them.
Svyatoslav Ryhel [Sat, 11 Dec 2021 21:13:45 +0000 (00:13 +0300)]
dt-bindings: ARM: tegra: Document ASUS Transformers
Document Tegra20/30/114-based ASUS Transformer Series tablet devices.
This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG
Infinity TF700T, TF701T.
Thierry Reding [Mon, 6 Dec 2021 15:55:59 +0000 (16:55 +0100)]
dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties
Add the interconnects, interconnect-names and iommus properties to the
device tree bindings for the Tegra XUDC controller. These are used to
describe the device's paths to and from memory.
Thierry Reding [Mon, 13 Dec 2021 16:21:51 +0000 (17:21 +0100)]
arm64: tegra: Hook up MMC and BPMP to memory controller
Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.
Thierry Reding [Tue, 7 Dec 2021 14:05:32 +0000 (15:05 +0100)]
arm64: tegra: Sort Tegra210 XUSB clocks correctly
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Thierry Reding [Tue, 7 Dec 2021 13:47:47 +0000 (14:47 +0100)]
arm64: tegra: Drop unused properties for Tegra194 PCIe
The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.
Thierry Reding [Tue, 7 Dec 2021 13:28:29 +0000 (14:28 +0100)]
arm64: tegra: Adjust length of CCPLEX cluster MMIO region
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.
Thierry Reding [Tue, 7 Dec 2021 13:21:18 +0000 (14:21 +0100)]
arm64: tegra: Sort Tegra132 XUSB clocks correctly
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Thierry Reding [Tue, 7 Dec 2021 13:17:07 +0000 (14:17 +0100)]
arm64: tegra: Add OPP tables on Tegra132
Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.
Thierry Reding [Tue, 7 Dec 2021 13:13:37 +0000 (14:13 +0100)]
arm64: tegra: Fix compatible string for Tegra132 timer
The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.
Thierry Reding [Thu, 19 Mar 2020 15:45:38 +0000 (16:45 +0100)]
arm64: tegra: Add native timer support on Tegra186
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Thierry Reding [Mon, 6 Dec 2021 17:02:18 +0000 (18:02 +0100)]
arm64: tegra: Rename top-level regulators
Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
Thierry Reding [Mon, 6 Dec 2021 16:58:55 +0000 (17:58 +0100)]
arm64: tegra: Rename top-level clocks
Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
Jon Hunter [Wed, 1 Dec 2021 15:57:16 +0000 (15:57 +0000)]
arm64: tegra: Add ISO SMMU controller for Tegra194
The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.
Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.
This based upon an initial patch by Thierry Reding <[email protected]>.
Prathamesh Shete [Tue, 16 Nov 2021 12:02:36 +0000 (17:32 +0530)]
arm64: tegra: Add support to enumerate SD in UHS mode
Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad voltage switching and enumerate SD card in UHS-I modes.
Thierry Reding [Fri, 12 Nov 2021 13:19:04 +0000 (14:19 +0100)]
arm64: tegra: Describe Tegra234 CPU hierarchy
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.
Thierry Reding [Fri, 12 Nov 2021 12:35:37 +0000 (13:35 +0100)]
arm64: tegra: Fixup SYSRAM references
The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.
Thierry Reding [Thu, 16 Dec 2021 15:50:49 +0000 (16:50 +0100)]
Merge tag 'tegra-for-5.17-dt-bindings-memory' into for-5.17/arm64/dt
dt-bindings: memory: Add Tegra234 support
This stable tag contains the addition of the EMC clock ID and an initial
list of memory client IDs for Tegra234 and will be shared between the
memory and ARM SoC trees.
Thierry Reding [Mon, 13 Dec 2021 16:21:47 +0000 (17:21 +0100)]
dt-bindings: memory: tegra: Add Tegra234 support
Document the variant of the memory controller and external memory
controllers found on Tegra234 and add some memory client and SMMU
stream ID definitions for use in device tree files.
Thierry Reding [Mon, 13 Dec 2021 16:21:46 +0000 (17:21 +0100)]
dt-bindings: memory: tegra: Update for Tegra194
The #interconnect-cells properties are required to hook up memory
clients to the MC/EMC in interconnects properties. Add a description for
these properties.
For the nested EMC controller, the list of required properties was
missing. Add it so that the validation can be more strict.
Also, allow multiple reg entries required by Tegra194 and later.
While at it, also remove the dummy BPMP node from the example because it
is incomplete and fails validation. It's also not necessary for this
file and the BPMP DT schema already has a full example.
Thierry Reding [Fri, 12 Nov 2021 12:35:35 +0000 (13:35 +0100)]
dt-bindings: sram: Document NVIDIA Tegra SYSRAM
Tegra SoCs have extra on-chip RAM that can be used for inter-processor
communication. Tegra186 and later make use of it to establish a two-way
channel between the CCPLEX and BPMP. Add missing compatible strings for
Tegra186 and Tegra194 as well as a new compatible string for Tegra234.
Arnd Bergmann [Thu, 16 Dec 2021 14:00:32 +0000 (15:00 +0100)]
Merge tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Devicetree changes for omaps for v5.17 merge window
These changes are mostly minor non-urgent fixes for typos and binding checks.
The system-power-controller gets configured for more am3 devices as it's not
am335x-boneblack speicif. For for am437x we add magnetic card reader support.
Note that the asahi-kasei,ak8975 binding changes may produce a new binding
check warning as the binding related change is merged separately.
* tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp.
ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value
ARM: dts: am437x-gp-evm: enable ADC1
ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module
ARM: dts: am437x-cm-t43: Use a correctly spelled DT property
ARM: dts: am335x-icev2: Add system-power-controller to RTC node
ARM: dts: am335x-boneblack-common: move system-power-controller
ARM: dts: elpida_ecb240abacn: Change Elpida compatible
Arnd Bergmann [Thu, 16 Dec 2021 13:51:42 +0000 (14:51 +0100)]
Merge tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA dts updates for v5.17
- Update N5X to include qspi, usb and ethernet
- Adjust NAND partition size for Agilex and Stratix10
* tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: Update NAND MTD partition for Agilex and Stratix 10
arm64: dts: n5x: add qspi, usb, and ethernet support
Arnd Bergmann [Wed, 15 Dec 2021 14:56:39 +0000 (15:56 +0100)]
Merge tag 'asahi-soc-dt-5.17-v2' of https://github.com/AsahiLinux/linux into arm/dt
Apple SoC DT updates for 5.17, round 2:
- Various cleanups (removing useless props, sorting nodes, renaming
things)
- Add PMGR min-state binding & props (see PMGR pull for driver change)
- Initial compatibles for t600x machines (M1 Pro/Max). This covers the
bindings that just need compatible bumps & minor tweaks, no driver
changes.
- Add watchdog node (driver not merged yet, hopefully will be; binding
went in the previous pull)
- Add missing power-domains property to the mailbox binding
Arnd Bergmann [Wed, 15 Dec 2021 14:55:30 +0000 (15:55 +0100)]
Merge tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.17, round 1
Highlights:
----------
-MCU:
- fix ili9341 for dtbs_check warnings on stm32f429 disco.
- MPU:
- ST boards:
- tune HS USB phys on stm32mp15 EV1 and DKx boards.
- add pull-up on USART3/UART7 RX pins on STM32MP15 DKx boards.
- use correct pinctrl setting for STUSB1600 on STM32MP15 DK boards.
- ENGICAM:
- enable LVDS pannel on i.Core STM32MP1 EDIMM2.2.
- add "i.Core STM32MP1 C.TOUCH 2.0 10.1" OF" support:
EDIMM compliant general purpose carrier board with ETH 10/100,
WIFI/BT, CAN, ...
* tag 'stm32-dt-for-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2
ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk
ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards
ARM: dts: stm32: fix dtbs_check warning on ili9341 dts binding on stm32f429 disco
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