Eddie James [Thu, 17 Mar 2022 21:14:26 +0000 (16:14 -0500)]
spi: fsi: Implement a timeout for polling status
The data transfer routines must poll the status register to
determine when more data can be shifted in or out. If the hardware
gets into a bad state, these polling loops may never exit. Prevent
this by returning an error if a timeout is exceeded.
Biju Das [Wed, 16 Mar 2022 17:53:17 +0000 (17:53 +0000)]
spi: Fix erroneous sgs value with min_t()
While computing sgs in spi_map_buf(), the data type
used in min_t() for max_seg_size is 'unsigned int' where
as that of ctlr->max_dma_len is 'size_t'.
min_t(unsigned int,x,y) gives wrong results if one of x/y is
'size_t'
Consider the below examples on a 64-bit machine (ie size_t is
64-bits, and unsigned int is 32-bit).
case 1) min_t(unsigned int, 5, 0x100000001);
case 2) min_t(size_t, 5, 0x100000001);
Case 1 returns '1', where as case 2 returns '5'. As you can see
the result from case 1 is wrong.
This patch fixes the above issue by using the data type of the
parameters that are used in min_t with maximum data length.
Kuldeep Singh [Wed, 9 Mar 2022 17:18:47 +0000 (22:48 +0530)]
spi: Update clock-names property for arm pl022
PL022 has two input clocks named sspclk and apb_pclk. Current schema
refers to two notations of sspclk which are indeed same and thus one can
be dropped. Update clock-names property to reflect the same.
Add combined sequence mode supported by Tegra QSPI controller.
For commands which contain cmd, addr, data parts to it, controller
can accept all 3 transfers at once and avoid interrupt for each
transfer. This would improve read & write performance.
Add ACPI ID for Tegra QUAD SPI. Switch to common device property calls.
Skip clock calls that are not updated in ACPI boot.
Runtime PM support is not yet enabled with ACPI boot.
Biju Das [Mon, 7 Mar 2022 18:48:43 +0000 (18:48 +0000)]
spi: Fix invalid sgs value
max_seg_size is unsigned int and it can have a value up to 2^32
(for eg:-RZ_DMAC driver sets dma_set_max_seg_size as U32_MAX)
When this value is used in min_t() as an integer type, it becomes
-1 and the value of sgs becomes 0.
Fix this issue by replacing the 'int' data type with 'unsigned int'
in min_t().
dt-bindings: mfd: maxim,max77802: Convert to dtschema
Convert the MFD part of Maxim MAX77802 PMIC to DT schema format. The
example DTS was copied from existing DTS (exynos5800-peach-pi.dts), so
keep the license as GPL-2.0-only.
dt-bindings: mfd: maxim,max14577: Convert to dtschema
Convert the MFD part of Maxim MAX14577/MAX77836 MUIC to DT schema
format. The example DTS was copied from existing DTS
(exynos3250-rinato.dts), so keep the license as GPL-2.0-only.
regulator: dt-bindings: maxim,max14577: Convert to dtschema
Convert the regulator bindings of Maxim MAX14577/MAX77835 MUIC to DT
schema format. The existing bindings were defined in
../bindings/mfd/max14577.txt.
spi: s3c64xx: Allow controller-data to be optional
The Samsung SoC SPI driver requires to provide controller-data node
for each of SPI peripheral device nodes. Make this controller-data node
optional, so DTS could be simpler.
The ChromeOS Embedded Controller appears on boards with Samsung Exynos
SoC, where Exynos SPI bindings expect controller-data node. Reference
SPI peripheral bindings which include now Samsung SPI peripheral parts.
Convert the Samsung SoC (S3C24xx, S3C64xx, S5Pv210, Exynos) SPI
controller bindings to DT schema format.
The conversion also drops requirement from providing controller-data and
its data for each of SPI peripheral device nodes. The dtschema cannot
express this and the requirement is being relaxed in the driver now.
MAINTAINERS: mfd: Cover MAX77843 by Maxim PMIC/MUIC for Exynos boards entry
The MAX77843 is used in Exynos5433-based TM2 boards and shares some
parts of code with MAX77693 (regulator and haptic motor drivers).
Include all MAX77843 drivers in the entry for Maxim PMIC/MUIC drivers
for Exynos boards, so they will receive some dedicated review coverage.
Document the bindings for MAX77843 MFD driver, based on Exynos5433 TM2
devicetree. These are neither accurate nor finished bindings but at
least allow parsing existing DTS files.
The example DTS was copied from existing DTS
(exynos5433-tm2-common.dtsi), so keep the license as GPL-2.0-only.
Document the bindings for MAX77843 MUIC/extcon driver, based on
Exynos5433 TM2 devicetree. These are neither accurate nor finished
bindings but at least allow parsing existing DTS files.
Rob Herring [Tue, 1 Mar 2022 21:23:57 +0000 (15:23 -0600)]
spi: dt-bindings: mediatek: Set min size for 'mediatek,pad-select'
The minimum array length defaults to the same size as the maximum. For
'mediatek,pad-select', the example has a length of 2 and in-tree .dts
files have a length of 1, but the schema says the length must be 4.
There's currently no warning in the example because the schema fixups
are not handling this case correctly.
Add RSPI binding documentation for Renesas RZ/V2L SoC.
RSPI block is identical to one found on RZ/A, so no driver changes are
required. The fallback compatible string "renesas,rspi-rz" will be used
on RZ/V2L.
Yun Zhou [Thu, 17 Feb 2022 14:12:34 +0000 (22:12 +0800)]
spi: use specific last_cs instead of last_cs_enable
Commit d40f0b6f2e21 instroduced last_cs_enable to avoid setting
chipselect if it's not necessary, but it also introduces a bug. The
chipselect may not be set correctly on multi-device SPI busses. The
reason is that we can't judge the chipselect by bool last_cs_enable,
since chipselect may be modified after other devices were accessed.
So we should record the specific state of chipselect in case of
confusion.
Li-hao Kuo [Fri, 25 Feb 2022 06:31:53 +0000 (14:31 +0800)]
spi: dt-bindings: remove unused required property
fix issue
/builds/robherring/linux-dt/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.example.dt.yaml:
spi@9C002D80: 'clocks-names' is a required property
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml
delete unused required(clock-name)
Andy Shevchenko [Wed, 23 Feb 2022 19:19:48 +0000 (21:19 +0200)]
spi: pxa2xx-pci: Do not dereference fwnode in struct device
In order to make the underneath API easier to change in the future,
prevent users from dereferencing fwnode from struct device.
Instead, use the specific dev_fwnode() API for that.
Andreas Färber [Sat, 19 Feb 2022 13:15:48 +0000 (14:15 +0100)]
spi: gpio: Implement LSB First bitbang support
Add support for slave DT property spi-lsb-first, i.e., SPI_LSB_FIRST mode.
Duplicate the inline helpers bitbang_txrx_be_cpha{0,1} as LE versions.
Conditionally call them from all the spi-gpio txrx_word callbacks.
Some alternatives to this implementation approach were discussed back
then [0], but eventually it was considered reasonable.
Ahmad Fatoum [Tue, 1 Feb 2022 11:51:41 +0000 (12:51 +0100)]
spi: stm32: ignore Rx queue not empty in stm32f4 Tx only mode
STM32F4_SPI_SR_RXNE and STM32F4_SPI_SR_OVR are distinct bits in the same
status register. ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE is thus
equal to ~STM32F4_SPI_SR_OVR.
The original intention was likely for transmission-only transfers to
ignore interrupts both for when the Rx queue has bytes (RXNE) as well
as when these bytes haven't been read in time (OVR).
Describe two new memories modes:
- A stacked mode when the bus is common but the address space extended
with an additinals wires.
- A parallel mode with parallel busses accessing parallel flashes where
the data is spread.
Miquel Raynal [Wed, 26 Jan 2022 11:26:05 +0000 (12:26 +0100)]
dt-bindings: mtd: spi-nor: Allow two CS per device
The Xilinx QSPI controller has two advanced modes which allow the
controller to behave differently and consider two flashes as one single
storage.
One of these two modes is quite complex to support from a binding point
of view and is the dual parallel memories. In this mode, each byte of
data is stored in both devices: the even bits in one, the odd bits in
the other. The split is automatically handled by the QSPI controller and
is transparent for the user.
The other mode is simpler to support, it is called dual stacked
memories. The controller shares the same SPI bus but each of the devices
contain half of the data. Once in this mode, the controller does not
follow CS requests but instead internally wires the two CS levels with
the value of the most significant address bit.
Supporting these two modes will involve core changes which include the
possibility of providing two CS for a single SPI device
Heiner Kallweit [Fri, 18 Feb 2022 13:58:35 +0000 (14:58 +0100)]
spi: use sysfs_emit() for printing statistics and add trailing newline
Use dedicated function sysfs_emit() that does some extra checking,
e.g. to ensure that no more than PAGESIZE bytes are written.
In addition add a trailing newline to the output, that makes it
better readable from the console.
shengfei Xu [Wed, 16 Feb 2022 01:40:27 +0000 (09:40 +0800)]
spi: rockchip: Suspend and resume the bus during NOIRQ_SYSTEM_SLEEP_PM ops
the wakeup interrupt handler which is guaranteed not to run while
@resume noirq() is being executed. the patch can help to avoid the
wakeup source try to access spi when the spi is in suspend mode.
Jon Lin [Wed, 16 Feb 2022 01:40:26 +0000 (09:40 +0800)]
spi: rockchip: Preset cs-high and clk polarity in setup progress
After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the first
transmission coming.
Jon Lin [Wed, 16 Feb 2022 01:40:25 +0000 (09:40 +0800)]
spi: rockchip: Stop spi slave dma receiver when cs inactive
The spi which's version is higher than ver 2 will automatically
enable this feature.
If the length of master transmission is uncertain, the RK spi slave
is better to automatically stop after cs inactive instead of waiting
for xfer_completion forever.
André Almeida [Wed, 16 Feb 2022 16:27:19 +0000 (13:27 -0300)]
spi: amd: Fix building without ACPI enabled
Commit 209043554915 ("spi: amd: Add support for version AMDI0062")
removed the cast ACPI_PTR() for no good reason. This wrapper is
important to make sure that the driver can be compiled with or without
CONFIG_ACPI enabled, useful for compiling test. Give back the cast so
compilation works again.
it turns out that the preferred way to deal with the SPI flash controller
drivers is through SPI MEM which is part of Linux SPI subsystem.
This series does that for the intel-spi driver. This also renames the
driver to follow the convention used in the SPI subsystem. The first patch
improves the write protection handling to be slightly more safer. The
following two patches do the conversion itself. Note the Intel SPI flash
controller only allows commands such as read, write and so on and it
internally uses whatever addressing etc. it figured from the SFDP on the
flash device.
Linus Walleij [Thu, 10 Feb 2022 23:19:54 +0000 (00:19 +0100)]
spi: Retire legacy GPIO handling
All drivers using GPIOs as chip select have been rewritten to use
GPIO descriptors passing the ->use_gpio_descriptors flag. Retire
the code and fields used by the legacy GPIO API.
Do not drop the ->use_gpio_descriptors flag: it now only indicates
that we want to use GPIOs in addition to native chip selects.
Mika Westerberg [Wed, 9 Feb 2022 12:27:06 +0000 (15:27 +0300)]
Documentation / MTD: Rename the intel-spi driver
Since the driver is renamed (and moved) update the BIOS upgrade guide
accordingly from intel-spi to spi-intel. Keep the guide under MTD
documentation because this is pretty much still about MTD and SPI-NOR.
Mika Westerberg [Wed, 9 Feb 2022 12:27:05 +0000 (15:27 +0300)]
mtd: spi-nor: intel-spi: Convert to SPI MEM
The preferred way to implement SPI-NOR controller drivers is through SPI
subsubsystem utilizing the SPI MEM core functions. This converts the
Intel SPI flash controller driver over the SPI MEM by moving the driver
from SPI-NOR subsystem to SPI subsystem and in one go make it use the
SPI MEM functions. The driver name will be changed from intel-spi to
spi-intel to match the convention used in the SPI subsystem.
Mika Westerberg [Wed, 9 Feb 2022 12:27:04 +0000 (15:27 +0300)]
mtd: spi-nor: intel-spi: Disable write protection only if asked
Currently the driver tries to disable the BIOS write protection
automatically even if this is not what the user wants. For this reason
modify the driver so that by default it does not touch the write
protection. Only if specifically asked by the user (setting writeable=1
command line parameter) the driver tries to disable the BIOS write
protection.
this series goal is to change the spi remove callback's return value to void.
After numerous patches nearly all drivers already return 0 unconditionally.
The four first patches in this series convert the remaining three drivers to
return 0, the final patch changes the remove prototype and converts all
implementers.
Uwe Kleine-König [Sun, 23 Jan 2022 17:52:01 +0000 (18:52 +0100)]
spi: make remove callback a void function
The value returned by an spi driver's remove function is mostly ignored.
(Only an error message is printed if the value is non-zero that the
error is ignored.)
So change the prototype of the remove function to return no value. This
way driver authors are not tempted to assume that passing an error to
the upper layer is a good idea. All drivers are adapted accordingly.
There is no intended change of behaviour, all callbacks were prepared to
return 0 before.
Uwe Kleine-König [Sun, 23 Jan 2022 17:52:00 +0000 (18:52 +0100)]
platform/chrome: cros_ec: Make cros_ec_unregister() return void
Up to now cros_ec_unregister() returns zero unconditionally. Make it
return void instead which makes it easier to see in the callers that
there is no error to handle.
Also the return value of i2c, platform and spi remove callbacks is
ignored anyway.
Uwe Kleine-König [Sun, 23 Jan 2022 17:51:59 +0000 (18:51 +0100)]
tpm: st33zp24: Make st33zp24_remove() a void function
Up to now st33zp24_remove() returns zero unconditionally. Make it return
no value instead which makes it easier to see in the callers that there is
no error to handle.
Also the return value of i2c and spi remove callbacks is ignored anyway.
The two macros FBTFT_REGISTER_DRIVER and FBTFT_REGISTER_SPI_DRIVER
contain quite some duplication: Both define an spi driver and an of device
table and the differences are quite subtle.
Miaoqian Lin [Fri, 28 Jan 2022 16:59:56 +0000 (16:59 +0000)]
spi: tegra210-quad: Fix missin IRQ check in tegra_qspi_probe
This func misses checking for platform_get_irq()'s call and may passes the
negative error codes to request_threaded_irq(), which takes unsigned IRQ #,
causing it to fail with -EINVAL, overriding an original error code.
Stop calling request_threaded_irq() with invalid IRQ #s.
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