Dave Airlie [Fri, 8 Dec 2023 05:06:04 +0000 (15:06 +1000)]
Merge tag 'drm-intel-next-2023-12-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Improve display debug msgs and other general clean-ups (Ville, Rahuul)
- PSR fixes and improvements around selective fetch (Jouni, Ville)
- Remove FBC restrictions for Xe2LPD displays (Vinod)
- Skip some timing checks on BXT/GLK DSI transcoders (Ville)
- DP MST Fixes (Ville)
- Correct the input parameter on _intel_dsb_commit (heminhong)
- Fix IP version of the display WAs (Bala)
- DGFX uses direct VBT pin mapping (Clint)
- Proper handling of bool on PIPE_CONF_CHECK macros (Jani)
- Skip state verification with TBT-ALT mod (Mika Kahona)
- General organization of display code for reusage with Xe
(Jouni, Luca, Jani, Maarten)
- Squelch a sparse warning (Jani)
- Don't use "proxy" headers (Andy Shevchenko)
- Use devm_gpiod_get() for all GPIOs (Hans)
- Fix ADL+ tiled plane stride (Ville)
- Use octal permissions in display debugfs (Jani)
Luca Coelho [Fri, 1 Dec 2023 10:00:32 +0000 (12:00 +0200)]
drm/i915: handle uncore spinlock when not available
The uncore code may not always be available (e.g. when we build the
display code with Xe), so we can't always rely on having the uncore's
spinlock.
To handle this, split the spin_lock/unlock_irqsave/restore() into
spin_lock/unlock() followed by a call to local_irq_save/restore() and
create wrapper functions for locking and unlocking the uncore's
spinlock. In these functions, we have a condition check and only
actually try to lock/unlock the spinlock when I915 is defined, and
thus uncore is available.
This keeps the ifdefs contained in these new functions and all such
logic inside the display code.
Ville Syrjälä [Mon, 4 Dec 2023 20:24:43 +0000 (22:24 +0200)]
drm/i915: Fix ADL+ tiled plane stride when the POT stride is smaller than the original
plane_view_scanout_stride() currently assumes that we had to pad the
mapping stride with dummy pages in order to align it. But that is not
the case if the original fb stride exceeds the aligned stride used
to populate the remapped view, which is calculated from the user
specified framebuffer width rather than the user specified framebuffer
stride.
Ignore the original fb stride in this case and just stick to the POT
aligned stride. Getting this wrong will cause the plane to fetch the
wrong data, and can lead to fault errors if the page tables at the
bogus location aren't even populated.
TODO: figure out if this is OK for CCS, or if we should instead increase
the width of the view to cover the entire user specified fb stride
instead...
Jouni Högander [Sun, 3 Dec 2023 11:48:40 +0000 (13:48 +0200)]
drm/i915/display: Split i915 specific code away from intel_fb.c
We are preparing for Xe driver. Backing object implementation is differing
between i915 and Xe. Split i915 specific code into separate source file
built only for i915.
v9:
- Use ERR_CAST
v8:
- return original error code from intel_fb_bo_lookup_valid_bo on failure
v7:
- drop #include <drm/drm_plane.h>
- s/user_mode_cmd/mode_cmd/
- Use passed i915 pointer instead of to_i915(obj->base.dev)
v6: Add missing intel_fb_bo.[ch]
v5:
- Keep drm_any_plane_has_format check in intel_fb.c
- Use mode_cmd instead of user_mode_cmd for intel_fb_bo_lookup_valid_bo
v4: Move drm_any_plane_has_format check into intel_fb_bo.c
v3: Fix failure handling in intel_framebuffer_init
v2: Couple of fixes to error value handling
Jouni Högander [Sun, 3 Dec 2023 11:48:39 +0000 (13:48 +0200)]
drm/i915/display: Handle invalid fb_modifier in intel_fb_modifier_to_tiling
Lookup_modifier is returning INTEL_PLANE_CAP_TILING_4 on invalid
fb_modifier value. Use lookup_modifier_or_null in
intel_fb_modifier_to_tiling and return I915_TILING_NONE in case
lookup_modifier_or_null returns null.
Jouni Högander [Sun, 3 Dec 2023 11:48:37 +0000 (13:48 +0200)]
drm/i915/display: use intel_bo_to_drm_bo in intel_fb.c
We are preparing for Xe driver. I915 and Xe object implementation are
differing. Do not use i915_gem_object->base directly. Instead use
intel_bo_to_drm_bo.
Also use drm_gem_object_put instead of i915_gem_object_put. This should be
ok as i915_gem_object_put is really just doing __drm_gem_object_put.
Jouni Högander [Wed, 15 Nov 2023 09:07:19 +0000 (11:07 +0200)]
drm/i915/display: use intel_bo_to_drm_bo in intel_fbdev
We are preparing for Xe driver. I915 and Xe object implementation are
differing. Do not use i915_gem_object->base directly. Instead use
intel_bo_to_drm_bo.
Jouni Högander [Wed, 15 Nov 2023 09:07:18 +0000 (11:07 +0200)]
drm/i915/display: split i915 specific code from intel_fbdev
Split out code from intel_fbdev that can not be share between i915 and
xe. Create new i915 specific source/header file intel_fbdev_fb.[ch] which
contains this code.
Mika Kahola [Wed, 29 Nov 2023 12:22:21 +0000 (14:22 +0200)]
drm/i915/display: Skip state verification with TBT-ALT mode
With TBT-ALT mode we are not programming C20 chip PLL's and
hence we don't need to check state verification. We don't
need to program DP link signal levels i.e.pre-emphasis and
voltage swing either.
This patch fixes dmesg errors like this one
"[drm] ERROR PHY F Write 0c06 failed after 3 retries."
drm/radeon: check return value of radeon_ring_lock()
In the unlikely event of radeon_ring_lock() failing, its errno return
value should be processed. This patch checks said return value and
prints a debug message in case of an error.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: 48c0c902e2e6 ("drm/radeon/kms: add support for CP setup on SI") Signed-off-by: Nikita Zhandarovich <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
drm/radeon/r100: Fix integer overflow issues in r100_cs_track_check()
It may be possible, albeit unlikely, to encounter integer overflow
during the multiplication of several unsigned int variables, the
result being assigned to a variable 'size' of wider type.
Prevent this potential behaviour by converting one of the multiples
to unsigned long.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: 0242f74d29df ("drm/radeon: clean up CS functions in r100.c") Signed-off-by: Nikita Zhandarovich <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Lijo Lazar [Fri, 6 Oct 2023 08:19:03 +0000 (13:49 +0530)]
drm/amdgpu: Add reg_state sysfs attribute
Add reg_state attribute to fetch the register snapshot of different
IPs like XGMI, WAFL,PCIE and USR. To get a snapshot for a particular IP
1) Open the sysfs file
2) Seek to the offset as defined in amdgpu_sysfs_reg_offset
3) Read
Taimur Hassan [Fri, 10 Nov 2023 15:24:20 +0000 (10:24 -0500)]
drm/amd/display: Fix some HostVM parameters in DML
[Why]
A number of DML parameters related to HostVM were either missing or
being set incorrectly, which may cause inaccuracies in calculating
margins and determining BW limitations.
[How]
Correct these values where needed and populate the missing values.
[Why]
DTBCLK is enabled on idle and it will burn power.
[How]
There's a few issues here:
- Always enabling DTBCLK on clock manager init
- Setting refclk when DTBCLK is supposed to be disabled
- Not applying the correct calculated version refclk, but instead the
base value which might be zero
On dtbclk_en change we'll message PMFW to enable or disable the clock
accordingly.
The DTBDTO will be then based on refclk, but it will be set to the
default fixed value if there was nothing calculated in DML despite the
clock being considered enabled.
Felix Kuehling [Fri, 27 Oct 2023 22:21:55 +0000 (18:21 -0400)]
drm/amdkfd: Run restore_workers on freezable WQs
Make restore workers freezable so we don't have to explicitly flush them
in suspend and GPU reset code paths, and we don't accidentally try to
restore BOs while the GPU is suspended. Not having to flush restore_work
also helps avoid lock/fence dependencies in the GPU reset case where we're
not allowed to wait for fences.
A side effect of this is, that we can now have multiple concurrent threads
trying to signal the same eviction fence. Rework eviction fence signaling
and replacement to account for that.
The GPU reset path can no longer rely on restore_process_worker to resume
queues because evict/restore workers can run independently of it. Instead
call a new restore_process_helper directly.
When dGPU is put into BOCO it may be in D3cold but still able send
PME on display hotplug event. For this to work it must be enabled
as wake source from D3.
When runpm is enabled use pci_wake_from_d3() to mark wakeup as
enabled by default.
For 'AMDGPU_FAMILY_SI' family cards, in 'si_common_early_init' func, init
'didt_rreg' and 'didt_wreg' to 'NULL'. But in func
'amdgpu_debugfs_regs_didt_read/write', using 'RREG32_DIDT' 'WREG32_DIDT'
lacks of relevant judgment. And other 'amdgpu_ip_block_version' that use
these two definitions won't be added for 'AMDGPU_FAMILY_SI'.
Dinghao Liu [Thu, 23 Nov 2023 07:33:22 +0000 (15:33 +0800)]
drm/amd/pm: fix a memleak in aldebaran_tables_init
When kzalloc() for smu_table->ecc_table fails, we should free
the previously allocated resources to prevent memleak.
Fixes: edd794208555 ("drm/amd/pm: add message smu to get ecc_table v2") Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Alex Deucher [Fri, 10 Nov 2023 14:39:18 +0000 (09:39 -0500)]
drm/amdgpu: fix AGP addressing when GART is not at 0
This worked by luck if the GART aperture ended up at 0. When
we ended up moving GART on some chips, the GART aperture ended
up offsetting the AGP address since the resource->start is
a GART offset, not an MC address. Fix this by moving the AGP
address setup into amdgpu_bo_gpu_offset_no_check().
v2: check mem_type before checking agp
v3: check if the ttm bo has a ttm_tt allocated yet
Hamza Mahfooz [Wed, 22 Nov 2023 19:50:34 +0000 (14:50 -0500)]
drm/amd/display: fix ABM disablement
On recent versions of DMUB firmware, if we want to completely disable
ABM we have to pass ABM_LEVEL_IMMEDIATE_DISABLE as the requested ABM
level to DMUB. Otherwise, LCD eDP displays are unable to reach their
maximum brightness levels. So, to fix this whenever the user requests an
ABM level of 0 pass ABM_LEVEL_IMMEDIATE_DISABLE to DMUB instead. Also,
to keep the user's experience consistent map ABM_LEVEL_IMMEDIATE_DISABLE
to 0 when a user tries to read the requested ABM level.
Anthony Koo [Sun, 12 Nov 2023 03:47:50 +0000 (22:47 -0500)]
drm/amd/display: [FW Promotion] Release 0.0.193.0
- Add a tracing framework, to measure duration, execution count and
longest duration of main loop/vsync interrupt work
GPINT command is used to start/stop the measurements.
Taimur Hassan [Fri, 10 Nov 2023 15:15:28 +0000 (10:15 -0500)]
drm/amd/display: Fix conversions between bytes and KB
[Why]
There are a number of instances where we convert HostVMMinPageSize or
GPUVMMinPageSize from bytes to KB by dividing (rather than multiplying) and
vice versa.
Additionally, in some cases, a parameter is passed through DML in KB but
later checked as if it were in bytes.
Mukul Joshi [Wed, 22 Nov 2023 20:17:22 +0000 (15:17 -0500)]
drm/amdkfd: Use common function for IP version check
KFD_GC_VERSION was recently updated to use a new function
for IP version checks. As a result, use KFD_GC_VERSION as
the common function for all IP version checks in KFD.
[Why]
The new table doesn't have an implicit mapping between Fclk SOC voltage
and MemClk and it currently builds the table off of number of Fclk
states rather than DcfClock states.
The DML table in use is not correct for functionality or power and
does not align with our existing policies for DCN3x.
[How]
Build the table based on DcfClock with the following assumptions:
1. Raising Soc voltage is the most expensive operation, so assume that
running at max DispClock or DppClock is preferable.
2. Assume that we can run at max Fclk / MemClk at any state, but
restrict the maximum state to the very last entry in the table as the
worst case scenario.
3. Assume that Fclk always has a 2x multiplier on DcfClock unless the
table specifies something lower.
Parandhaman K [Thu, 9 Nov 2023 10:22:17 +0000 (15:52 +0530)]
drm/amd/display: Refactor OPTC into component folder
[why]
Move all optc files to unique
folder optc.
[how]
creating optc repo in dc, and moved the dcnxx_optc.c and .h files into
corresponding new folders inside the optc and cleared the linkage
errors by adding relative paths in the Makefile.template.
Alvin Lee [Thu, 9 Nov 2023 23:08:17 +0000 (18:08 -0500)]
drm/amd/display: If P-State is supported try SubVP for smaller vlevel
[Description]
- To reduce vlevel further, we can try to apply subvp on
configs that already support p-state since the natural
p-state support may not allow for DPM0.
- Add code to try subvp to reduce UCLK DPM level further
if already supported, but don't use subvp if it does not
optimize the DPM level even lower
Alvin Lee [Thu, 9 Nov 2023 15:50:30 +0000 (10:50 -0500)]
drm/amd/display: Enable SubVP on 1080p60 displays
[Description]
- Previously SubVP would never be selected on 1080p60 displays because
it has too much vactive margin. However, implement a change to allow
it like how 1440p60 is allowed.
- Add a new struct such that we have a list of allowed modes for
enabling subvp with vactive margin (currently 1080p60 and 1440p60)
- Also ensure to block drr + vblank cases to prevent unexpected
enablement of new display configs
- Update SW cursor fallback for these new potential cases as well
Wayne Lin [Mon, 7 Aug 2023 07:34:39 +0000 (15:34 +0800)]
drm/amd/display: adjust flow for deallocation mst payload
[Why]
MST relevant variables are maintained at drm side. As the result, we
still have to call drm_dp_remove_payload_part2() to update the relevant
values regardless the link is under mst mode or not. We used to have a
workaround patch to tackle this: commit 3d8fcc6740c9 ("drm/amd/display:
Extract temp drm mst deallocation wa into its own function")
Now it's time to remove the workaround and adjust the flow.
[How]
During deallocate_mst_payload(), source actually doesn't send out
ALLOCATE_PAYLOAD at the end as like the flow in allocate_mst_payload().
Call function dm_helpers_dp_mst_send_payload_allocation() at the end of
deallocate_mst_payload() is a bit confusing.
Separate dm_helpers_dp_mst_send_payload_allocation() into 2 functions.
Have a new function dm_helpers_dp_mst_update_mst_mgr_for_deallocation()
to replace dm_helpers_dp_mst_send_payload_allocation() for payload
deallocation.
[Why]
Remove the brightness cache in DC. It uses a single value to represent
the brightness for both SDR and HDR mode. This leads to flash in HDR
on/off. It also unconditionally programs brightness as in HDR mode. This
may introduce garbage on SDR mode in miniLED panel.
[How]
Simplify the initialization flow by removing the DC cache and taking
what panel has as default. Expand the mechanism for PWM to DPCD Aux to
restore cached brightness value generally.
Alvin Lee [Wed, 8 Nov 2023 22:16:28 +0000 (17:16 -0500)]
drm/amd/display: Increase num voltage states to 40
[Description]
If during driver init stage there are greater than 20
intermediary voltage states while constructing the SOC
BB we could hit issues because we will index outside of the
clock_limits array and start overwriting data. Increase the
total number of states to 40 to avoid this issue.
Alvin Lee [Tue, 7 Nov 2023 22:01:49 +0000 (17:01 -0500)]
drm/amd/display: Use DRAM speed from validation for dummy p-state
[Description]
When choosing which dummy p-state latency to use, we
need to use the DRAM speed from validation. The DRAMSpeed
DML variable can change because we use different input
params to DML when populating watermarks set B.
Wenjing Liu [Thu, 2 Nov 2023 19:02:42 +0000 (15:02 -0400)]
drm/amd/display: always use mpc factor of 2 for stereo timings
[why]
In the new pipe resource management logic, the special handling for
stereo timings is missing.
This commit implements the same stereo timings handling as old
pipe resource management code.
Perry Yuan [Tue, 1 Aug 2023 14:37:41 +0000 (10:37 -0400)]
drm/amdgpu: optimize RLC powerdown notification on Vangogh
The smu needs to get the rlc power down message to sync the rlc state
with smu, the rlc state updating message need to be sent at while smu
begin suspend sequence , otherwise SMU will crash while RLC state is not
notified by driver, and rlc state probally changed after that
notification, so it needs to notify rlc state to smu at the end of the
suspend sequence in amdgpu_device_suspend() that can make sure the rlc
state is correctly set to SMU.
[ 101.000590] amdgpu 0000:03:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x0000001E SMN_C2PMSG_82:0x00000000
[ 101.000598] amdgpu 0000:03:00.0: amdgpu: Failed to disable gfxoff!
[ 110.838026] amdgpu 0000:03:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x0000001E SMN_C2PMSG_82:0x00000000
[ 110.838035] amdgpu 0000:03:00.0: amdgpu: Failed to disable smu features.
[ 110.838039] amdgpu 0000:03:00.0: amdgpu: Fail to disable dpm features!
[ 110.838040] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend of IP block <smu> failed -62
[ 110.884394] PM: suspend of devices aborted after 21213.620 msecs
[ 110.884402] PM: start suspend of devices aborted after 21213.882 msecs
[ 110.884405] PM: Some devices failed to suspend, or early wake event detected
Wenjing Liu [Mon, 6 Nov 2023 21:47:19 +0000 (16:47 -0500)]
drm/amd/display: fix a pipe mapping error in dcn32_fpu
[why]
In dcn32 DML pipes are ordered the same as dc pipes but only for used
pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices
would be 0 and 1 respectively. However
update_pipe_slice_table_with_split_flags doesn't skip indices for free
pipes. This causes us to not reference correct dml pipe output when
building pipe topology.
[how]
Use two variables to iterate dc and dml pipes respectively and only
increment dml pipe index when current dc pipe is not free.
drm/amd/display: Add z-state support policy for dcn35
[Why]
DML2 means that the dcn3x policy for calculating z-state support
no longer runs from validate_bandwidth.
This means we are unconditionally allowing Z8, the hardware default.
[How]
Port the policy over to DCN35, but with a few modifications:
- Don't use min_dst_y_next_start as a check for Z8/Z10 allow
- Add support for overriding the Z10 stutter period per ASIC
- Cleanup the code to make the policy assignment more clear
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