From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sat, 16 Mar 2024 18:24:51 +0000 (-0700)
Subject: Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
X-Git-Tag: v6.9-rc1~82
X-Git-Url: https://repo.jachan.dev/linux.git/commitdiff_plain/90a498f294c2766f05ba72dbc0ecafb2af521a4c

Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
 "New hardware support:

   - Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS
     PHY and SDM630 USBC support

   - Rockchip HDMI/eDP Combo PHY driver

   - Mediatek MT8365 CSI phy driver

  Updates:

   - Rework on Qualcomm phy PCS registers and type-c handling

   - Cadence torrent phy updates for multilink configuration

   - TI gmii resume support"

* tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
  phy: constify of_phandle_args in xlate
  phy: ti: tusb1210: Define device IDs
  phy: ti: tusb1210: Use temporary variable for struct device
  phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver
  dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
  phy: ti: gmii-sel: add resume support
  phy: mtk-mipi-csi: add driver for CSI phy
  dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
  phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200
  dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
  phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration
  phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration
  dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
  phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API
  dt-bindings: phy: qmp-ufs: Fix PHY clocks
  phy: qcom: sgmii-eth: move PCS registers to separate header
  phy: qcom: sgmii-eth: use existing register definitions
  phy: qcom: qmp-usbc: drop has_pwrdn_delay handling
  phy: qcom: qmp: move common bits definitions to common header
  phy: qcom: qmp: split DP PHY registers to separate headers
  ...
---

90a498f294c2766f05ba72dbc0ecafb2af521a4c
diff --cc drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 5c003988c35d,6b6994cb77d7..85253936fac3
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@@ -1621,27 -1328,7 +1336,23 @@@ static const struct qmp_usb_offsets qmp
  	.rx		= 0x1000,
  };
  
 +static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
- 	.lanes			= 1,
- 
 +	.offsets		= &qmp_usb_offsets_v3,
 +
 +	.serdes_tbl		= ipq9574_usb3_serdes_tbl,
 +	.serdes_tbl_num		= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
 +	.tx_tbl			= msm8996_usb3_tx_tbl,
 +	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
 +	.rx_tbl			= ipq8074_usb3_rx_tbl,
 +	.rx_tbl_num		= ARRAY_SIZE(ipq8074_usb3_rx_tbl),
 +	.pcs_tbl		= ipq8074_usb3_pcs_tbl,
 +	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
 +	.vreg_list		= qmp_phy_vreg_l,
 +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
 +	.regs			= qmp_v3_usb3phy_regs_layout,
 +};
 +
  static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
- 	.lanes			= 1,
- 
  	.offsets		= &qmp_usb_offsets_v3,
  
  	.serdes_tbl		= ipq8074_usb3_serdes_tbl,
@@@ -1676,9 -1361,7 +1385,7 @@@ static const struct qmp_phy_cfg ipq9574
  };
  
  static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
- 	.lanes			= 1,
- 
 -	.offsets		= &qmp_usb_offsets_v3,
 +	.offsets		= &qmp_usb_offsets_v3_msm8996,
  
  	.serdes_tbl		= msm8996_usb3_serdes_tbl,
  	.serdes_tbl_num		= ARRAY_SIZE(msm8996_usb3_serdes_tbl),