From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Mon, 28 Oct 2013 00:43:41 +0000 (+0000)
Subject: Merge branch 'baserock/bjdooks/312-rc4/be/core-v3' of git://git.baserock.org/delta... 
X-Git-Tag: v3.13-rc1~103^2~1^2~2
X-Git-Url: https://repo.jachan.dev/linux.git/commitdiff_plain/2098990e7c558c175b96213d41058983e00a7919

Merge branch 'baserock/bjdooks/312-rc4/be/core-v3' of git://git.baserock.org/delta/linux into devel-stable

Conflicts:
	arch/arm/kernel/head.S

This series has been well tested and it would be great to get this
merged now.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---

2098990e7c558c175b96213d41058983e00a7919
diff --cc arch/arm/include/asm/atomic.h
index 55ffc3b850f4,6447a0b7b127..134aa28b6f64
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@@ -304,11 -299,10 +304,11 @@@ static inline void atomic64_add(u64 i, 
  	u64 result;
  	unsigned long tmp;
  
 +	prefetchw(&v->counter);
  	__asm__ __volatile__("@ atomic64_add\n"
  "1:	ldrexd	%0, %H0, [%3]\n"
- "	adds	%0, %0, %4\n"
- "	adc	%H0, %H0, %H4\n"
+ "	adds	%Q0, %Q0, %Q4\n"
+ "	adc	%R0, %R0, %R4\n"
  "	strexd	%1, %0, %H0, [%3]\n"
  "	teq	%1, #0\n"
  "	bne	1b"
@@@ -345,11 -339,10 +345,11 @@@ static inline void atomic64_sub(u64 i, 
  	u64 result;
  	unsigned long tmp;
  
 +	prefetchw(&v->counter);
  	__asm__ __volatile__("@ atomic64_sub\n"
  "1:	ldrexd	%0, %H0, [%3]\n"
- "	subs	%0, %0, %4\n"
- "	sbc	%H0, %H0, %H4\n"
+ "	subs	%Q0, %Q0, %Q4\n"
+ "	sbc	%R0, %R0, %R4\n"
  "	strexd	%1, %0, %H0, [%3]\n"
  "	teq	%1, #0\n"
  "	bne	1b"
diff --cc arch/arm/kernel/head.S
index 32402ba6710a,a047acfa6b6d..e46330f4506a
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@@ -602,28 -586,26 +606,42 @@@ __fixup_a_pv_table
  	b	2f
  1:	add     r7, r3
  	ldrh	ip, [r7, #2]
+ ARM_BE8(rev16	ip, ip)
 -	and	ip, 0x8f00
 -	orr	ip, r6	@ mask in offset bits 31-24
 +	tst	ip, #0x4000
 +	and	ip, #0x8f00
 +	orrne	ip, r6	@ mask in offset bits 31-24
 +	orreq	ip, r0	@ mask in offset bits 7-0
+ ARM_BE8(rev16	ip, ip)
  	strh	ip, [r7, #2]
- 	ldrheq	ip, [r7]
- 	biceq	ip, #0x20
- 	orreq	ip, ip, r0, lsr #16
- 	strheq	ip, [r7]
++	bne	2f
++	ldrh	ip, [r7]
++ARM_BE8(rev16	ip, ip)
++	bic	ip, #0x20
++	orr	ip, ip, r0, lsr #16
++ARM_BE8(rev16	ip, ip)
++	strh	ip, [r7]
  2:	cmp	r4, r5
  	ldrcc	r7, [r4], #4	@ use branch for delay slot
  	bcc	1b
  	bx	lr
  #else
 +	moveq	r0, #0x400000	@ set bit 22, mov to mvn instruction
  	b	2f
  1:	ldr	ip, [r7, r3]
+ #ifdef CONFIG_CPU_ENDIAN_BE8
+ 	@ in BE8, we load data in BE, but instructions still in LE
+ 	bic	ip, ip, #0xff000000
 -	orr	ip, ip, r6, lsl#24
++	tst	ip, #0x000f0000	@ check the rotation field
++	orrne	ip, ip, r6, lsl #24 @ mask in offset bits 31-24
++	biceq	ip, ip, #0x00004000 @ clear bit 22
++	orreq	ip, ip, r0, lsl #24 @ mask in offset bits 7-0
+ #else
  	bic	ip, ip, #0x000000ff
 -	orr	ip, ip, r6	@ mask in offset bits 31-24
 +	tst	ip, #0xf00	@ check the rotation field
 +	orrne	ip, ip, r6	@ mask in offset bits 31-24
 +	biceq	ip, ip, #0x400000	@ clear bit 22
 +	orreq	ip, ip, r0	@ mask in offset bits 7-0
+ #endif
  	str	ip, [r7, r3]
  2:	cmp	r4, r5
  	ldrcc	r7, [r4], #4	@ use branch for delay slot