m68k: Fix misspellings in comments.

Signed-off-by: Adam Buchbinder <[email protected]>
Acked-by: Greg Ungerer <[email protected]> [nommu, coldfire]
Signed-off-by: Geert Uytterhoeven <[email protected]>

diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h
index 4ebf098b8a1fd58c9a222d864b9f4cea6f6c2171..1a8080c4cc402a9922ee873474c3c0010cf59655 100644 (file)
--- a/arch/m68k/include/asm/MC68328.h
+++ b/arch/m68k/include/asm/MC68328.h
@@ -798,7 +798,7 @@
 
 /**********
  *
 
 /**********
  *

- * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
+ * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)

  *
  **********/
 
  *
  **********/
 


@@ -824,7 +824,7 @@
 
 /**********
  *
 
 /**********
  *

- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)

  *
  **********/
 
  *
  **********/
 


@@ -904,7 +904,7 @@
 
 #define UBAUD_PRESCALER_MASK   0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT  0
 
 #define UBAUD_PRESCALER_MASK   0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT  0

-#define UBAUD_DIVIDE_MASK      0x0700  /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_MASK      0x0700  /* Baud Rate freq. divisor */

 #define UBAUD_DIVIDE_SHIFT     8
 #define UBAUD_BAUD_SRC         0x0800  /* Baud Rate Source */
 #define UBAUD_GPIOSRC          0x1000  /* GPIO source */
 #define UBAUD_DIVIDE_SHIFT     8
 #define UBAUD_BAUD_SRC         0x0800  /* Baud Rate Source */
 #define UBAUD_GPIOSRC          0x1000  /* GPIO source */

diff --git a/arch/m68k/include/asm/MC68EZ328.h b/arch/m68k/include/asm/MC68EZ328.h
index d1bde58ab0ddbd63e75508cbcb691d11c925c222..fedac87c5d130858ad929118229b4680f588e568 100644 (file)
--- a/arch/m68k/include/asm/MC68EZ328.h
+++ b/arch/m68k/include/asm/MC68EZ328.h
@@ -631,7 +631,7 @@
 
 /**********
  *
 
 /**********
  *

- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)

  *
  **********/
 
  *
  **********/
 


@@ -712,7 +712,7 @@
 
 #define UBAUD_PRESCALER_MASK   0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT  0
 
 #define UBAUD_PRESCALER_MASK   0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT  0

-#define UBAUD_DIVIDE_MASK      0x0700  /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_MASK      0x0700  /* Baud Rate freq. divisor */

 #define UBAUD_DIVIDE_SHIFT     8
 #define UBAUD_BAUD_SRC         0x0800  /* Baud Rate Source */
 #define UBAUD_UCLKDIR          0x2000  /* UCLK Direction */
 #define UBAUD_DIVIDE_SHIFT     8
 #define UBAUD_BAUD_SRC         0x0800  /* Baud Rate Source */
 #define UBAUD_UCLKDIR          0x2000  /* UCLK Direction */


@@ -1160,7 +1160,7 @@ typedef volatile struct {
 #define DRAMMC_COL10           0x0080  /* Col address bit for MD10 PA11/PA0  */
 #define DRAMMC_COL9            0x0040  /* Col address bit for MD9  PA10/PA0  */
 #define DRAMMC_COL8            0x0020  /* Col address bit for MD8  PA9/PA0   */
 #define DRAMMC_COL10           0x0080  /* Col address bit for MD10 PA11/PA0  */
 #define DRAMMC_COL9            0x0040  /* Col address bit for MD9  PA10/PA0  */
 #define DRAMMC_COL8            0x0020  /* Col address bit for MD8  PA9/PA0   */

-#define DRAMMC_REF_MASK                0x001f  /* Reresh Cycle */
+#define DRAMMC_REF_MASK                0x001f  /* Refresh Cycle */

 #define DRAMMC_REF_SHIFT       0
 
 /*
 #define DRAMMC_REF_SHIFT       0
 
 /*

diff --git a/arch/m68k/include/asm/MC68VZ328.h b/arch/m68k/include/asm/MC68VZ328.h
index 6bd1bf1f85ea23de0338e554a4609047b2db78aa..34a51b2c784fb96e74924947df9bbeef426ef2fb 100644 (file)
--- a/arch/m68k/include/asm/MC68VZ328.h
+++ b/arch/m68k/include/asm/MC68VZ328.h
@@ -724,7 +724,7 @@
 
 /**********
  *
 
 /**********
  *

- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)

  *
  **********/
 
  *
  **********/
 


@@ -806,7 +806,7 @@
 
 #define UBAUD_PRESCALER_MASK   0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT  0
 
 #define UBAUD_PRESCALER_MASK   0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT  0

-#define UBAUD_DIVIDE_MASK      0x0700  /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_MASK      0x0700  /* Baud Rate freq. divisor */

 #define UBAUD_DIVIDE_SHIFT     8
 #define UBAUD_BAUD_SRC         0x0800  /* Baud Rate Source */
 #define UBAUD_UCLKDIR          0x2000  /* UCLK Direction */
 #define UBAUD_DIVIDE_SHIFT     8
 #define UBAUD_BAUD_SRC         0x0800  /* Baud Rate Source */
 #define UBAUD_UCLKDIR          0x2000  /* UCLK Direction */


@@ -1256,7 +1256,7 @@ typedef struct {
 #define DRAMMC_COL10           0x0080  /* Col address bit for MD10 PA11/PA0  */
 #define DRAMMC_COL9            0x0040  /* Col address bit for MD9  PA10/PA0  */
 #define DRAMMC_COL8            0x0020  /* Col address bit for MD8  PA9/PA0   */
 #define DRAMMC_COL10           0x0080  /* Col address bit for MD10 PA11/PA0  */
 #define DRAMMC_COL9            0x0040  /* Col address bit for MD9  PA10/PA0  */
 #define DRAMMC_COL8            0x0020  /* Col address bit for MD8  PA9/PA0   */

-#define DRAMMC_REF_MASK                0x001f  /* Reresh Cycle */
+#define DRAMMC_REF_MASK                0x001f  /* Refresh Cycle */

 #define DRAMMC_REF_SHIFT       0
 
 /*
 #define DRAMMC_REF_SHIFT       0
 
 /*

diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 6d13cae44af530240b99b83e4248288ee939ae69..59e171063c2f1f846dcac7c4fc07eab2b26093fc 100644 (file)
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -23,8 +23,8 @@
 #define CACR_IEC       0x00008000      /* Enable instruction cache */
 #define CACR_DNFB      0x00002000      /* Inhibited fill buffer */
 #define CACR_IDPI      0x00001000      /* Disable CPUSHL */
 #define CACR_IEC       0x00008000      /* Enable instruction cache */
 #define CACR_DNFB      0x00002000      /* Inhibited fill buffer */
 #define CACR_IDPI      0x00001000      /* Disable CPUSHL */

-#define CACR_IHLCK     0x00000800      /* Intruction cache half lock */
-#define CACR_IDCM      0x00000400      /* Intruction cache inhibit */
+#define CACR_IHLCK     0x00000800      /* Instruction cache half lock */
+#define CACR_IDCM      0x00000400      /* Instruction cache inhibit */

 #define CACR_ICINVA    0x00000100      /* Invalidate instr cache */
 #define CACR_EUSP      0x00000020      /* Enable separate user a7 */
 
 #define CACR_ICINVA    0x00000100      /* Invalidate instr cache */
 #define CACR_EUSP      0x00000020      /* Enable separate user a7 */
 

diff --git a/arch/m68k/include/asm/mac_iop.h b/arch/m68k/include/asm/mac_iop.h
index fde874a01e20fe001f78d5f4f5e440786f614d48..42566fd052bc0e091a4143f9fbd168c40752985c 100644 (file)
--- a/arch/m68k/include/asm/mac_iop.h
+++ b/arch/m68k/include/asm/mac_iop.h
@@ -48,7 +48,7 @@
 
 /* IOP message status codes */
 
 
 /* IOP message status codes */
 

-#define IOP_MSGSTATUS_UNUSED   0       /* Unusued message structure       */
+#define IOP_MSGSTATUS_UNUSED   0       /* Unused message structure        */

 #define IOP_MSGSTATUS_WAITING  1       /* waiting for channel             */
 #define IOP_MSGSTATUS_SENT     2       /* message sent, awaiting reply    */
 #define IOP_MSGSTATUS_COMPLETE 3       /* message complete and reply rcvd */
 #define IOP_MSGSTATUS_WAITING  1       /* waiting for channel             */
 #define IOP_MSGSTATUS_SENT     2       /* message sent, awaiting reply    */
 #define IOP_MSGSTATUS_COMPLETE 3       /* message complete and reply rcvd */

diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 089f0f150bbfc06169a720e2ddb9b9d3d563658c..1150e42c3f19db6c3241bee5156a60cdde79b434 100644 (file)
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -51,7 +51,7 @@
  *     Bit definitions for the Timer Event Registers (TER).
  */
 #define        MCFTIMER_TER_CAP        0x01            /* Capture event */
  *     Bit definitions for the Timer Event Registers (TER).
  */
 #define        MCFTIMER_TER_CAP        0x01            /* Capture event */

-#define        MCFTIMER_TER_REF        0x02            /* Refernece event */
+#define        MCFTIMER_TER_REF        0x02            /* Reference event */

 
 /****************************************************************************/
 #endif /* mcftimer_h */
 
 /****************************************************************************/
 #endif /* mcftimer_h */

diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c
index ce56e04386e707350568fd5850a4f44259f033b0..920ff63d4a81d77af96849d3e7c7f802da8be4a7 100644 (file)
--- a/arch/m68k/mac/via.c
+++ b/arch/m68k/mac/via.c
@@ -68,7 +68,7 @@ static int gIER,gIFR,gBufA,gBufB;
  * interrupt. This limitation also seems to apply to VIA clone logic cores in
  * Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)
  *
  * interrupt. This limitation also seems to apply to VIA clone logic cores in
  * Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)
  *

- * We used to fake it by configuring the relevent VIA pin as an output
+ * We used to fake it by configuring the relevant VIA pin as an output

  * (to mask the interrupt) or input (to unmask). That scheme did not work on
  * (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector
  * circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,
  * (to mask the interrupt) or input (to unmask). That scheme did not work on
  * (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector
  * circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,