]> Git Repo - linux.git/commit
drm/i915/xe3lpd: Update pmdemand programming
authorMatt Roper <[email protected]>
Mon, 28 Oct 2024 19:30:07 +0000 (12:30 -0700)
committerMatt Roper <[email protected]>
Tue, 29 Oct 2024 14:36:34 +0000 (07:36 -0700)
commitae03d70748c745d8b7d2a960f0ff49218639a9b2
tree9c791c38e1fc758047214a07a9ee5290911f28ea
parent493454445c9531051bd27a0305a61953780bd453
drm/i915/xe3lpd: Update pmdemand programming

There are some minor changes to pmdemand handling on Xe3:
 - Active scalers are no longer tracked.  We can simply skip the readout
   and programming of this field.
 - Active dbuf slices are no longer tracked.  We should skip the readout
   and programming of this field and also make sure that it stays 0 in
   our software bookkeeping so that we won't erroneously return true
   from intel_pmdemand_needs_update() due to mismatches.
 - Even though there aren't enough pipes to utilize them, the size of
   the 'active pipes' field has expanded to four bits, taking over the
   register bits previously used for dbuf slices.  Since the lower bits
   of the mask have moved, we need to update our reads/writes to handle
   this properly.

v2: active pipes is no longer always max 3, add in the ability to go to
4 for PTL.
v3: use intel_display for display_ver check, use INTEL_NUM_PIPES
v4: add a conditional for number of pipes macro vs using 3.
v5: reverse conditional order of v4.
v6: undo v5 and fix num_pipes assignment
v7: pass display struct instead of i915, checkpatch fix
v8: Alignment issue

Bspec: 68883, 69125
Signed-off-by: Matt Roper <[email protected]>
Signed-off-by: Matt Atwood <[email protected]>
Signed-off-by: Clint Taylor <[email protected]>
Reviewed-by: Vinod Govindapillai <[email protected]>
Reviewed-by: Gustavo Sousa <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
drivers/gpu/drm/i915/display/intel_pmdemand.c
drivers/gpu/drm/i915/display/intel_pmdemand.h
drivers/gpu/drm/i915/i915_reg.h
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