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clk: sunxi: mod1 clock support
authorEmilio López <[email protected]>
Fri, 18 Jul 2014 18:28:02 +0000 (15:28 -0300)
committerMaxime Ripard <[email protected]>
Wed, 21 Oct 2015 19:51:29 +0000 (21:51 +0200)
commit9b038bc58ad2658c76fd8b50bb333dfd4454573c
tree00ea3d70e94441ae7b7a0fd43b1f4c2e083d651atree | snapshot
parente2771545f49fbfec874642533058a3423fa29e16commit | diff
clk: sunxi: mod1 clock support

The module 1 type of clocks consist of a gate and a mux and are used on
the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
SPDIF. This commit adds support for them on the sunxi clock driver.

Signed-off-by: Emilio López <[email protected]>
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
drivers/clk/sunxi/Makefile diff | blob | blame | history
drivers/clk/sunxi/clk-a10-mod1.c [new file with mode: 0644] blob
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