Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gfx.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 6098b8b1ae5b1fab3f174de414651b7c9305a18a..a33d4bc34cee746cdee7e70103190fee0aa9f2cd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -448,8 +448,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 
                        ring->mqd_size = mqd_size;
                        /* prepare MQD backup */
-                       adev->gfx.mec.mqd_backup[j + xcc_id * adev->gfx.num_compute_rings] = kmalloc(mqd_size, GFP_KERNEL);
-                       if (!adev->gfx.mec.mqd_backup[j + xcc_id * adev->gfx.num_compute_rings])
+                       adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);
+                       if (!adev->gfx.mec.mqd_backup[j])
                                dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
                }
        }
@@ -509,7 +509,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                j = i + xcc_id * adev->gfx.num_compute_rings;
                kiq->pmf->kiq_unmap_queues(kiq_ring,
-                                          &adev->gfx.compute_ring[i],
+                                          &adev->gfx.compute_ring[j],
                                           RESET_QUEUES, 0, 0);
        }
 
@@ -541,7 +541,7 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        j = i + xcc_id * adev->gfx.num_gfx_rings;
                        kiq->pmf->kiq_unmap_queues(kiq_ring,
-                                                  &adev->gfx.gfx_ring[i],
+                                                  &adev->gfx.gfx_ring[j],
                                                   PREEMPT_QUEUES, 0, 0);
                }
        }
@@ -593,6 +593,8 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 
        DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
                                                        kiq_ring->queue);
+       amdgpu_device_flush_hdp(adev, NULL);
+
        spin_lock(&kiq->ring_lock);
        r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
                                        adev->gfx.num_compute_rings +
@@ -630,6 +632,8 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
        if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
                return -EINVAL;
 
+       amdgpu_device_flush_hdp(adev, NULL);
+
        spin_lock(&kiq->ring_lock);
        /* No need to map kcq on the slave */
        if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
@@ -644,7 +648,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        j = i + xcc_id * adev->gfx.num_gfx_rings;
                        kiq->pmf->kiq_map_queues(kiq_ring,
-                                                &adev->gfx.gfx_ring[i]);
+                                                &adev->gfx.gfx_ring[j]);
                }
        }
 
@@ -884,6 +888,25 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
        return 0;
 }
 
+void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
+               void *ras_error_status,
+               void (*func)(struct amdgpu_device *adev, void *ras_error_status,
+                               int xcc_id))
+{
+       int i;
+       int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
+       uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);
+       struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+
+       if (err_data) {
+               err_data->ue_count = 0;
+               err_data->ce_count = 0;
+       }
+
+       for_each_inst(i, xcc_mask)
+               func(adev, ras_error_status, i);
+}
+
 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 {
        signed long r, cnt = 0;