Merge tag 'samsung-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a78a206e176ecdc8a2c96262c1d823cc3417b8f3..1e14531353e05ec7aadd69ea9d6e019310a25682 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -200,19 +200,29 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
  */
 void amdgpu_vm_flush(struct amdgpu_ring *ring,
                     struct amdgpu_vm *vm,
-                    struct amdgpu_fence *updates)
+                    struct fence *updates)
 {
        uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
        struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
-       struct amdgpu_fence *flushed_updates = vm_id->flushed_updates;
+       struct fence *flushed_updates = vm_id->flushed_updates;
+       bool is_earlier = false;
+
+       if (flushed_updates && updates) {
+               BUG_ON(flushed_updates->context != updates->context);
+               is_earlier = (updates->seqno - flushed_updates->seqno <=
+                             INT_MAX) ? true : false;
+       }
 
        if (pd_addr != vm_id->pd_gpu_addr || !flushed_updates ||
-           (updates && amdgpu_fence_is_earlier(flushed_updates, updates))) {
+           is_earlier) {
 
                trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
-               vm_id->flushed_updates = amdgpu_fence_ref(
-                       amdgpu_fence_later(flushed_updates, updates));
-               amdgpu_fence_unref(&flushed_updates);
+               if (is_earlier) {
+                       vm_id->flushed_updates = fence_get(updates);
+                       fence_put(flushed_updates);
+               }
+               if (!flushed_updates)
+                       vm_id->flushed_updates = fence_get(updates);
                vm_id->pd_gpu_addr = pd_addr;
                amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
        }
@@ -306,13 +316,12 @@ static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
        }
 }
 
-static int amdgpu_vm_free_job(
-       struct amdgpu_cs_parser *sched_job)
+int amdgpu_vm_free_job(struct amdgpu_job *job)
 {
        int i;
-       for (i = 0; i < sched_job->num_ibs; i++)
-               amdgpu_ib_free(sched_job->adev, &sched_job->ibs[i]);
-       kfree(sched_job->ibs);
+       for (i = 0; i < job->num_ibs; i++)
+               amdgpu_ib_free(job->adev, &job->ibs[i]);
+       kfree(job->ibs);
        return 0;
 }
 
@@ -618,9 +627,14 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 {
        uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
        uint64_t last_pte = ~0, last_dst = ~0;
+       void *owner = AMDGPU_FENCE_OWNER_VM;
        unsigned count = 0;
        uint64_t addr;
 
+       /* sync to everything on unmapping */
+       if (!(flags & AMDGPU_PTE_VALID))
+               owner = AMDGPU_FENCE_OWNER_UNDEFINED;
+
        /* walk over the address space and update the page tables */
        for (addr = start; addr < end; ) {
                uint64_t pt_idx = addr >> amdgpu_vm_block_size;
@@ -629,8 +643,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
                uint64_t pte;
                int r;
 
-               amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv,
-                                AMDGPU_FENCE_OWNER_VM);
+               amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner);
                r = reservation_object_reserve_shared(pt->tbo.resv);
                if (r)
                        return r;
@@ -672,31 +685,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
        return 0;
 }
 
-/**
- * amdgpu_vm_fence_pts - fence page tables after an update
- *
- * @vm: requested vm
- * @start: start of GPU address range
- * @end: end of GPU address range
- * @fence: fence to use
- *
- * Fence the page tables in the range @start - @end (cayman+).
- *
- * Global and local mutex must be locked!
- */
-static void amdgpu_vm_fence_pts(struct amdgpu_vm *vm,
-                               uint64_t start, uint64_t end,
-                               struct fence *fence)
-{
-       unsigned i;
-
-       start >>= amdgpu_vm_block_size;
-       end >>= amdgpu_vm_block_size;
-
-       for (i = start; i <= end; ++i)
-               amdgpu_bo_fence(vm->page_tables[i].bo, fence, true);
-}
-
 /**
  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
  *
@@ -781,17 +769,6 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
        ib->length_dw = 0;
 
-       if (!(flags & AMDGPU_PTE_VALID)) {
-               unsigned i;
-
-               for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-                       struct amdgpu_fence *f = vm->ids[i].last_id_use;
-                       r = amdgpu_sync_fence(adev, &ib->sync, &f->base);
-                       if (r)
-                               return r;
-               }
-       }
-
        r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
                                  mapping->it.last + 1, addr + mapping->offset,
                                  flags, gtt_flags);
@@ -811,8 +788,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
        if (r)
                goto error_free;
 
-       amdgpu_vm_fence_pts(vm, mapping->it.start,
-                           mapping->it.last + 1, f);
+       amdgpu_bo_fence(vm->page_directory, f, true);
        if (fence) {
                fence_put(*fence);
                *fence = fence_get(f);
@@ -853,7 +829,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        int r;
 
        if (mem) {
-               addr = mem->start << PAGE_SHIFT;
+               addr = (u64)mem->start << PAGE_SHIFT;
                if (mem->mem_type != TTM_PL_TT)
                        addr += adev->vm_manager.vram_base_offset;
        } else {
@@ -1087,6 +1063,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 
        /* walk over the address space and allocate the page tables */
        for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
+               struct reservation_object *resv = vm->page_directory->tbo.resv;
                struct amdgpu_bo *pt;
 
                if (vm->page_tables[pt_idx].bo)
@@ -1095,9 +1072,13 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
                /* drop mutex to allocate and clear page table */
                mutex_unlock(&vm->mutex);
 
+               ww_mutex_lock(&resv->lock, NULL);
                r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
                                     AMDGPU_GPU_PAGE_SIZE, true,
-                                    AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &pt);
+                                    AMDGPU_GEM_DOMAIN_VRAM,
+                                    AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
+                                    NULL, resv, &pt);
+               ww_mutex_unlock(&resv->lock);
                if (r)
                        goto error_free;
 
@@ -1297,8 +1278,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
        vm->page_directory_fence = NULL;
 
        r = amdgpu_bo_create(adev, pd_size, align, true,
-                            AMDGPU_GEM_DOMAIN_VRAM, 0,
-                            NULL, &vm->page_directory);
+                            AMDGPU_GEM_DOMAIN_VRAM,
+                            AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
+                            NULL, NULL, &vm->page_directory);
        if (r)
                return r;
 
@@ -1347,7 +1329,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
        fence_put(vm->page_directory_fence);
 
        for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-               amdgpu_fence_unref(&vm->ids[i].flushed_updates);
+               fence_put(vm->ids[i].flushed_updates);
                amdgpu_fence_unref(&vm->ids[i].last_id_use);
        }