Merge tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_atomfirmware.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 0b7f4c4d58e58828d48f5a1435fb99b263e5cf35..fb2681dd6b338c222eaa0431cce61f940ad239b2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -58,7 +58,7 @@ uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *ade
        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
                                index, &size, &frev, &crev, &data_offset)) {
                /* support firmware_info 3.1 + */
-               if ((frev == 3 && crev >=1) || (frev > 3)) {
+               if ((frev == 3 && crev >= 1) || (frev > 3)) {
                        firmware_info = (union firmware_info *)
                                (mode_info->atom_context->bios + data_offset);
                        fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
@@ -217,6 +217,7 @@ union umc_info {
        struct atom_umc_info_v3_1 v31;
        struct atom_umc_info_v3_2 v32;
        struct atom_umc_info_v3_3 v33;
+       struct atom_umc_info_v4_0 v40;
 };
 
 union vram_info {
@@ -508,9 +509,8 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 
        if (amdgpu_atom_parse_data_header(mode_info->atom_context,
                                index, &size, &frev, &crev, &data_offset)) {
+               umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
                if (frev == 3) {
-                       umc_info = (union umc_info *)
-                               (mode_info->atom_context->bios + data_offset);
                        switch (crev) {
                        case 1:
                                umc_config = le32_to_cpu(umc_info->v31.umc_config);
@@ -533,6 +533,20 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
                                /* unsupported crev */
                                return false;
                        }
+               } else if (frev == 4) {
+                       switch (crev) {
+                       case 0:
+                               umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
+                               ecc_default_enabled =
+                                       (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
+                               break;
+                       default:
+                               /* unsupported crev */
+                               return false;
+                       }
+               } else {
+                       /* unsupported frev */
+                       return false;
                }
        }
 
@@ -597,7 +611,7 @@ bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
                                          index, &size, &frev, &crev,
                                          &data_offset)) {
                /* support firmware_info 3.4 + */
-               if ((frev == 3 && crev >=4) || (frev > 3)) {
+               if ((frev == 3 && crev >= 4) || (frev > 3)) {
                        firmware_info = (union firmware_info *)
                                (mode_info->atom_context->bios + data_offset);
                        /* The ras_rom_i2c_slave_addr should ideally
@@ -850,7 +864,7 @@ int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 
        firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 
-       if (frev !=3)
+       if (frev != 3)
                return -EINVAL;
 
        switch (crev) {
@@ -909,7 +923,7 @@ int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
        }
 
        index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
-                                            asic_init);
+                                       asic_init);
        if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
                if (frev == 2 && crev >= 1) {
                        memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));