crypto: akcipher - Drop sign/verify operations

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_doorbell.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index f637574644c0ee16955365dc59cb4f6d4c82264f..2675689ef70f733f8f882f73f289ac062e52396c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -31,10 +31,15 @@ struct amdgpu_doorbell {
        /* doorbell mmio */
        resource_size_t         base;
        resource_size_t         size;
-       u32 __iomem             *ptr;
 
        /* Number of doorbells reserved for amdgpu kernel driver */
        u32 num_kernel_doorbells;
+
+       /* Kernel doorbells */
+       struct amdgpu_bo *kernel_doorbells;
+
+       /* For CPU access of doorbells */
+       uint32_t *cpu_addr;
 };
 
 /* Reserved doorbells for amdgpu (including multimedia).
@@ -81,6 +86,7 @@ struct amdgpu_doorbell_index {
                        uint32_t vce_ring6_7;
                } uvd_vce;
        };
+       uint32_t vpe_ring;
        uint32_t first_non_cp;
        uint32_t last_non_cp;
        uint32_t max_assignment;
@@ -90,8 +96,7 @@ struct amdgpu_doorbell_index {
        uint32_t xcc_doorbell_range;
 };
 
-typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
-{
+enum AMDGPU_DOORBELL_ASSIGNMENT {
        AMDGPU_DOORBELL_KIQ                     = 0x000,
        AMDGPU_DOORBELL_HIQ                     = 0x001,
        AMDGPU_DOORBELL_DIQ                     = 0x002,
@@ -109,10 +114,10 @@ typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
        AMDGPU_DOORBELL_IH                      = 0x1E8,
        AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
        AMDGPU_DOORBELL_INVALID                 = 0xFFFF
-} AMDGPU_DOORBELL_ASSIGNMENT;
+};
+
+enum AMDGPU_VEGA20_DOORBELL_ASSIGNMENT {
 
-typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
-{
        /* Compute + GFX: 0~255 */
        AMDGPU_VEGA20_DOORBELL_KIQ                     = 0x000,
        AMDGPU_VEGA20_DOORBELL_HIQ                     = 0x001,
@@ -176,10 +181,10 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
 
        AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x1F7,
        AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF
-} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
+};
+
+enum AMDGPU_NAVI10_DOORBELL_ASSIGNMENT {
 
-typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
-{
        /* Compute + GFX: 0~255 */
        AMDGPU_NAVI10_DOORBELL_KIQ                      = 0x000,
        AMDGPU_NAVI10_DOORBELL_HIQ                      = 0x001,
@@ -222,18 +227,19 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
        AMDGPU_NAVI10_DOORBELL64_VCNc_d                 = 0x18E,
        AMDGPU_NAVI10_DOORBELL64_VCNe_f                 = 0x18F,
 
+       AMDGPU_NAVI10_DOORBELL64_VPE                    = 0x190,
+
        AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP           = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
-       AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP            = AMDGPU_NAVI10_DOORBELL64_VCNe_f,
+       AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP            = AMDGPU_NAVI10_DOORBELL64_VPE,
 
-       AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT           = 0x18F,
+       AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT           = AMDGPU_NAVI10_DOORBELL64_VPE,
        AMDGPU_NAVI10_DOORBELL_INVALID                  = 0xFFFF
-} AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
+};
 
 /*
  * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
  */
-typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
-{
+enum AMDGPU_DOORBELL64_ASSIGNMENT {
        /*
         * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
         * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
@@ -309,9 +315,10 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
 
        AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
        AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
-} AMDGPU_DOORBELL64_ASSIGNMENT;
+};
+
+enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 {
 
-typedef enum _AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 {
        /* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */
 
        /* KIQ/HIQ/DIQ */
@@ -330,22 +337,33 @@ typedef enum _AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 {
        AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END         = 0x19F,
        /* IH: 0x1A0 ~ 0x1AF */
        AMDGPU_DOORBELL_LAYOUT1_IH                      = 0x1A0,
-       /* VCN: 0x1B0 ~ 0x1D4 */
+       /* VCN: 0x1B0 ~ 0x1E8 */
        AMDGPU_DOORBELL_LAYOUT1_VCN_START               = 0x1B0,
-       AMDGPU_DOORBELL_LAYOUT1_VCN_END                 = 0x1D4,
+       AMDGPU_DOORBELL_LAYOUT1_VCN_END                 = 0x1E8,
 
        AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP            = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START,
        AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP             = AMDGPU_DOORBELL_LAYOUT1_VCN_END,
 
-       AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT          = 0x1D4,
+       AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT          = 0x1E8,
        AMDGPU_DOORBELL_LAYOUT1_INVALID                 = 0xFFFF
-} AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1;
+};
 
 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
 
+/*
+ * GPU doorbell aperture helpers function.
+ */
+int amdgpu_doorbell_init(struct amdgpu_device *adev);
+void amdgpu_doorbell_fini(struct amdgpu_device *adev);
+int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev);
+uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,
+                                     struct amdgpu_bo *db_bo,
+                                     uint32_t doorbell_index,
+                                     uint32_t db_size);
+
 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))