Merge drm/drm-next into drm-intel-next

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_object.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index b4c8e5d5c763cd5416b712e60c3a7ec2a10ed44a..ac1bb5089260483c37b4488f6799a84c8d61c99e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -523,7 +523,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
        };
        struct amdgpu_bo *bo;
        unsigned long page_align, size = bp->size;
-       size_t acc_size;
        int r;
 
        /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
@@ -546,9 +545,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 
        *bo_ptr = NULL;
 
-       acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
-                                      sizeof(struct amdgpu_bo));
-
        bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
        if (bo == NULL)
                return -ENOMEM;
@@ -577,8 +573,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
                bo->tbo.priority = 1;
 
        r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
-                                &bo->placement, page_align, &ctx, acc_size,
-                                NULL, bp->resv, &amdgpu_bo_destroy);
+                                &bo->placement, page_align, &ctx,  NULL,
+                                bp->resv, &amdgpu_bo_destroy);
        if (unlikely(r != 0))
                return r;
 
@@ -787,7 +783,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
        if (r < 0)
                return r;
 
-       r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
+       r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.mem.num_pages, &bo->kmap);
        if (r)
                return r;
 
@@ -911,10 +907,16 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 
        if (bo->tbo.pin_count) {
                uint32_t mem_type = bo->tbo.mem.mem_type;
+               uint32_t mem_flags = bo->tbo.mem.placement;
 
                if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
                        return -EINVAL;
 
+               if ((mem_type == TTM_PL_VRAM) &&
+                   (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
+                   !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
+                       return -EINVAL;
+
                ttm_bo_pin(&bo->tbo);
 
                if (max_offset != 0) {
@@ -930,7 +932,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
        if (bo->tbo.base.import_attach)
                dma_buf_pin(bo->tbo.base.import_attach);
 
-       bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
        /* force to pin into visible video ram */
        if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
                bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
@@ -983,6 +984,7 @@ error:
  */
 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
 {
+       bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
        return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
 }
 
@@ -1059,13 +1061,17 @@ static const char *amdgpu_vram_names[] = {
  */
 int amdgpu_bo_init(struct amdgpu_device *adev)
 {
-       /* reserve PAT memory space to WC for VRAM */
-       arch_io_reserve_memtype_wc(adev->gmc.aper_base,
-                                  adev->gmc.aper_size);
+       /* On A+A platform, VRAM can be mapped as WB */
+       if (!adev->gmc.xgmi.connected_to_cpu) {
+               /* reserve PAT memory space to WC for VRAM */
+               arch_io_reserve_memtype_wc(adev->gmc.aper_base,
+                               adev->gmc.aper_size);
+
+               /* Add an MTRR for the VRAM */
+               adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
+                               adev->gmc.aper_size);
+       }
 
-       /* Add an MTRR for the VRAM */
-       adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
-                                             adev->gmc.aper_size);
        DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
                 adev->gmc.mc_vram_size >> 20,
                 (unsigned long long)adev->gmc.aper_size >> 20);
@@ -1083,8 +1089,10 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
 void amdgpu_bo_fini(struct amdgpu_device *adev)
 {
        amdgpu_ttm_fini(adev);
-       arch_phys_wc_del(adev->gmc.vram_mtrr);
-       arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+       if (!adev->gmc.xgmi.connected_to_cpu) {
+               arch_phys_wc_del(adev->gmc.vram_mtrr);
+               arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+       }
 }
 
 /**