Merge tag 'irq-urgent-2025-02-08' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_kms.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 016a6f6c4267b44b8a02f2b7424a50e792f46e7c..98528ee94c15a13e72ff4c0fb45a9519d504377c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -846,7 +846,7 @@ out:
        case AMDGPU_INFO_DEV_INFO: {
                struct drm_amdgpu_info_device *dev_info;
                uint64_t vm_size;
-               uint32_t pcie_gen_mask;
+               uint32_t pcie_gen_mask, pcie_width_mask;
 
                dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
                if (!dev_info)
@@ -934,15 +934,18 @@ out:
                dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 
                /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
-               pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
+               pcie_gen_mask = adev->pm.pcie_gen_mask &
+                       (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT);
+               pcie_width_mask = adev->pm.pcie_mlw_mask &
+                       (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT);
                dev_info->pcie_gen = fls(pcie_gen_mask);
                dev_info->pcie_num_lanes =
-                       adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
-                       adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
-                       adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
-                       adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
-                       adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
-                       adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
+                       pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
+                       pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
+                       pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
+                       pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
+                       pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
+                       pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 
                dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
                dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;