Merge branch 'upstream' of git://electric-eye.fr.zoreil.com/home/romieu/linux-2.6...

[linux.git] / include / asm-mips / pgtable-32.h

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 8d66303eabc4f763c114a252be3f7d4f5b260114..4b26d8528133f6a7c8c6289622cd1428d6d3257b 100644 (file)
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -9,7 +9,6 @@
 #ifndef _ASM_PGTABLE_32_H
 #define _ASM_PGTABLE_32_H
 
-#include <linux/config.h>
 #include <asm/addrspace.h>
 #include <asm/page.h>
 
@@ -43,10 +42,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  * works even with the cache aliasing problem the R4k and above have.
  */
 
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define PMD_SIZE       (1UL << PMD_SHIFT)
-#define PMD_MASK       (~(PMD_SIZE-1))
-
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
 #ifdef CONFIG_64BIT_PHYS_ADDR
 #define PGDIR_SHIFT    21
@@ -78,7 +73,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 #define USER_PTRS_PER_PGD      (0x80000000UL/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS     0
 
-#define VMALLOC_START     KSEG2
+#define VMALLOC_START     MAP_BASE
 
 #ifdef CONFIG_HIGHMEM
 # define VMALLOC_END   (PKMAP_BASE-2*PAGE_SIZE)
@@ -120,7 +115,7 @@ static inline void pmd_clear(pmd_t *pmdp)
        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 #define pte_page(x)            pfn_to_page(pte_pfn(x))
 #define pte_pfn(x)             ((unsigned long)((x).pte_high >> 6))
 static inline pte_t
@@ -141,17 +136,18 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define pfn_pte(pfn, prot)     __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 #else
 #define pte_pfn(x)             ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)     __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pfn_pte(pfn, prot)     __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
 
 #define __pgd_offset(address)  pgd_index(address)
+#define __pud_offset(address)  (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 #define __pmd_offset(address)  (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
-#define pgd_index(address)     ((address) >> PGDIR_SHIFT)
+#define pgd_index(address)     (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 
 /* to find an entry in a page-table-directory */
 #define pgd_offset(mm,addr)    ((mm)->pgd + pgd_index(addr))
@@ -180,48 +176,67 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
        ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
 
 /*
- * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset
- * into this range:
+ * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
  */
-#define PTE_FILE_MAX_BITS      27
+#define PTE_FILE_MAX_BITS      28
 
-#define pte_to_pgoff(_pte) \
-       ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 ))
+#define pte_to_pgoff(_pte)     ((((_pte).pte >> 1 ) & 0x07) | \
+                                (((_pte).pte >> 2 ) & 0x38) | \
+                                (((_pte).pte >> 10) <<  6 ))
 
-#define pgoff_to_pte(off) \
-       ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE })
+#define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x07) << 1 ) | \
+                                          (((off) & 0x38) << 2 ) | \
+                                          (((off) >>  6 ) << 10) | \
+                                          _PAGE_FILE })
 
 #else
 
 /* Swap entries must have VALID and GLOBAL bits cleared. */
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __swp_type(x)          (((x).val >> 2) & 0x1f)
+#define __swp_offset(x)         ((x).val >> 7)
+#define __swp_entry(type,offset)       \
+               ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+#else
 #define __swp_type(x)          (((x).val >> 8) & 0x1f)
-#define __swp_offset(x)                ((x).val >> 13)
+#define __swp_offset(x)         ((x).val >> 13)
 #define __swp_entry(type,offset)       \
-               ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
+               ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 /*
- * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
- * into this range:
+ * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
  */
-#define PTE_FILE_MAX_BITS      27
+#define PTE_FILE_MAX_BITS      30
 
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-       /* fixme */
-#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
-#define pgoff_to_pte(off) \
-       ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
+#define pte_to_pgoff(_pte)     ((_pte).pte_high >> 2)
+#define pgoff_to_pte(off)      ((pte_t) { _PAGE_FILE, (off) << 2 })
 
 #else
-#define pte_to_pgoff(_pte) \
-       ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
+/*
+ * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
+ */
+#define PTE_FILE_MAX_BITS      28
+
+#define pte_to_pgoff(_pte)     ((((_pte).pte >> 1) & 0x7) | \
+                                (((_pte).pte >> 2) & 0x8) | \
+                                (((_pte).pte >> 8) <<  4))
 
-#define pgoff_to_pte(off) \
-       ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
+#define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x7) << 1) | \
+                                          (((off) & 0x8) << 2) | \
+                                          (((off) >>  4) << 8) | \
+                                          _PAGE_FILE })
 #endif
 
 #endif
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x)  ((pte_t) { 0, (x).val })
+#else
 #define __pte_to_swp_entry(pte)        ((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
+#endif
 
 #endif /* _ASM_PGTABLE_32_H */