Merge some cs42l42 patches into asoc-5.15

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ib.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c16f1f0d35e111b2a70cf04dcb18b8..ec65ab0ddf890e5dd9decfc87456f800a686a885 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -130,7 +130,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_ib *ib = &ibs[0];
        struct dma_fence *tmp = NULL;
-       bool skip_preamble, need_ctx_switch;
+       bool need_ctx_switch;
        unsigned patch_offset = ~0;
        struct amdgpu_vm *vm;
        uint64_t fence_ctx;
@@ -214,20 +214,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        if (job && ring->funcs->init_cond_exec)
                patch_offset = amdgpu_ring_init_cond_exec(ring);
 
-#ifdef CONFIG_X86_64
-       if (!(adev->flags & AMD_IS_APU))
-#endif
-       {
-               if (ring->funcs->emit_hdp_flush)
-                       amdgpu_ring_emit_hdp_flush(ring);
-               else
-                       amdgpu_asic_flush_hdp(adev, ring);
-       }
+       amdgpu_device_flush_hdp(adev, ring);
 
        if (need_ctx_switch)
                status |= AMDGPU_HAVE_CTX_SWITCH;
 
-       skip_preamble = ring->current_ctx == fence_ctx;
        if (job && ring->funcs->emit_cntxcntl) {
                status |= job->preamble_status;
                status |= job->preemption_status;
@@ -245,14 +236,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        for (i = 0; i < num_ibs; ++i) {
                ib = &ibs[i];
 
-               /* drop preamble IBs if we don't have a context switch */
-               if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-                   skip_preamble &&
-                   !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
-                   !amdgpu_mcbp &&
-                   !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
-                       continue;
-
                if (job && ring->funcs->emit_frame_cntl) {
                        if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
                                amdgpu_ring_emit_frame_cntl(ring, false, secure);
@@ -268,10 +251,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        if (job && ring->funcs->emit_frame_cntl)
                amdgpu_ring_emit_frame_cntl(ring, false, secure);
 
-#ifdef CONFIG_X86_64
-       if (!(adev->flags & AMD_IS_APU))
-#endif
-               amdgpu_asic_invalidate_hdp(adev, ring);
+       amdgpu_device_invalidate_hdp(adev, ring);
 
        if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
                fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
@@ -328,7 +308,7 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev)
 
        for (i = 0; i < AMDGPU_IB_POOL_MAX; i++) {
                if (i == AMDGPU_IB_POOL_DIRECT)
-                       size = PAGE_SIZE * 2;
+                       size = PAGE_SIZE * 6;
                else
                        size = AMDGPU_IB_POOL_SIZE;