drm/nouveau/kms: Don't change EDID when it hasn't actually changed

[linux.git] / drivers / fpga / xilinx-spi.c

diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
index 272ee0c22822e103a6617d8daeb1a91d900d63e7..2967aa2a74e2206bfbf88a2266dd736b21225851 100644 (file)
--- a/drivers/fpga/xilinx-spi.c
+++ b/drivers/fpga/xilinx-spi.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Xilinx Spartan6 Slave Serial SPI Driver
+ * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
  *
  * Copyright (C) 2017 DENX Software Engineering
  *
@@ -23,6 +23,7 @@
 struct xilinx_spi_conf {
        struct spi_device *spi;
        struct gpio_desc *prog_b;
+       struct gpio_desc *init_b;
        struct gpio_desc *done;
 };
 
@@ -36,13 +37,45 @@ static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
        return FPGA_MGR_STATE_UNKNOWN;
 }
 
+/**
+ * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
+ * a given delay if the pin is unavailable
+ *
+ * @mgr:        The FPGA manager object
+ * @value:      Value INIT_B to wait for (1 = asserted = low)
+ * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
+ *
+ * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
+ * too much time passed waiting for that. If no INIT_B GPIO is available
+ * then always return 0.
+ */
+static int wait_for_init_b(struct fpga_manager *mgr, int value,
+                          unsigned long alt_udelay)
+{
+       struct xilinx_spi_conf *conf = mgr->priv;
+       unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+
+       if (conf->init_b) {
+               while (time_before(jiffies, timeout)) {
+                       /* dump_state(conf, "wait for init_d .."); */
+                       if (gpiod_get_value(conf->init_b) == value)
+                               return 0;
+                       usleep_range(100, 400);
+               }
+               return -ETIMEDOUT;
+       }
+
+       udelay(alt_udelay);
+
+       return 0;
+}
+
 static int xilinx_spi_write_init(struct fpga_manager *mgr,
                                 struct fpga_image_info *info,
                                 const char *buf, size_t count)
 {
        struct xilinx_spi_conf *conf = mgr->priv;
-       const size_t prog_latency_7500us = 7500;
-       const size_t prog_pulse_1us = 1;
+       int err;
 
        if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
                dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
@@ -51,17 +84,28 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr,
 
        gpiod_set_value(conf->prog_b, 1);
 
-       udelay(prog_pulse_1us); /* min is 500 ns */
+       err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
+       if (err) {
+               dev_err(&mgr->dev, "INIT_B pin did not go low\n");
+               gpiod_set_value(conf->prog_b, 0);
+               return err;
+       }
 
        gpiod_set_value(conf->prog_b, 0);
 
+       err = wait_for_init_b(mgr, 0, 0);
+       if (err) {
+               dev_err(&mgr->dev, "INIT_B pin did not go high\n");
+               return err;
+       }
+
        if (gpiod_get_value(conf->done)) {
                dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
                return -EIO;
        }
 
        /* program latency */
-       usleep_range(prog_latency_7500us, prog_latency_7500us + 100);
+       usleep_range(7500, 7600);
        return 0;
 }
 
@@ -156,6 +200,13 @@ static int xilinx_spi_probe(struct spi_device *spi)
                return PTR_ERR(conf->prog_b);
        }
 
+       conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
+       if (IS_ERR(conf->init_b)) {
+               dev_err(&spi->dev, "Failed to get INIT_B gpio: %ld\n",
+                       PTR_ERR(conf->init_b));
+               return PTR_ERR(conf->init_b);
+       }
+
        conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
        if (IS_ERR(conf->done)) {
                dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",