Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mes.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 0c546245793b9c292851db1098ce14c2f27fe734..e9091ebfe230db24072a7abc0dc9ff1effd9267f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -21,6 +21,8 @@
  *
  */
 
+#include <linux/firmware.h>
+
 #include "amdgpu_mes.h"
 #include "amdgpu.h"
 #include "soc15_common.h"
@@ -922,6 +924,43 @@ error:
        return r;
 }
 
+int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
+                               uint64_t process_context_addr,
+                               uint32_t spi_gdbg_per_vmid_cntl,
+                               const uint32_t *tcp_watch_cntl,
+                               uint32_t flags,
+                               bool trap_en)
+{
+       struct mes_misc_op_input op_input = {0};
+       int r;
+
+       if (!adev->mes.funcs->misc_op) {
+               DRM_ERROR("mes set shader debugger is not supported!\n");
+               return -EINVAL;
+       }
+
+       op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
+       op_input.set_shader_debugger.process_context_addr = process_context_addr;
+       op_input.set_shader_debugger.flags.u32all = flags;
+       op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl;
+       memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
+                       sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
+
+       if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
+                       AMDGPU_MES_API_VERSION_SHIFT) >= 14)
+               op_input.set_shader_debugger.trap_en = trap_en;
+
+       amdgpu_mes_lock(&adev->mes);
+
+       r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
+       if (r)
+               DRM_ERROR("failed to set_shader_debugger\n");
+
+       amdgpu_mes_unlock(&adev->mes);
+
+       return r;
+}
+
 static void
 amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
                               struct amdgpu_ring *ring,
@@ -1102,6 +1141,11 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
                            &ctx_data->meta_data_obj,
                            &ctx_data->meta_data_mc_addr,
                            &ctx_data->meta_data_ptr);
+       if (r) {
+               dev_warn(adev->dev, "(%d) create CTX bo failed\n", r);
+               return r;
+       }
+
        if (!ctx_data->meta_data_obj)
                return -ENOMEM;
 
@@ -1298,14 +1342,9 @@ static int amdgpu_mes_test_queues(struct amdgpu_ring **added_rings)
                if (!ring)
                        continue;
 
-               r = amdgpu_ring_test_ring(ring);
-               if (r) {
-                       DRM_DEV_ERROR(ring->adev->dev,
-                                     "ring %s test failed (%d)\n",
-                                     ring->name, r);
+               r = amdgpu_ring_test_helper(ring);
+               if (r)
                        return r;
-               } else
-                       DRM_INFO("ring %s test pass\n", ring->name);
 
                r = amdgpu_ring_test_ib(ring, 1000 * 10);
                if (r) {
@@ -1326,12 +1365,9 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev)
        struct amdgpu_mes_ctx_data ctx_data = {0};
        struct amdgpu_ring *added_rings[AMDGPU_MES_CTX_MAX_RINGS] = { NULL };
        int gang_ids[3] = {0};
-       int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX,
-                                  AMDGPU_MES_CTX_MAX_GFX_RINGS},
-                                { AMDGPU_RING_TYPE_COMPUTE,
-                                  AMDGPU_MES_CTX_MAX_COMPUTE_RINGS},
-                                { AMDGPU_RING_TYPE_SDMA,
-                                  AMDGPU_MES_CTX_MAX_SDMA_RINGS } };
+       int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX, 1 },
+                                { AMDGPU_RING_TYPE_COMPUTE, 1 },
+                                { AMDGPU_RING_TYPE_SDMA, 1} };
        int i, r, pasid, k = 0;
 
        pasid = amdgpu_pasid_alloc(16);
@@ -1423,3 +1459,78 @@ error_pasid:
        kfree(vm);
        return 0;
 }
+
+int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
+{
+       const struct mes_firmware_header_v1_0 *mes_hdr;
+       struct amdgpu_firmware_info *info;
+       char ucode_prefix[30];
+       char fw_name[40];
+       bool need_retry = false;
+       int r;
+
+       amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix,
+                                      sizeof(ucode_prefix));
+       if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) {
+               snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin",
+                        ucode_prefix,
+                        pipe == AMDGPU_MES_SCHED_PIPE ? "_2" : "1");
+               need_retry = true;
+       } else {
+               snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin",
+                        ucode_prefix,
+                        pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1");
+       }
+
+       r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], fw_name);
+       if (r && need_retry && pipe == AMDGPU_MES_SCHED_PIPE) {
+               snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
+                        ucode_prefix);
+               DRM_INFO("try to fall back to %s\n", fw_name);
+               r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe],
+                                        fw_name);
+       }
+
+       if (r)
+               goto out;
+
+       mes_hdr = (const struct mes_firmware_header_v1_0 *)
+               adev->mes.fw[pipe]->data;
+       adev->mes.uc_start_addr[pipe] =
+               le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
+               ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
+       adev->mes.data_start_addr[pipe] =
+               le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
+               ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
+
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+               int ucode, ucode_data;
+
+               if (pipe == AMDGPU_MES_SCHED_PIPE) {
+                       ucode = AMDGPU_UCODE_ID_CP_MES;
+                       ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
+               } else {
+                       ucode = AMDGPU_UCODE_ID_CP_MES1;
+                       ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
+               }
+
+               info = &adev->firmware.ucode[ucode];
+               info->ucode_id = ucode;
+               info->fw = adev->mes.fw[pipe];
+               adev->firmware.fw_size +=
+                       ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
+                             PAGE_SIZE);
+
+               info = &adev->firmware.ucode[ucode_data];
+               info->ucode_id = ucode_data;
+               info->fw = adev->mes.fw[pipe];
+               adev->firmware.fw_size +=
+                       ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
+                             PAGE_SIZE);
+       }
+
+       return 0;
+out:
+       amdgpu_ucode_release(&adev->mes.fw[pipe]);
+       return r;
+}