Merge tag 'iommu-updates-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 27d8dd77860dd3a9b29a5c2aa91fc6fdb8986f46..b455da4877829e57b76178ed2300959c4dade7f4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -574,10 +574,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the power state and the clock information for those levels.
  *
  * To manually adjust these states, first select manual using
  * the power state and the clock information for those levels.
  *
  * To manually adjust these states, first select manual using

- * power_dpm_force_performance_level.  Writing a string of the level
- * numbers to the file will select which levels you want to enable.
- * E.g., writing 456 to the file will enable levels 4, 5, and 6.
- *
+ * power_dpm_force_performance_level.
+ * Secondly,Enter a new value for each level by inputing a string that
+ * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
+ * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.

  */
 
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
  */
 
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,


@@ -602,23 +602,27 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
        struct amdgpu_device *adev = ddev->dev_private;
        int ret;
        long level;
        struct amdgpu_device *adev = ddev->dev_private;
        int ret;
        long level;

-       uint32_t i, mask = 0;
-       char sub_str[2];
+       uint32_t mask = 0;
+       char *sub_str = NULL;
+       char *tmp;
+       char buf_cpy[count];
+       const char delimiter[3] = {' ', '\n', '\0'};

 
 

-       for (i = 0; i < strlen(buf); i++) {
-               if (*(buf + i) == '\n')
-                       continue;
-               sub_str[0] = *(buf + i);
-               sub_str[1] = '\0';
-               ret = kstrtol(sub_str, 0, &level);
+       memcpy(buf_cpy, buf, count+1);
+       tmp = buf_cpy;
+       while (tmp[0]) {
+               sub_str =  strsep(&tmp, delimiter);
+               if (strlen(sub_str)) {
+                       ret = kstrtol(sub_str, 0, &level);

 
 

-               if (ret) {
-                       count = -EINVAL;
-                       goto fail;
-               }
-               mask |= 1 << level;
+                       if (ret) {
+                               count = -EINVAL;
+                               goto fail;
+                       }
+                       mask |= 1 << level;
+               } else
+                       break;

        }
        }

-

        if (adev->powerplay.pp_funcs->force_clock_level)
                amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 
        if (adev->powerplay.pp_funcs->force_clock_level)
                amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 


@@ -648,21 +652,26 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
        struct amdgpu_device *adev = ddev->dev_private;
        int ret;
        long level;
        struct amdgpu_device *adev = ddev->dev_private;
        int ret;
        long level;

-       uint32_t i, mask = 0;
-       char sub_str[2];
+       uint32_t mask = 0;
+       char *sub_str = NULL;
+       char *tmp;
+       char buf_cpy[count];
+       const char delimiter[3] = {' ', '\n', '\0'};

 
 

-       for (i = 0; i < strlen(buf); i++) {
-               if (*(buf + i) == '\n')
-                       continue;
-               sub_str[0] = *(buf + i);
-               sub_str[1] = '\0';
-               ret = kstrtol(sub_str, 0, &level);
+       memcpy(buf_cpy, buf, count+1);
+       tmp = buf_cpy;
+       while (tmp[0]) {
+               sub_str =  strsep(&tmp, delimiter);
+               if (strlen(sub_str)) {
+                       ret = kstrtol(sub_str, 0, &level);

 
 

-               if (ret) {
-                       count = -EINVAL;
-                       goto fail;
-               }
-               mask |= 1 << level;
+                       if (ret) {
+                               count = -EINVAL;
+                               goto fail;
+                       }
+                       mask |= 1 << level;
+               } else
+                       break;

        }
        if (adev->powerplay.pp_funcs->force_clock_level)
                amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
        }
        if (adev->powerplay.pp_funcs->force_clock_level)
                amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);


@@ -693,21 +702,27 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
        struct amdgpu_device *adev = ddev->dev_private;
        int ret;
        long level;
        struct amdgpu_device *adev = ddev->dev_private;
        int ret;
        long level;

-       uint32_t i, mask = 0;
-       char sub_str[2];
+       uint32_t mask = 0;
+       char *sub_str = NULL;
+       char *tmp;
+       char buf_cpy[count];
+       const char delimiter[3] = {' ', '\n', '\0'};

 
 

-       for (i = 0; i < strlen(buf); i++) {
-               if (*(buf + i) == '\n')
-                       continue;
-               sub_str[0] = *(buf + i);
-               sub_str[1] = '\0';
-               ret = kstrtol(sub_str, 0, &level);
+       memcpy(buf_cpy, buf, count+1);
+       tmp = buf_cpy;

 
 

-               if (ret) {
-                       count = -EINVAL;
-                       goto fail;
-               }
-               mask |= 1 << level;
+       while (tmp[0]) {
+               sub_str =  strsep(&tmp, delimiter);
+               if (strlen(sub_str)) {
+                       ret = kstrtol(sub_str, 0, &level);
+
+                       if (ret) {
+                               count = -EINVAL;
+                               goto fail;
+                       }
+                       mask |= 1 << level;
+               } else
+                       break;

        }
        if (adev->powerplay.pp_funcs->force_clock_level)
                amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
        }
        if (adev->powerplay.pp_funcs->force_clock_level)
                amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);


@@ -1349,19 +1364,14 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
        struct amdgpu_device *adev = dev_get_drvdata(dev);
        umode_t effective_mode = attr->mode;
 
        struct amdgpu_device *adev = dev_get_drvdata(dev);
        umode_t effective_mode = attr->mode;
 

-       /* handle non-powerplay limitations */
-       if (!adev->powerplay.pp_handle) {
-               /* Skip fan attributes if fan is not present */
-               if (adev->pm.no_fan &&
-                   (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
-                    attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
-                    attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
-                    attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
-                       return 0;
-               /* requires powerplay */
-               if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
-                       return 0;
-       }
+
+       /* Skip fan attributes if fan is not present */
+       if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
+           attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
+           attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
+           attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
+           attr == &sensor_dev_attr_fan1_input.dev_attr.attr))
+               return 0;

 
        /* Skip limit attributes if DPM is not enabled */
        if (!adev->pm.dpm_enabled &&
 
        /* Skip limit attributes if DPM is not enabled */
        if (!adev->pm.dpm_enabled &&


@@ -1868,26 +1878,26 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
                        amdgpu_fence_wait_empty(ring);
        }
 
                        amdgpu_fence_wait_empty(ring);
        }
 

-       if (!amdgpu_device_has_dc_support(adev)) {
-               mutex_lock(&adev->pm.mutex);
-               amdgpu_dpm_get_active_displays(adev);
-               adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
-               adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
-               adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
-               /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
-               if (adev->pm.pm_display_cfg.vrefresh > 120)
-                       adev->pm.pm_display_cfg.min_vblank_time = 0;
-               if (adev->powerplay.pp_funcs->display_configuration_change)
-                       adev->powerplay.pp_funcs->display_configuration_change(
-                                                       adev->powerplay.pp_handle,
-                                                       &adev->pm.pm_display_cfg);
-               mutex_unlock(&adev->pm.mutex);
-       }
-

        if (adev->powerplay.pp_funcs->dispatch_tasks) {
        if (adev->powerplay.pp_funcs->dispatch_tasks) {

+               if (!amdgpu_device_has_dc_support(adev)) {
+                       mutex_lock(&adev->pm.mutex);
+                       amdgpu_dpm_get_active_displays(adev);
+                       adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
+                       adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
+                       adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
+                       /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
+                       if (adev->pm.pm_display_cfg.vrefresh > 120)
+                               adev->pm.pm_display_cfg.min_vblank_time = 0;
+                       if (adev->powerplay.pp_funcs->display_configuration_change)
+                               adev->powerplay.pp_funcs->display_configuration_change(
+                                                               adev->powerplay.pp_handle,
+                                                               &adev->pm.pm_display_cfg);
+                       mutex_unlock(&adev->pm.mutex);
+               }

                amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
        } else {
                mutex_lock(&adev->pm.mutex);
                amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
        } else {
                mutex_lock(&adev->pm.mutex);

+               amdgpu_dpm_get_active_displays(adev);

                /* update battery/ac status */
                if (power_supply_is_system_supplied() > 0)
                        adev->pm.dpm.ac_power = true;
                /* update battery/ac status */
                if (power_supply_is_system_supplied() > 0)
                        adev->pm.dpm.ac_power = true;