drm/nouveau/kms: Don't change EDID when it hasn't actually changed

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_virt.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index f0128f745bd2847c2b7aaee89a3ee7a12a4a2271..f826945989c727a1a5b23fef67e7541e5d62c86f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -30,6 +30,17 @@
 #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
 #define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
 
+/* all asic after AI use this offset */
+#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
+/* tonga/fiji use this offset */
+#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
+
+enum amdgpu_sriov_vf_mode {
+       SRIOV_VF_MODE_BARE_METAL = 0,
+       SRIOV_VF_MODE_ONE_VF,
+       SRIOV_VF_MODE_MULTI_VF,
+};
+
 struct amdgpu_mm_table {
        struct amdgpu_bo        *bo;
        uint32_t                *cpu_addr;
@@ -54,6 +65,7 @@ struct amdgpu_vf_error_buffer {
 struct amdgpu_virt_ops {
        int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
        int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
+       int (*req_init_data)(struct amdgpu_device *adev);
        int (*reset_gpu)(struct amdgpu_device *adev);
        int (*wait_reset)(struct amdgpu_device *adev);
        void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
@@ -83,6 +95,8 @@ enum AMDGIM_FEATURE_FLAG {
        AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
        /* VRAM LOST by GIM */
        AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
+       /* MM bandwidth */
+       AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
        /* PP ONE VF MODE in GIM */
        AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
 };
@@ -129,19 +143,27 @@ struct  amdgim_pf2vf_info_v2 {
        uint32_t vce_enc_max_pixels_count;
        /* 16x16 pixels/sec, codec independent */
        uint32_t vce_enc_max_bandwidth;
+       /* Bad pages block position in BYTE */
+       uint32_t bp_block_offset_L;
+       uint32_t bp_block_offset_H;
+       /* Bad pages block size in BYTE */
+       uint32_t bp_block_size;
        /* MEC FW position in kb from the start of VF visible frame buffer */
-       uint64_t mecfw_kboffset;
+       uint32_t mecfw_kboffset_L;
+       uint32_t mecfw_kboffset_H;
        /* MEC FW size in KB */
        uint32_t mecfw_ksize;
        /* UVD FW position in kb from the start of VF visible frame buffer */
-       uint64_t uvdfw_kboffset;
+       uint32_t uvdfw_kboffset_L;
+       uint32_t uvdfw_kboffset_H;
        /* UVD FW size in KB */
        uint32_t uvdfw_ksize;
        /* VCE FW position in kb from the start of VF visible frame buffer */
-       uint64_t vcefw_kboffset;
+       uint32_t vcefw_kboffset_L;
+       uint32_t vcefw_kboffset_H;
        /* VCE FW size in KB */
        uint32_t vcefw_ksize;
-       uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 3)];
+       uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (18 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 0)];
 } __aligned(4);
 
 
@@ -240,6 +262,17 @@ typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
                } \
        } while (0)
 
+struct amdgpu_virt_ras_err_handler_data {
+       /* point to bad page records array */
+       struct eeprom_table_record *bps;
+       /* point to reserved bo array */
+       struct amdgpu_bo **bps_bo;
+       /* the count of entries */
+       int count;
+       /* last reserved entry's index + 1 */
+       int last_reserved;
+};
+
 /* GPU virtualization */
 struct amdgpu_virt {
        uint32_t                        caps;
@@ -256,6 +289,10 @@ struct amdgpu_virt {
        struct amdgpu_virt_fw_reserve   fw_reserve;
        uint32_t gim_feature;
        uint32_t reg_access_mode;
+       int req_init_data_ver;
+       bool tdr_debug;
+       struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
+       bool ras_init_done;
 };
 
 #define amdgpu_sriov_enabled(adev) \
@@ -287,6 +324,10 @@ static inline bool is_virtual_machine(void)
 
 #define amdgpu_sriov_is_pp_one_vf(adev) \
        ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
+#define amdgpu_sriov_is_debug(adev) \
+       ((!adev->in_gpu_reset) && adev->virt.tdr_debug)
+#define amdgpu_sriov_is_normal(adev) \
+       ((!adev->in_gpu_reset) && (!adev->virt.tdr_debug))
 
 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
@@ -296,11 +337,20 @@ void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
+void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
 int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
                                        unsigned int key,
                                        unsigned int chksum);
+void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
+void amdgpu_detect_virtualization(struct amdgpu_device *adev);
+
+bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
+int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
+void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
+
+enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
 #endif