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iov_iter: use bvec iterator to implement iterate_bvec()
[linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4e1e398acab1482a41d97a9e1b39a3c6840bd90a..7fb1da4e7fc349dfdfe26bb32dd7e97192b2ec04 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -492,10 +492,9 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
                              state, rewrites);
 }
 
-static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
+static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 {
-       uint32_t val;
-       uint32_t mask;
+       u32 mask;
 
        mask = DC_STATE_EN_UPTO_DC5;
        if (IS_BROXTON(dev_priv))
@@ -503,10 +502,30 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
        else
                mask |= DC_STATE_EN_UPTO_DC6;
 
+       return mask;
+}
+
+void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
+{
+       u32 val;
+
+       val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
+
+       DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
+                     dev_priv->csr.dc_state, val);
+       dev_priv->csr.dc_state = val;
+}
+
+static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
+{
+       uint32_t val;
+       uint32_t mask;
+
        if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
                state &= dev_priv->csr.allowed_dc_mask;
 
        val = I915_READ(DC_STATE_EN);
+       mask = gen9_dc_mask(dev_priv);
        DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
                      val & mask, state);
 
@@ -563,7 +582,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
        assert_csr_loaded(dev_priv);
 }
 
-static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
+void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
        assert_can_enable_dc5(dev_priv);
 
@@ -626,7 +645,8 @@ gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
         * other request bits to be set, so WARN for those.
         */
        if (power_well_id == SKL_DISP_PW_1 ||
-           (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
+           ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+            power_well_id == SKL_DISP_PW_MISC_IO))
                DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
                                 "by DMC\n", power_well->name);
        else
@@ -1592,33 +1612,56 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        intel_runtime_pm_put(dev_priv);
 }
 
-#define HSW_ALWAYS_ON_POWER_DOMAINS (                  \
-       BIT(POWER_DOMAIN_PIPE_A) |                      \
-       BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
-       BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
+#define HSW_DISPLAY_POWER_DOMAINS (                    \
+       BIT(POWER_DOMAIN_PIPE_B) |                      \
+       BIT(POWER_DOMAIN_PIPE_C) |                      \
+       BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
+       BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
+       BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
+       BIT(POWER_DOMAIN_TRANSCODER_A) |                \
+       BIT(POWER_DOMAIN_TRANSCODER_B) |                \
+       BIT(POWER_DOMAIN_TRANSCODER_C) |                \
        BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
        BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
        BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
-       BIT(POWER_DOMAIN_PORT_CRT) |                    \
-       BIT(POWER_DOMAIN_PLLS) |                        \
-       BIT(POWER_DOMAIN_AUX_A) |                       \
-       BIT(POWER_DOMAIN_AUX_B) |                       \
-       BIT(POWER_DOMAIN_AUX_C) |                       \
-       BIT(POWER_DOMAIN_AUX_D) |                       \
-       BIT(POWER_DOMAIN_GMBUS) |                       \
-       BIT(POWER_DOMAIN_INIT))
-#define HSW_DISPLAY_POWER_DOMAINS (                            \
-       (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
+       BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
+       BIT(POWER_DOMAIN_VGA) |                         \
+       BIT(POWER_DOMAIN_AUDIO) |                       \
        BIT(POWER_DOMAIN_INIT))
 
-#define BDW_ALWAYS_ON_POWER_DOMAINS (                  \
-       HSW_ALWAYS_ON_POWER_DOMAINS |                   \
-       BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
-#define BDW_DISPLAY_POWER_DOMAINS (                            \
-       (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
+#define BDW_DISPLAY_POWER_DOMAINS (                    \
+       BIT(POWER_DOMAIN_PIPE_B) |                      \
+       BIT(POWER_DOMAIN_PIPE_C) |                      \
+       BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
+       BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
+       BIT(POWER_DOMAIN_TRANSCODER_A) |                \
+       BIT(POWER_DOMAIN_TRANSCODER_B) |                \
+       BIT(POWER_DOMAIN_TRANSCODER_C) |                \
+       BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
+       BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
+       BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
+       BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
+       BIT(POWER_DOMAIN_VGA) |                         \
+       BIT(POWER_DOMAIN_AUDIO) |                       \
        BIT(POWER_DOMAIN_INIT))
 
-#define VLV_DISPLAY_POWER_DOMAINS      POWER_DOMAIN_MASK
+#define VLV_DISPLAY_POWER_DOMAINS (            \
+       BIT(POWER_DOMAIN_PIPE_A) |              \
+       BIT(POWER_DOMAIN_PIPE_B) |              \
+       BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+       BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+       BIT(POWER_DOMAIN_TRANSCODER_A) |        \
+       BIT(POWER_DOMAIN_TRANSCODER_B) |        \
+       BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
+       BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
+       BIT(POWER_DOMAIN_PORT_DSI) |            \
+       BIT(POWER_DOMAIN_PORT_CRT) |            \
+       BIT(POWER_DOMAIN_VGA) |                 \
+       BIT(POWER_DOMAIN_AUDIO) |               \
+       BIT(POWER_DOMAIN_AUX_B) |               \
+       BIT(POWER_DOMAIN_AUX_C) |               \
+       BIT(POWER_DOMAIN_GMBUS) |               \
+       BIT(POWER_DOMAIN_INIT))
 
 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (                \
        BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
@@ -1648,6 +1691,28 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        BIT(POWER_DOMAIN_AUX_C) |               \
        BIT(POWER_DOMAIN_INIT))
 
+#define CHV_DISPLAY_POWER_DOMAINS (            \
+       BIT(POWER_DOMAIN_PIPE_A) |              \
+       BIT(POWER_DOMAIN_PIPE_B) |              \
+       BIT(POWER_DOMAIN_PIPE_C) |              \
+       BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+       BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+       BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+       BIT(POWER_DOMAIN_TRANSCODER_A) |        \
+       BIT(POWER_DOMAIN_TRANSCODER_B) |        \
+       BIT(POWER_DOMAIN_TRANSCODER_C) |        \
+       BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
+       BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
+       BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
+       BIT(POWER_DOMAIN_PORT_DSI) |            \
+       BIT(POWER_DOMAIN_VGA) |                 \
+       BIT(POWER_DOMAIN_AUDIO) |               \
+       BIT(POWER_DOMAIN_AUX_B) |               \
+       BIT(POWER_DOMAIN_AUX_C) |               \
+       BIT(POWER_DOMAIN_AUX_D) |               \
+       BIT(POWER_DOMAIN_GMBUS) |               \
+       BIT(POWER_DOMAIN_INIT))
+
 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (                \
        BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
        BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
@@ -1832,7 +1897,7 @@ static struct i915_power_well chv_power_wells[] = {
                 * power wells don't actually exist. Pipe A power well is
                 * required for any pipe to work.
                 */
-               .domains = VLV_DISPLAY_POWER_DOMAINS,
+               .domains = CHV_DISPLAY_POWER_DOMAINS,
                .data = PIPE_A,
                .ops = &chv_pipe_power_well_ops,
        },
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